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Fix driver in 5g_usb

This commit is contained in:
TXuian 2024-11-01 14:18:55 +08:00
parent b586bd1247
commit 6632bc08e9
9 changed files with 51 additions and 778 deletions
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30
Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_bsp.c
View File

@ -321,43 +321,21 @@ const struct HAL_CANFD_DEV g_can2Dev =
#endif #endif
#ifdef HAL_GMAC_MODULE_ENABLED #ifdef HAL_GMAC_MODULE_ENABLED
// const struct HAL_GMAC_DEV g_gmac0Dev =
// {
// .pReg = GMAC0,
// .clkID = CLK_MAC0_2TOP,
// .clkGateID = CLK_MAC0_2TOP_GATE,
// .pclkID = PCLK_PHP,
// .pclkGateID = PCLK_GMAC0_GATE,
// .irqNum = GMAC0_IRQn,
// };
const struct HAL_GMAC_DEV g_gmac0Dev = const struct HAL_GMAC_DEV g_gmac0Dev =
{ {
.pReg = GMAC0, .pReg = GMAC0,
.clkID125M = CLK_MAC0_2TOP, .clkID = CLK_MAC0_2TOP,
.clkID50M = CLK_MAC0_2TOP, .clkGateID = CLK_MAC0_2TOP_GATE,
.clkGateID125M = CLK_MAC0_2TOP_GATE,
.clkGateID50M = CLK_MAC0_2TOP_GATE,
.pclkID = PCLK_PHP, .pclkID = PCLK_PHP,
.pclkGateID = PCLK_GMAC0_GATE, .pclkGateID = PCLK_GMAC0_GATE,
.irqNum = GMAC0_IRQn, .irqNum = GMAC0_IRQn,
}; };
// const struct HAL_GMAC_DEV g_gmac1Dev =
// {
// .pReg = GMAC1,
// .clkID = CLK_MAC1_2TOP,
// .clkGateID = CLK_MAC1_2TOP_GATE,
// .pclkID = PCLK_USB,
// .pclkGateID = PCLK_GMAC1_GATE,
// .irqNum = GMAC1_IRQn,
// };
const struct HAL_GMAC_DEV g_gmac1Dev = const struct HAL_GMAC_DEV g_gmac1Dev =
{ {
.pReg = GMAC1, .pReg = GMAC1,
.clkID125M = CLK_MAC1_2TOP, .clkID = CLK_MAC1_2TOP,
.clkID50M = CLK_MAC1_2TOP, .clkGateID = CLK_MAC1_2TOP_GATE,
.clkGateID125M = CLK_MAC1_2TOP_GATE,
.clkGateID50M = CLK_MAC1_2TOP_GATE,
.pclkID = PCLK_USB, .pclkID = PCLK_USB,
.pclkGateID = PCLK_GMAC1_GATE, .pclkGateID = PCLK_GMAC1_GATE,
.irqNum = GMAC1_IRQn, .irqNum = GMAC1_IRQn,

90
Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru.c
View File

@ -115,8 +115,8 @@
#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ) #define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ)
#define CRU_READ(r) (*(volatile uint32_t *)((uintptr_t)(r))) #define CRU_READ(r) (*(volatile uint32_t *)(r))
#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)((uintptr_t)(r)) = ((w) << (16) | (v) << (b))) #define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)(r) = ((w) << (16) | (v) << (b)))
/********************* Private Structure Definition **************************/ /********************* Private Structure Definition **************************/
static struct PLL_CONFIG g_rockchipAutoTable; static struct PLL_CONFIG g_rockchipAutoTable;
@ -147,22 +147,6 @@ static int isBetterFreq(uint32_t now, uint32_t new, uint32_t best)
return (new <= now && new > best); return (new <= now && new > best);
} }
int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num)
{
uint32_t best = 0, mux = 0;
int i;
for (i = 0; i < num; i++) {
if (isBetterFreq(freq, table[i], best)) {
best = table[i];
mux = i;
break;
}
}
return mux;
}
int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1, int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
uint32_t freq2, uint32_t freq3) uint32_t freq2, uint32_t freq3)
{ {
@ -207,17 +191,6 @@ int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1)
return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq1, freq1); return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq1, freq1);
} }
uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num)
{
uint32_t mux = HAL_CRU_ClkGetMux(muxName);
if (mux <= (uint32_t)num) {
return table[mux];
} else {
return HAL_INVAL;
}
}
uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1, uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
uint32_t freq2, uint32_t freq3) uint32_t freq2, uint32_t freq3)
{ {
@ -250,30 +223,6 @@ uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1)
return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq1, freq1); return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq1, freq1);
} }
int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div)
{
uint32_t mux = 0;
int i = 0;
for (i = 0; i < num; i++) {
if (is_div) {
if (table[i] && (table[i] % freq == 0)) {
mux = i;
break;
}
} else {
if (table[i] && (table[i] == freq)) {
mux = i;
break;
}
}
}
*pFreqOut = table[mux];
return mux;
}
int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0,
uint32_t pFreq1, uint32_t pFreq2, uint32_t pFreq1, uint32_t pFreq2,
uint32_t pFreq3, uint32_t *pFreqOut) uint32_t pFreq3, uint32_t *pFreqOut)
@ -862,7 +811,7 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup)
*/ */
uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup)
{ {
uint64_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd;
uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE;
mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift,
@ -1204,18 +1153,16 @@ HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks)
return HAL_OK; return HAL_OK;
} }
HAL_SECTION_SRAM_CODE
HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue)
{ {
uint32_t shift, mask, index, maxDiv; uint32_t shift, mask, index;
index = CLK_DIV_GET_REG_OFFSET(divName); index = CLK_DIV_GET_REG_OFFSET(divName);
shift = CLK_DIV_GET_BITS_SHIFT(divName); shift = CLK_DIV_GET_BITS_SHIFT(divName);
HAL_ASSERT(shift < 16); HAL_ASSERT(shift < 16);
mask = CLK_DIV_GET_MASK(divName); mask = CLK_DIV_GET_MASK(divName);
maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1; if (divValue > mask) {
if (divValue > maxDiv) { divValue = mask;
divValue = maxDiv;
} }
#ifdef CRU_CLK_DIV_CON_CNT #ifdef CRU_CLK_DIV_CON_CNT
@ -1393,31 +1340,6 @@ HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
return HAL_OK; return HAL_OK;
} }
HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate,
uint32_t *numerator,
uint32_t *denominator)
{
uint32_t gcdVal;
gcdVal = CRU_Gcd(rate, rateOut);
if (!gcdVal) {
return HAL_ERROR;
}
*numerator = rateOut / gcdVal;
*denominator = rate / gcdVal;
if (*numerator < 4) {
*numerator *= 4;
*denominator *= 4;
}
if (*numerator > 0xffffff || *denominator > 0xffffff) {
return HAL_INVAL;
}
return HAL_OK;
}
HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv) HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv)
{ {
uint32_t div = CLK_GET_DIV(clockName); uint32_t div = CLK_GET_DIV(clockName);

33
Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru_rk3568.c
View File

@ -874,23 +874,6 @@ uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName)
} }
return freq; return freq;
case CLK_SDMMC0:
if (HAL_CRU_ClkGetMux(clkMux) == 1) {
freq = 400000000;
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
freq = 300000000;
} else if (HAL_CRU_ClkGetMux(clkMux) == 3) {
freq = 100000000;
} else if (HAL_CRU_ClkGetMux(clkMux) == 4) {
freq = 50000000;
} else if (HAL_CRU_ClkGetMux(clkMux) == 5) {
freq = 750000;
} else {
freq = PLL_INPUT_OSC_RATE;
}
return freq;
case ACLK_USB: case ACLK_USB:
case HCLK_USB: case HCLK_USB:
case PCLK_USB: case PCLK_USB:
@ -1019,22 +1002,6 @@ HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate)
mux = 0; mux = 0;
} }
break;
case CLK_SDMMC0:
if (rate == 400000000) {
mux = 1;
} else if (rate == 750000) {
mux = 5;
} else if (rate == 50000000) {
mux = 4;
} else if (rate == 100000000) {
mux = 3;
} else if (rate == 300000000) {
mux = 2;
} else {
mux = 0;
}
break; break;
case ACLK_USB: case ACLK_USB:
case HCLK_USB: case HCLK_USB:

30
Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c
View File

@ -283,7 +283,6 @@
#define GMAC_DESC3_FD (0x1 << 29) #define GMAC_DESC3_FD (0x1 << 29)
#define GMAC_DESC3_LD (0x1 << 28) #define GMAC_DESC3_LD (0x1 << 28)
#define GMAC_DESC3_BUF1V (0x1 << 24) #define GMAC_DESC3_BUF1V (0x1 << 24)
#define GMAC_DESC3_CIC (0x3 << 16)
#define DES3_ERROR_SUMMARY (1 << 15) #define DES3_ERROR_SUMMARY (1 << 15)
@ -1124,7 +1123,7 @@ int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
HAL_ASSERT(pGMAC != NULL); HAL_ASSERT(pGMAC != NULL);
// HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg); HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg);
status = Mdio_WaitIdle(pGMAC); status = Mdio_WaitIdle(pGMAC);
if (status) { if (status) {
HAL_DBG("MDIO not idle at entry"); HAL_DBG("MDIO not idle at entry");
@ -1174,8 +1173,8 @@ HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
HAL_ASSERT(pGMAC != NULL); HAL_ASSERT(pGMAC != NULL);
// HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__, HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__,
// mdioAddr, mdioReg, mdioVal); mdioAddr, mdioReg, mdioVal);
status = Mdio_WaitIdle(pGMAC); status = Mdio_WaitIdle(pGMAC);
if (status) { if (status) {
HAL_DBG("MDIO not idle at entry"); HAL_DBG("MDIO not idle at entry");
@ -1348,6 +1347,7 @@ HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC)
if (pGMAC->phyStatus.neg == PHY_AUTONEG_ENABLE) { if (pGMAC->phyStatus.neg == PHY_AUTONEG_ENABLE) {
uint32_t lpa = 0, estatus = 0; uint32_t lpa = 0, estatus = 0;
int32_t gblpa = 0; int32_t gblpa = 0;
/* Check for gigabit capability */ /* Check for gigabit capability */
if (pGMAC->phyStatus.supported & (HAL_GMAC_PHY_SUPPORTED_1000baseT_Full | if (pGMAC->phyStatus.supported & (HAL_GMAC_PHY_SUPPORTED_1000baseT_Full |
HAL_GMAC_PHY_SUPPORTED_1000baseT_Half)) { HAL_GMAC_PHY_SUPPORTED_1000baseT_Half)) {
@ -1746,13 +1746,6 @@ HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay,
* *
* @return HAL status * @return HAL status
*/ */
#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
#define DMA_AXI_WR_OSR_LMT_SHIFT 24
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
#define DMA_AXI_RD_OSR_LMT_SHIFT 16
#define DMA_AXI_OSR_MAX 0xf
HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
{ {
uint32_t mmc_mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | uint32_t mmc_mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
@ -1771,7 +1764,6 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
value = READ_REG(pGMAC->pReg->DMA_MODE); value = READ_REG(pGMAC->pReg->DMA_MODE);
WRITE_REG(pGMAC->pReg->DMA_MODE, value | DMA_MODE_SWR); WRITE_REG(pGMAC->pReg->DMA_MODE, value | DMA_MODE_SWR);
/* Wait for software Reset */ /* Wait for software Reset */
HAL_DelayMs(100);
while (limit--) { while (limit--) {
if (!(READ_REG(pGMAC->pReg->DMA_MODE) & DMA_MODE_SWR)) { if (!(READ_REG(pGMAC->pReg->DMA_MODE) & DMA_MODE_SWR)) {
break; break;
@ -1785,12 +1777,6 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
} }
HAL_DelayMs(100); HAL_DelayMs(100);
value = READ_REG(pGMAC->pReg->DMA_SYSBUS_MODE);
value &= ~DMA_AXI_WR_OSR_LMT;
value |= (0x0 & DMA_AXI_OSR_MAX) << DMA_AXI_WR_OSR_LMT_SHIFT;
value &= ~DMA_AXI_RD_OSR_LMT;
value |= (0x2 & DMA_AXI_OSR_MAX) << DMA_AXI_RD_OSR_LMT_SHIFT;
/* DMA init */ /* DMA init */
WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, DMA_SYSBUS_MODE_BLEN16 | WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, DMA_SYSBUS_MODE_BLEN16 |
@ -1803,7 +1789,6 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
/* Set the HW DMA mode and the COE */ /* Set the HW DMA mode and the COE */
txFifosz = 128 << ((hwCap & GMAC_HW_TXFIFOSIZE) >> GMAC_HW_TXFIFOSIZE_SHIFT); txFifosz = 128 << ((hwCap & GMAC_HW_TXFIFOSIZE) >> GMAC_HW_TXFIFOSIZE_SHIFT);
rxFifosz = 128 << ((hwCap & GMAC_HW_RXFIFOSIZE) >> GMAC_HW_RXFIFOSIZE_SHIFT); rxFifosz = 128 << ((hwCap & GMAC_HW_RXFIFOSIZE) >> GMAC_HW_RXFIFOSIZE_SHIFT);
/* init rx chan */ /* init rx chan */
value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL); value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL);
@ -1817,7 +1802,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
/* init tx chan */ /* init tx chan */
value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL); value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL);
value = value | (32 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT); value = value | (8 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
value |= DMA_CH0_TX_CONTROL_OSF; value |= DMA_CH0_TX_CONTROL_OSF;
WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value); WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value);
@ -2017,7 +2002,7 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet,
desc->des0 = (uint32_t)(uint64_t)packet; desc->des0 = (uint32_t)(uint64_t)packet;
desc->des1 = 0; desc->des1 = 0;
desc->des2 = length | 1<<31; desc->des2 = length;
/* /*
* Make sure that if HW sees the _OWN write below, it will see all the * Make sure that if HW sees the _OWN write below, it will see all the
* writes to the rest of the descriptor too. * writes to the rest of the descriptor too.
@ -2064,7 +2049,7 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length)
HAL_DBG("Rx at %p\n", desc->des0); HAL_DBG("Rx at %p\n", desc->des0);
des3 = desc->des3; des3 = desc->des3;
if (des3 & GMAC_DESC3_OWN) { if (des3 & GMAC_DESC3_OWN) {
HAL_DBG("%p: RX packet not available\n", desc->des0); HAL_DBG("%s: RX packet not available\n", __func__);
return NULL; return NULL;
} }
@ -2187,6 +2172,7 @@ HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg,
pGMAC->txDescIdx = 0; pGMAC->txDescIdx = 0;
pGMAC->rxDescIdx = 0; pGMAC->rxDescIdx = 0;
/* Get CR bits depending on hclk value */ /* Get CR bits depending on hclk value */
if ((freq >= 20000000) && (freq < 35000000)) { if ((freq >= 20000000) && (freq < 35000000)) {
/* CSR Clock Range between 20-35 MHz */ /* CSR Clock Range between 20-35 MHz */

71
Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gpio.c
View File

@ -58,7 +58,7 @@
*/ */
static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) { if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000; pin &= 0xFFFF0000;
pGPIO->PORT_EOI_H = pin | (pin >> 16); pGPIO->PORT_EOI_H = pin | (pin >> 16);
@ -82,7 +82,7 @@ static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO)
{ {
uint32_t type; uint32_t type;
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
type = (pGPIO->INT_TYPE_L & 0xffff); type = (pGPIO->INT_TYPE_L & 0xffff);
type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16); type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16);
type |= (pGPIO->INT_BOTHEDGE_L & 0xffff); type |= (pGPIO->INT_BOTHEDGE_L & 0xffff);
@ -161,7 +161,7 @@ HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, e
return HAL_INVAL; return HAL_INVAL;
} }
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) { if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000; pin &= 0xFFFF0000;
pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin); pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin);
@ -195,7 +195,7 @@ HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, e
*/ */
HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction) HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) { if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000; pin &= 0xFFFF0000;
pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin); pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin);
@ -251,7 +251,7 @@ eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPI
eGPIO_pinDirection direction; eGPIO_pinDirection direction;
uint32_t value; uint32_t value;
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin); value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin);
#else #else
value = pGPIO->SWPORTA_DDR & pin; value = pGPIO->SWPORTA_DDR & pin;
@ -275,7 +275,7 @@ eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPI
*/ */
HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level) HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) { if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000; pin &= 0xFFFF0000;
pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin); pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin);
@ -340,7 +340,7 @@ eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pi
eGPIO_pinLevel level; eGPIO_pinLevel level;
uint32_t value; uint32_t value;
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin); value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin);
#else #else
value = pGPIO->SWPORTA_DR & pin; value = pGPIO->SWPORTA_DR & pin;
@ -365,7 +365,7 @@ eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS p
{ {
uint32_t value; uint32_t value;
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
value = (pGPIO->EXT_PORT & pin); value = (pGPIO->EXT_PORT & pin);
#else #else
value = (pGPIO->EXT_PORTA & pin); value = (pGPIO->EXT_PORTA & pin);
@ -383,7 +383,7 @@ uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
{ {
uint32_t value; uint32_t value;
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
value = (pGPIO->EXT_PORT); value = (pGPIO->EXT_PORT);
#else #else
value = (pGPIO->EXT_PORTA); value = (pGPIO->EXT_PORTA);
@ -404,7 +404,7 @@ uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
*/ */
void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) { if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000; pin &= 0xFFFF0000;
#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED #ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
@ -433,7 +433,7 @@ void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
*/ */
void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
if (IS_GPIO_HIGH_PIN(pin)) { if (IS_GPIO_HIGH_PIN(pin)) {
pin &= 0xFFFF0000; pin &= 0xFFFF0000;
pGPIO->INT_EN_H = pin; pGPIO->INT_EN_H = pin;
@ -511,7 +511,7 @@ void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank)
*/ */
HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO) HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
pGPIO->GPIO_VIRTUAL_EN = 0x10001; pGPIO->GPIO_VIRTUAL_EN = 0x10001;
return HAL_OK; return HAL_OK;
@ -527,7 +527,7 @@ HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
*/ */
HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO) HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
pGPIO->GPIO_VIRTUAL_EN = 0x10000; pGPIO->GPIO_VIRTUAL_EN = 0x10000;
return HAL_OK; return HAL_OK;
@ -545,51 +545,22 @@ HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
*/ */
HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel) HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel)
{ {
#if (GPIO_VER_ID >= 0x01000C2BU) #if (GPIO_VER_ID == 0x01000C2BU)
uint32_t lowPins, highPins; uint32_t low_pins, high_pins;
lowPins = pin & 0x0000ffff; low_pins = pin & 0x0000ffff;
highPins = (pin & 0xffff0000) >> 16; high_pins = (pin & 0xffff0000) >> 16;
#if defined(GPIO0_EXP)
/* Support OS_A and OS_B */ /* Support OS_A and OS_B */
if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) { if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) {
pGPIO->GPIO_REG_GROUP_L = lowPins << 16; pGPIO->GPIO_REG_GROUP_L = low_pins << 16;
pGPIO->GPIO_REG_GROUP_H = highPins << 16; pGPIO->GPIO_REG_GROUP_H = high_pins << 16;
} else { } else {
pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16); pGPIO->GPIO_REG_GROUP_L = low_pins | (low_pins << 16);
pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16); pGPIO->GPIO_REG_GROUP_H = high_pins | (high_pins << 16);
} }
return HAL_OK; return HAL_OK;
#elif defined(GPIO0_EXP3)
/* Support 4 OS */
switch (vmodel) {
case GPIO_VIRTUAL_MODEL_OS_A:
pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
break;
case GPIO_VIRTUAL_MODEL_OS_B:
pGPIO->GPIO_REG_GROUP1_L = lowPins | (lowPins << 16);
pGPIO->GPIO_REG_GROUP1_H = highPins | (highPins << 16);
break;
case GPIO_VIRTUAL_MODEL_OS_C:
pGPIO->GPIO_REG_GROUP2_L = lowPins | (lowPins << 16);
pGPIO->GPIO_REG_GROUP2_H = highPins | (highPins << 16);
break;
case GPIO_VIRTUAL_MODEL_OS_D:
pGPIO->GPIO_REG_GROUP3_L = lowPins | (lowPins << 16);
pGPIO->GPIO_REG_GROUP3_H = highPins | (highPins << 16);
break;
default:
HAL_DBG("unknown gpio virtual model-%d\n", vmodel);
break;
}
return HAL_OK;
#else
#error missing GPIO EXP register definition!
#endif
#endif #endif
return HAL_ERROR; return HAL_ERROR;

23
Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_cru.h
View File

@ -159,11 +159,6 @@ typedef enum {
GLB_RST_SND_WDT1, GLB_RST_SND_WDT1,
GLB_RST_FST_WDT2, GLB_RST_FST_WDT2,
GLB_RST_SND_WDT2, GLB_RST_SND_WDT2,
GLB_RST_FST_WDT3,
GLB_RST_SND_WDT3,
GLB_RST_FST_WDT4,
GLB_RST_SND_WDT4,
} eCRU_WdtRstType; } eCRU_WdtRstType;
struct CRU_BANK_INFO { struct CRU_BANK_INFO {
@ -197,14 +192,12 @@ int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1, int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1,
uint32_t freq2); uint32_t freq2);
int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1); int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1);
int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num);
uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1, uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
uint32_t freq2, uint32_t freq3); uint32_t freq2, uint32_t freq3);
uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1, uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1,
uint32_t freq2); uint32_t freq2);
uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1); uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1);
uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num);
int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut); uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut);
@ -212,7 +205,6 @@ int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
uint32_t pFreq2, uint32_t *pFreqOut); uint32_t pFreq2, uint32_t *pFreqOut);
int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
uint32_t *pFreqOut); uint32_t *pFreqOut);
int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div);
/** @} */ /** @} */
@ -379,21 +371,6 @@ uint32_t HAL_CRU_ClkGetMux(uint32_t muxName);
HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
uint32_t *numerator, uint32_t *numerator,
uint32_t *denominator); uint32_t *denominator);
/**
* @brief Get frac div config V2(24bit).
* @param rateOut: clk out rate.
* @param rate: clk src rate.
* @param numerator: the returned numerator.
* @param denominator: the returned denominator.
* @return HAL_Status.
*/
HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate,
uint32_t *numerator,
uint32_t *denominator);
/** /**
* @brief Get clk freq. * @brief Get clk freq.
* @param clockName: CLOCK_Name id. * @param clockName: CLOCK_Name id.

14
Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h
View File

@ -207,10 +207,10 @@ struct GMAC_Link {
* @brief GMAC DMA Descriptors Data Structure Definition * @brief GMAC DMA Descriptors Data Structure Definition
*/ */
struct GMAC_Desc { struct GMAC_Desc {
volatile uint32_t des0; /**< DMA Descriptors first word */ uint32_t des0; /**< DMA Descriptors first word */
volatile uint32_t des1; /**< DMA Descriptors second word */ uint32_t des1; /**< DMA Descriptors second word */
volatile uint32_t des2; /**< DMA Descriptors third word */ uint32_t des2; /**< DMA Descriptors third word */
volatile uint32_t des3; /**< DMA Descriptors four word */ uint32_t des3; /**< DMA Descriptors four word */
}; };
/** /**
@ -287,10 +287,8 @@ struct GMAC_HANDLE {
*/ */
struct HAL_GMAC_DEV { struct HAL_GMAC_DEV {
struct GMAC_REG *pReg; struct GMAC_REG *pReg;
eCLOCK_Name clkID125M; eCLOCK_Name clkID;
eCLOCK_Name clkID50M; uint32_t clkGateID;
uint32_t clkGateID125M;
uint32_t clkGateID50M;
eCLOCK_Name pclkID; eCLOCK_Name pclkID;
uint32_t pclkGateID; uint32_t pclkGateID;
IRQn_Type irqNum; IRQn_Type irqNum;

525
Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_pinctrl.h
View File

@ -370,516 +370,6 @@ typedef enum {
GPIO4_EXP_D5, GPIO4_EXP_D5,
GPIO4_EXP_D6, GPIO4_EXP_D6,
GPIO4_EXP_D7, GPIO4_EXP_D7,
#endif
#if defined(GPIO0_EXP1)
GPIO0_EXP1_A0 = 160,
GPIO0_EXP1_A1,
GPIO0_EXP1_A2,
GPIO0_EXP1_A3,
GPIO0_EXP1_A4,
GPIO0_EXP1_A5,
GPIO0_EXP1_A6,
GPIO0_EXP1_A7,
GPIO0_EXP1_B0 = 168,
GPIO0_EXP1_B1,
GPIO0_EXP1_B2,
GPIO0_EXP1_B3,
GPIO0_EXP1_B4,
GPIO0_EXP1_B5,
GPIO0_EXP1_B6,
GPIO0_EXP1_B7,
GPIO0_EXP1_C0 = 176,
GPIO0_EXP1_C1,
GPIO0_EXP1_C2,
GPIO0_EXP1_C3,
GPIO0_EXP1_C4,
GPIO0_EXP1_C5,
GPIO0_EXP1_C6,
GPIO0_EXP1_C7,
GPIO0_EXP1_D0 = 184,
GPIO0_EXP1_D1,
GPIO0_EXP1_D2,
GPIO0_EXP1_D3,
GPIO0_EXP1_D4,
GPIO0_EXP1_D5,
GPIO0_EXP1_D6,
GPIO0_EXP1_D7,
#endif
#if defined(GPIO1_EXP1)
GPIO1_EXP1_A0 = 192,
GPIO1_EXP1_A1,
GPIO1_EXP1_A2,
GPIO1_EXP1_A3,
GPIO1_EXP1_A4,
GPIO1_EXP1_A5,
GPIO1_EXP1_A6,
GPIO1_EXP1_A7,
GPIO1_EXP1_B0 = 200,
GPIO1_EXP1_B1,
GPIO1_EXP1_B2,
GPIO1_EXP1_B3,
GPIO1_EXP1_B4,
GPIO1_EXP1_B5,
GPIO1_EXP1_B6,
GPIO1_EXP1_B7,
GPIO1_EXP1_C0 = 208,
GPIO1_EXP1_C1,
GPIO1_EXP1_C2,
GPIO1_EXP1_C3,
GPIO1_EXP1_C4,
GPIO1_EXP1_C5,
GPIO1_EXP1_C6,
GPIO1_EXP1_C7,
GPIO1_EXP1_D0 = 216,
GPIO1_EXP1_D1,
GPIO1_EXP1_D2,
GPIO1_EXP1_D3,
GPIO1_EXP1_D4,
GPIO1_EXP1_D5,
GPIO1_EXP1_D6,
GPIO1_EXP1_D7,
#endif
#if defined(GPIO2_EXP1)
GPIO2_EXP1_A0 = 224,
GPIO2_EXP1_A1,
GPIO2_EXP1_A2,
GPIO2_EXP1_A3,
GPIO2_EXP1_A4,
GPIO2_EXP1_A5,
GPIO2_EXP1_A6,
GPIO2_EXP1_A7,
GPIO2_EXP1_B0 = 232,
GPIO2_EXP1_B1,
GPIO2_EXP1_B2,
GPIO2_EXP1_B3,
GPIO2_EXP1_B4,
GPIO2_EXP1_B5,
GPIO2_EXP1_B6,
GPIO2_EXP1_B7,
GPIO2_EXP1_C0 = 240,
GPIO2_EXP1_C1,
GPIO2_EXP1_C2,
GPIO2_EXP1_C3,
GPIO2_EXP1_C4,
GPIO2_EXP1_C5,
GPIO2_EXP1_C6,
GPIO2_EXP1_C7,
GPIO2_EXP1_D0 = 248,
GPIO2_EXP1_D1,
GPIO2_EXP1_D2,
GPIO2_EXP1_D3,
GPIO2_EXP1_D4,
GPIO2_EXP1_D5,
GPIO2_EXP1_D6,
GPIO2_EXP1_D7,
#endif
#if defined(GPIO3_EXP1)
GPIO3_EXP1_A0 = 256,
GPIO3_EXP1_A1,
GPIO3_EXP1_A2,
GPIO3_EXP1_A3,
GPIO3_EXP1_A4,
GPIO3_EXP1_A5,
GPIO3_EXP1_A6,
GPIO3_EXP1_A7,
GPIO3_EXP1_B0 = 264,
GPIO3_EXP1_B1,
GPIO3_EXP1_B2,
GPIO3_EXP1_B3,
GPIO3_EXP1_B4,
GPIO3_EXP1_B5,
GPIO3_EXP1_B6,
GPIO3_EXP1_B7,
GPIO3_EXP1_C0 = 272,
GPIO3_EXP1_C1,
GPIO3_EXP1_C2,
GPIO3_EXP1_C3,
GPIO3_EXP1_C4,
GPIO3_EXP1_C5,
GPIO3_EXP1_C6,
GPIO3_EXP1_C7,
GPIO3_EXP1_D0 = 280,
GPIO3_EXP1_D1,
GPIO3_EXP1_D2,
GPIO3_EXP1_D3,
GPIO3_EXP1_D4,
GPIO3_EXP1_D5,
GPIO3_EXP1_D6,
GPIO3_EXP1_D7,
#endif
#if defined(GPIO4_EXP1)
GPIO4_EXP1_A0 = 288,
GPIO4_EXP1_A1,
GPIO4_EXP1_A2,
GPIO4_EXP1_A3,
GPIO4_EXP1_A4,
GPIO4_EXP1_A5,
GPIO4_EXP1_A6,
GPIO4_EXP1_A7,
GPIO4_EXP1_B0 = 296,
GPIO4_EXP1_B1,
GPIO4_EXP1_B2,
GPIO4_EXP1_B3,
GPIO4_EXP1_B4,
GPIO4_EXP1_B5,
GPIO4_EXP1_B6,
GPIO4_EXP1_B7,
GPIO4_EXP1_C0 = 304,
GPIO4_EXP1_C1,
GPIO4_EXP1_C2,
GPIO4_EXP1_C3,
GPIO4_EXP1_C4,
GPIO4_EXP1_C5,
GPIO4_EXP1_C6,
GPIO4_EXP1_C7,
GPIO4_EXP1_D0 = 312,
GPIO4_EXP1_D1,
GPIO4_EXP1_D2,
GPIO4_EXP1_D3,
GPIO4_EXP1_D4,
GPIO4_EXP1_D5,
GPIO4_EXP1_D6,
GPIO4_EXP1_D7,
#endif
#if defined(GPIO0_EXP2)
GPIO0_EXP2_A0 = 320,
GPIO0_EXP2_A1,
GPIO0_EXP2_A2,
GPIO0_EXP2_A3,
GPIO0_EXP2_A4,
GPIO0_EXP2_A5,
GPIO0_EXP2_A6,
GPIO0_EXP2_A7,
GPIO0_EXP2_B0 = 328,
GPIO0_EXP2_B1,
GPIO0_EXP2_B2,
GPIO0_EXP2_B3,
GPIO0_EXP2_B4,
GPIO0_EXP2_B5,
GPIO0_EXP2_B6,
GPIO0_EXP2_B7,
GPIO0_EXP2_C0 = 336,
GPIO0_EXP2_C1,
GPIO0_EXP2_C2,
GPIO0_EXP2_C3,
GPIO0_EXP2_C4,
GPIO0_EXP2_C5,
GPIO0_EXP2_C6,
GPIO0_EXP2_C7,
GPIO0_EXP2_D0 = 344,
GPIO0_EXP2_D1,
GPIO0_EXP2_D2,
GPIO0_EXP2_D3,
GPIO0_EXP2_D4,
GPIO0_EXP2_D5,
GPIO0_EXP2_D6,
GPIO0_EXP2_D7,
#endif
#if defined(GPIO1_EXP2)
GPIO1_EXP2_A0 = 352,
GPIO1_EXP2_A1,
GPIO1_EXP2_A2,
GPIO1_EXP2_A3,
GPIO1_EXP2_A4,
GPIO1_EXP2_A5,
GPIO1_EXP2_A6,
GPIO1_EXP2_A7,
GPIO1_EXP2_B0 = 360,
GPIO1_EXP2_B1,
GPIO1_EXP2_B2,
GPIO1_EXP2_B3,
GPIO1_EXP2_B4,
GPIO1_EXP2_B5,
GPIO1_EXP2_B6,
GPIO1_EXP2_B7,
GPIO1_EXP2_C0 = 368,
GPIO1_EXP2_C1,
GPIO1_EXP2_C2,
GPIO1_EXP2_C3,
GPIO1_EXP2_C4,
GPIO1_EXP2_C5,
GPIO1_EXP2_C6,
GPIO1_EXP2_C7,
GPIO1_EXP2_D0 = 376,
GPIO1_EXP2_D1,
GPIO1_EXP2_D2,
GPIO1_EXP2_D3,
GPIO1_EXP2_D4,
GPIO1_EXP2_D5,
GPIO1_EXP2_D6,
GPIO1_EXP2_D7,
#endif
#if defined(GPIO2_EXP2)
GPIO2_EXP2_A0 = 384,
GPIO2_EXP2_A1,
GPIO2_EXP2_A2,
GPIO2_EXP2_A3,
GPIO2_EXP2_A4,
GPIO2_EXP2_A5,
GPIO2_EXP2_A6,
GPIO2_EXP2_A7,
GPIO2_EXP2_B0 = 392,
GPIO2_EXP2_B1,
GPIO2_EXP2_B2,
GPIO2_EXP2_B3,
GPIO2_EXP2_B4,
GPIO2_EXP2_B5,
GPIO2_EXP2_B6,
GPIO2_EXP2_B7,
GPIO2_EXP2_C0 = 400,
GPIO2_EXP2_C1,
GPIO2_EXP2_C2,
GPIO2_EXP2_C3,
GPIO2_EXP2_C4,
GPIO2_EXP2_C5,
GPIO2_EXP2_C6,
GPIO2_EXP2_C7,
GPIO2_EXP2_D0 = 408,
GPIO2_EXP2_D1,
GPIO2_EXP2_D2,
GPIO2_EXP2_D3,
GPIO2_EXP2_D4,
GPIO2_EXP2_D5,
GPIO2_EXP2_D6,
GPIO2_EXP2_D7,
#endif
#if defined(GPIO3_EXP2)
GPIO3_EXP2_A0 = 416,
GPIO3_EXP2_A1,
GPIO3_EXP2_A2,
GPIO3_EXP2_A3,
GPIO3_EXP2_A4,
GPIO3_EXP2_A5,
GPIO3_EXP2_A6,
GPIO3_EXP2_A7,
GPIO3_EXP2_B0 = 424,
GPIO3_EXP2_B1,
GPIO3_EXP2_B2,
GPIO3_EXP2_B3,
GPIO3_EXP2_B4,
GPIO3_EXP2_B5,
GPIO3_EXP2_B6,
GPIO3_EXP2_B7,
GPIO3_EXP2_C0 = 432,
GPIO3_EXP2_C1,
GPIO3_EXP2_C2,
GPIO3_EXP2_C3,
GPIO3_EXP2_C4,
GPIO3_EXP2_C5,
GPIO3_EXP2_C6,
GPIO3_EXP2_C7,
GPIO3_EXP2_D0 = 440,
GPIO3_EXP2_D1,
GPIO3_EXP2_D2,
GPIO3_EXP2_D3,
GPIO3_EXP2_D4,
GPIO3_EXP2_D5,
GPIO3_EXP2_D6,
GPIO3_EXP2_D7,
#endif
#if defined(GPIO4_EXP2)
GPIO4_EXP2_A0 = 448,
GPIO4_EXP2_A1,
GPIO4_EXP2_A2,
GPIO4_EXP2_A3,
GPIO4_EXP2_A4,
GPIO4_EXP2_A5,
GPIO4_EXP2_A6,
GPIO4_EXP2_A7,
GPIO4_EXP2_B0 = 456,
GPIO4_EXP2_B1,
GPIO4_EXP2_B2,
GPIO4_EXP2_B3,
GPIO4_EXP2_B4,
GPIO4_EXP2_B5,
GPIO4_EXP2_B6,
GPIO4_EXP2_B7,
GPIO4_EXP2_C0 = 464,
GPIO4_EXP2_C1,
GPIO4_EXP2_C2,
GPIO4_EXP2_C3,
GPIO4_EXP2_C4,
GPIO4_EXP2_C5,
GPIO4_EXP2_C6,
GPIO4_EXP2_C7,
GPIO4_EXP2_D0 = 472,
GPIO4_EXP2_D1,
GPIO4_EXP2_D2,
GPIO4_EXP2_D3,
GPIO4_EXP2_D4,
GPIO4_EXP2_D5,
GPIO4_EXP2_D6,
GPIO4_EXP2_D7,
#endif
#if defined(GPIO0_EXP3)
GPIO0_EXP3_A0 = 480,
GPIO0_EXP3_A1,
GPIO0_EXP3_A2,
GPIO0_EXP3_A3,
GPIO0_EXP3_A4,
GPIO0_EXP3_A5,
GPIO0_EXP3_A6,
GPIO0_EXP3_A7,
GPIO0_EXP3_B0 = 488,
GPIO0_EXP3_B1,
GPIO0_EXP3_B2,
GPIO0_EXP3_B3,
GPIO0_EXP3_B4,
GPIO0_EXP3_B5,
GPIO0_EXP3_B6,
GPIO0_EXP3_B7,
GPIO0_EXP3_C0 = 496,
GPIO0_EXP3_C1,
GPIO0_EXP3_C2,
GPIO0_EXP3_C3,
GPIO0_EXP3_C4,
GPIO0_EXP3_C5,
GPIO0_EXP3_C6,
GPIO0_EXP3_C7,
GPIO0_EXP3_D0 = 504,
GPIO0_EXP3_D1,
GPIO0_EXP3_D2,
GPIO0_EXP3_D3,
GPIO0_EXP3_D4,
GPIO0_EXP3_D5,
GPIO0_EXP3_D6,
GPIO0_EXP3_D7,
#endif
#if defined(GPIO1_EXP3)
GPIO1_EXP3_A0 = 512,
GPIO1_EXP3_A1,
GPIO1_EXP3_A2,
GPIO1_EXP3_A3,
GPIO1_EXP3_A4,
GPIO1_EXP3_A5,
GPIO1_EXP3_A6,
GPIO1_EXP3_A7,
GPIO1_EXP3_B0 = 520,
GPIO1_EXP3_B1,
GPIO1_EXP3_B2,
GPIO1_EXP3_B3,
GPIO1_EXP3_B4,
GPIO1_EXP3_B5,
GPIO1_EXP3_B6,
GPIO1_EXP3_B7,
GPIO1_EXP3_C0 = 528,
GPIO1_EXP3_C1,
GPIO1_EXP3_C2,
GPIO1_EXP3_C3,
GPIO1_EXP3_C4,
GPIO1_EXP3_C5,
GPIO1_EXP3_C6,
GPIO1_EXP3_C7,
GPIO1_EXP3_D0 = 536,
GPIO1_EXP3_D1,
GPIO1_EXP3_D2,
GPIO1_EXP3_D3,
GPIO1_EXP3_D4,
GPIO1_EXP3_D5,
GPIO1_EXP3_D6,
GPIO1_EXP3_D7,
#endif
#if defined(GPIO2_EXP3)
GPIO2_EXP3_A0 = 544,
GPIO2_EXP3_A1,
GPIO2_EXP3_A2,
GPIO2_EXP3_A3,
GPIO2_EXP3_A4,
GPIO2_EXP3_A5,
GPIO2_EXP3_A6,
GPIO2_EXP3_A7,
GPIO2_EXP3_B0 = 552,
GPIO2_EXP3_B1,
GPIO2_EXP3_B2,
GPIO2_EXP3_B3,
GPIO2_EXP3_B4,
GPIO2_EXP3_B5,
GPIO2_EXP3_B6,
GPIO2_EXP3_B7,
GPIO2_EXP3_C0 = 560,
GPIO2_EXP3_C1,
GPIO2_EXP3_C2,
GPIO2_EXP3_C3,
GPIO2_EXP3_C4,
GPIO2_EXP3_C5,
GPIO2_EXP3_C6,
GPIO2_EXP3_C7,
GPIO2_EXP3_D0 = 568,
GPIO2_EXP3_D1,
GPIO2_EXP3_D2,
GPIO2_EXP3_D3,
GPIO2_EXP3_D4,
GPIO2_EXP3_D5,
GPIO2_EXP3_D6,
GPIO2_EXP3_D7,
#endif
#if defined(GPIO3_EXP3)
GPIO3_EXP3_A0 = 576,
GPIO3_EXP3_A1,
GPIO3_EXP3_A2,
GPIO3_EXP3_A3,
GPIO3_EXP3_A4,
GPIO3_EXP3_A5,
GPIO3_EXP3_A6,
GPIO3_EXP3_A7,
GPIO3_EXP3_B0 = 584,
GPIO3_EXP3_B1,
GPIO3_EXP3_B2,
GPIO3_EXP3_B3,
GPIO3_EXP3_B4,
GPIO3_EXP3_B5,
GPIO3_EXP3_B6,
GPIO3_EXP3_B7,
GPIO3_EXP3_C0 = 592,
GPIO3_EXP3_C1,
GPIO3_EXP3_C2,
GPIO3_EXP3_C3,
GPIO3_EXP3_C4,
GPIO3_EXP3_C5,
GPIO3_EXP3_C6,
GPIO3_EXP3_C7,
GPIO3_EXP3_D0 = 600,
GPIO3_EXP3_D1,
GPIO3_EXP3_D2,
GPIO3_EXP3_D3,
GPIO3_EXP3_D4,
GPIO3_EXP3_D5,
GPIO3_EXP3_D6,
GPIO3_EXP3_D7,
#endif
#if defined(GPIO4_EXP3)
GPIO4_EXP3_A0 = 608,
GPIO4_EXP3_A1,
GPIO4_EXP3_A2,
GPIO4_EXP3_A3,
GPIO4_EXP3_A4,
GPIO4_EXP3_A5,
GPIO4_EXP3_A6,
GPIO4_EXP3_A7,
GPIO4_EXP3_B0 = 616,
GPIO4_EXP3_B1,
GPIO4_EXP3_B2,
GPIO4_EXP3_B3,
GPIO4_EXP3_B4,
GPIO4_EXP3_B5,
GPIO4_EXP3_B6,
GPIO4_EXP3_B7,
GPIO4_EXP3_C0 = 624,
GPIO4_EXP3_C1,
GPIO4_EXP3_C2,
GPIO4_EXP3_C3,
GPIO4_EXP3_C4,
GPIO4_EXP3_C5,
GPIO4_EXP3_C6,
GPIO4_EXP3_C7,
GPIO4_EXP3_D0 = 632,
GPIO4_EXP3_D1,
GPIO4_EXP3_D2,
GPIO4_EXP3_D3,
GPIO4_EXP3_D4,
GPIO4_EXP3_D5,
GPIO4_EXP3_D6,
GPIO4_EXP3_D7,
#endif #endif
GPIO_NUM_MAX GPIO_NUM_MAX
} ePINCTRL_PIN; } ePINCTRL_PIN;
@ -986,7 +476,7 @@ typedef enum {
PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT, PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT,
PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT, PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT,
PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT, PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT,
#elif defined(SOC_RK3588) || defined(SOC_RK3576) #elif defined(SOC_RK3588)
PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL),
PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL), PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL),
PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL), PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL),
@ -1000,7 +490,7 @@ typedef enum {
PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL,
#endif #endif
#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562) || defined(RKMCU_RK2118) #if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562)
PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV),
@ -1014,14 +504,6 @@ typedef enum {
PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
#elif defined(SOC_RK3576)
PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL1 = (0x4 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL3 = (0x6 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL4 = (0x1 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
#else #else
PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV),
PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV),
@ -1196,9 +678,6 @@ HAL_Status HAL_PINCTRL_DeInit(void);
HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
#ifdef RM0_IO
HAL_Status HAL_PINCTRL_SetRMIO(eGPIO_bankId bank, uint32_t rmioPin, eRMIO_Name rmioFunc);
#endif
HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode); HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode);
HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode); HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode);

13
Ubiquitous/XiZi_AIoT/services/drivers/3568/include/soc.h
View File

@ -415,7 +415,6 @@ typedef enum CLOCK_Name {
ACLK_USB = CLK(ACLK_USB_SEL, 0U), ACLK_USB = CLK(ACLK_USB_SEL, 0U),
HCLK_USB = CLK(HCLK_USB_SEL, 0U), HCLK_USB = CLK(HCLK_USB_SEL, 0U),
PCLK_USB = CLK(0U, PCLK_USB_DIV), PCLK_USB = CLK(0U, PCLK_USB_DIV),
CLK_SDMMC0 = CLK(CLK_SDMMC0_SEL, 0U),
} eCLOCK_Name; } eCLOCK_Name;
#endif #endif
/****************************************MBOX********************************************/ /****************************************MBOX********************************************/
@ -426,10 +425,10 @@ typedef enum CLOCK_Name {
#define GRF_DS_BIT_PER_PIN (8) #define GRF_DS_BIT_PER_PIN (8)
#define GRF_PULL_BIT_PER_PIN (2) #define GRF_PULL_BIT_PER_PIN (2)
/****************************************GPIO********************************************/ /****************************************GPIO********************************************/
// #ifdef GPIO_VER_ID #ifdef GPIO_VER_ID
// #undef GPIO_VER_ID #undef GPIO_VER_ID
// #define GPIO_VER_ID (0x01000C2BU) #define GPIO_VER_ID (0x01000C2BU)
// #endif #endif
/****************************************PMU*********************************************/ /****************************************PMU*********************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
typedef enum PD_Id { typedef enum PD_Id {
@ -439,10 +438,6 @@ typedef enum PD_Id {
/****************************************FSPI********************************************/ /****************************************FSPI********************************************/
#define FSPI_CHIP_CNT (2) #define FSPI_CHIP_CNT (2)
/****************************************WDT*********************************************/
#define GLB_RST_SND_WDT GLB_RST_SND_WDT0
#define GLB_RST_FST_WDT GLB_RST_FST_WDT0
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */