forked from xuos/xiuos
kernel normal boot at 3568
This commit is contained in:
lr
parent
d29c618113
commit
c2e21257d0
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@ -1,3 +1,3 @@
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SRC_FILES := l1_cache.c
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SRC_FILES := l1_cache.c cache.S
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,336 @@
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* This file is based on sample code from ARMv8 ARM.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define ASM_NL ;
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#define SYMBOL_NAME(X) X
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// #define SYMBOL_NAME_LABEL(X) X##:
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#define SYMBOL_NAME_LABEL(X) X:
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#ifndef __ALIGN
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#define __ALIGN .align 4
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#endif
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#ifndef __ALIGN_STR
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#define __ALIGN_STR ".align 4"
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#endif
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#define ALIGN __ALIGN
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#define ALIGN_STR __ALIGN_STR
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#define LENTRY(name) \
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ALIGN ASM_NL \
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SYMBOL_NAME_LABEL(name)
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#define ENTRY(name) \
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.globl SYMBOL_NAME(name) ASM_NL \
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LENTRY(name)
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#define WEAK(name) \
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.weak SYMBOL_NAME(name) ASM_NL \
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LENTRY(name)
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#define END(name) \
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.size name, .-name
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#define ENDPROC(name) \
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.type name STT_FUNC ASM_NL \
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END(name)
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_WXN (1 << 19) /* Write Permision Imply XN */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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.macro switch_el, xreg, el3_label, el2_label, el1_label
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mrs \xreg, CurrentEL
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cmp \xreg, 0xc
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b.eq \el3_label
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cmp \xreg, 0x8
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b.eq \el2_label
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cmp \xreg, 0x4
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b.eq \el1_label
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.endm
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/*
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* void __asm_dcache_level(level)
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* flush or invalidate one level cache.
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*
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* x0: cache level
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* x1: 0 clean & invalidate, 1 invalidate only
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* x2~x9: clobbered
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*/
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ENTRY(__asm_dcache_level)
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lsl x12, x0, #1
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msr csselr_el1, x12 /* select cache level */
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isb /* sync change of cssidr_el1 */
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mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
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and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
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add x2, x2, #4 /* x2 <- log2(cache line size) */
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mov x3, #0x3ff
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and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
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clz w5, w3 /* bit position of #ways */
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mov x4, #0x7fff
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and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
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/* x12 <- cache level << 1 */
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/* x2 <- line length offset */
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/* x3 <- number of cache ways - 1 */
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/* x4 <- number of cache sets - 1 */
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/* x5 <- bit position of #ways */
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loop_set:
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mov x6, x3 /* x6 <- working copy of #ways */
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loop_way:
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lsl x7, x6, x5
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orr x9, x12, x7 /* map way and level to cisw value */
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lsl x7, x4, x2
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orr x9, x9, x7 /* map set number to cisw value */
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tbz w1, #0, 1f
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dc isw, x9
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b 2f
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1: dc cisw, x9 /* clean & invalidate by set/way */
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2: subs x6, x6, #1 /* decrement the way */
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b.ge loop_way
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subs x4, x4, #1 /* decrement the set */
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b.ge loop_set
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ret
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ENDPROC(__asm_dcache_level)
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/*
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* void __asm_flush_dcache_all(int invalidate_only)
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*
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* x0: 0 clean & invalidate, 1 invalidate only
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*
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* flush or invalidate all data cache by SET/WAY.
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*/
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ENTRY(__asm_dcache_all)
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mov x1, x0
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dsb sy
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mrs x10, clidr_el1 /* read clidr_el1 */
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lsr x11, x10, #24
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and x11, x11, #0x7 /* x11 <- loc */
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cbz x11, finished /* if loc is 0, exit */
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mov x15, lr
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mov x0, #0 /* start flush at cache level 0 */
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/* x0 <- cache level */
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/* x10 <- clidr_el1 */
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/* x11 <- loc */
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/* x15 <- return address */
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loop_level:
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lsl x12, x0, #1
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add x12, x12, x0 /* x0 <- tripled cache level */
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lsr x12, x10, x12
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and x12, x12, #7 /* x12 <- cache type */
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cmp x12, #2
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b.lt skip /* skip if no cache or icache */
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bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
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skip:
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add x0, x0, #1 /* increment cache level */
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cmp x11, x0
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b.gt loop_level
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mov x0, #0
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msr csselr_el1, x0 /* restore csselr_el1 */
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dsb sy
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isb
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mov lr, x15
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finished:
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ret
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ENDPROC(__asm_dcache_all)
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ENTRY(__asm_flush_dcache_all)
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mov x0, #0
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b __asm_dcache_all
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ENDPROC(__asm_flush_dcache_all)
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ENTRY(__asm_invalidate_dcache_all)
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mov x0, #0x1
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b __asm_dcache_all
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ENDPROC(__asm_invalidate_dcache_all)
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/*
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* void __asm_flush_dcache_range(start, end)
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*
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* clean & invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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ENTRY(__asm_flush_dcache_range)
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isb
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mrs x3, ctr_el0
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lsr x3, x3, #16
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and x3, x3, #0xf
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc civac, x0 /* clean & invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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isb
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ret
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ENDPROC(__asm_flush_dcache_range)
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/*
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* void __asm_invalidate_dcache_range(start, end)
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*
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* invalidate data cache in the range
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*
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* x0: start address
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* x1: end address
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*/
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ENTRY(__asm_invalidate_dcache_range)
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mrs x3, ctr_el0
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ubfm x3, x3, #16, #19
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mov x2, #4
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lsl x2, x2, x3 /* cache line size */
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/* x2 <- minimal cache line size in cache system */
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sub x3, x2, #1
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bic x0, x0, x3
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1: dc ivac, x0 /* invalidate data or unified cache */
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add x0, x0, x2
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cmp x0, x1
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b.lo 1b
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dsb sy
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isb
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ret
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ENDPROC(__asm_invalidate_dcache_range)
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/*
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* void __asm_invalidate_icache_all(void)
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*
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* invalidate all tlb entries.
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*/
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ENTRY(__asm_invalidate_icache_all)
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ic ialluis
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isb sy
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ret
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ENDPROC(__asm_invalidate_icache_all)
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ENTRY(__asm_invalidate_l3_dcache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(__asm_invalidate_l3_dcache)
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.weak __asm_invalidate_l3_dcache
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ENTRY(__asm_flush_l3_dcache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(__asm_flush_l3_dcache)
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.weak __asm_flush_l3_dcache
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ENTRY(__asm_invalidate_l3_icache)
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mov x0, #0 /* return status as success */
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ret
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ENDPROC(__asm_invalidate_l3_icache)
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.weak __asm_invalidate_l3_icache
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/*
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* void __asm_switch_ttbr(ulong new_ttbr)
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*
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* Safely switches to a new page table.
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*/
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ENTRY(__asm_switch_ttbr)
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/* x2 = SCTLR (alive throghout the function) */
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switch_el x4, 3f, 2f, 1f
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3: mrs x2, sctlr_el3
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b 0f
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2: mrs x2, sctlr_el2
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b 0f
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1: mrs x2, sctlr_el1
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0:
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/* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
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movn x1, #(CR_M | CR_C | CR_I)
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and x1, x2, x1
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switch_el x4, 3f, 2f, 1f
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3: msr sctlr_el3, x1
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b 0f
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2: msr sctlr_el2, x1
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b 0f
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1: msr sctlr_el1, x1
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0: isb
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/* This call only clobbers x30 (lr) and x9 (unused) */
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mov x3, x30
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bl __asm_invalidate_tlb_all
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/* From here on we're running safely with caches disabled */
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/* Set TTBR to our first argument */
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switch_el x4, 3f, 2f, 1f
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3: msr ttbr0_el3, x0
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b 0f
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2: msr ttbr0_el2, x0
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b 0f
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1: msr ttbr0_el1, x0
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0: isb
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/* Restore original SCTLR and thus enable caches again */
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switch_el x4, 3f, 2f, 1f
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3: msr sctlr_el3, x2
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b 0f
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2: msr sctlr_el2, x2
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b 0f
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1: msr sctlr_el1, x2
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0: isb
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ret x3
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ENDPROC(__asm_switch_ttbr)
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ENTRY(__asm_invalidate_tlb_all)
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switch_el x9, 3f, 2f, 1f
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3: tlbi alle3
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dsb sy
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isb
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b 0f
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2: tlbi alle2
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dsb sy
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isb
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b 0f
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1: tlbi vmalle1
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dsb sy
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isb
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0:
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ret
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ENDPROC(__asm_invalidate_tlb_all)
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@ -20,6 +20,10 @@ Modification:
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*************************************************/
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#include "l1_cache.h"
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extern void __asm_flush_dcache_all();
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extern void __asm_flush_l3_dcache();
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extern void __asm_invalidate_icache_all();
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extern void __asm_invalidate_l3_icache();
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void InvalidateL1Dcache(uintptr_t start, uintptr_t end)
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{
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@ -153,34 +157,38 @@ void FlushL1Dcache(uintptr_t start, uintptr_t end)
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void FlushL1DcacheAll(void)
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{
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uint64_t ccsidr_el1; // Cache Size ID
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int num_sets; // number of sets
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int num_ways; // number of ways
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uint32_t wayset; // wayset parameter
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// uint64_t ccsidr_el1; // Cache Size ID
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// int num_sets; // number of sets
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// int num_ways; // number of ways
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// uint32_t wayset; // wayset parameter
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__asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID
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// __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID
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// Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1
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num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1;
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num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1;
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// // Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1
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// num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1;
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// num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1;
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// clean and invalidate all lines (all Sets in all ways)
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for (int way = 0; way < num_ways; way++) {
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for (int set = 0; set < num_sets; set++) {
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wayset = (way << 30) | (set << 5);
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__asm__ __volatile__("dc cisw, %0" : : "r"(wayset));
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}
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}
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// // clean and invalidate all lines (all Sets in all ways)
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// for (int way = 0; way < num_ways; way++) {
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// for (int set = 0; set < num_sets; set++) {
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// wayset = (way << 30) | (set << 5);
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// __asm__ __volatile__("dc cisw, %0" : : "r"(wayset));
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// }
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// }
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// All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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DSB();
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// // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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// DSB();
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__asm_flush_dcache_all();
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__asm_flush_l3_dcache();
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}
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void InvalidateL1IcacheAll()
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{
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__asm__ __volatile__("ic iallu\n\t");
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// synchronize context on this processor
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ISB();
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// __asm__ __volatile__("ic iallu\n\t");
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// // synchronize context on this processor
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// ISB();
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__asm_invalidate_icache_all();
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__asm_invalidate_l3_icache();
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}
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void InvalidateL1Icache(uintptr_t start, uintptr_t end)
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@ -92,7 +92,7 @@ static inline void invalidate_icache(uintptr_t start, uintptr_t end)
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static inline void invalidate_icache_all(void)
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{
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// InvalidateL1IcacheAll();
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InvalidateL1IcacheAll();
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}
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/****************************************************************************
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@ -151,7 +151,7 @@ static inline void flush_dcache(uintptr_t start, uintptr_t end)
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static inline void flush_dcache_all(void)
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{
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// FlushL1DcacheAll();
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FlushL1DcacheAll();
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// FlushL2CacheAll();
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}
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@ -30,8 +30,8 @@ int IPC_DO_SERVE_FUNC(Ipc_hello_string)(char* buf, int* len)
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return 0;
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}
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// IPC_SERVER_INTERFACE(Ipc_add, 2);
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IPC_SERVER_THREAD_INTERFACE(Ipc_add, 2);
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IPC_SERVER_INTERFACE(Ipc_add, 2);
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//IPC_SERVER_THREAD_INTERFACE(Ipc_add, 2);
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IPC_SERVER_INTERFACE(Ipc_hello_string, 2);
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IPC_SERVER_REGISTER_INTERFACES(IpcSimpleServer, 2, Ipc_hello_string, Ipc_add);
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