forked from xuos/xiuos
Merge branch 'rk3568' of https://gitlink.org.cn/tuyuyang/xiuos into rk3568
This commit is contained in:
lr
commit
b8cdfbfd8a
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@ -4,7 +4,7 @@ MAKEFLAGS += --no-print-directory
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.PHONY:COMPILE_APP COMPILE_KERNEL
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riscv_support :=
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arm_support += imx6q-sabrelite zynq7000-zc702 ok1028a-c
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arm_support += imx6q-sabrelite zynq7000-zc702 3568
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emulator_support +=
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support := $(riscv_support) $(arm_support) $(emulator_support)
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SRC_DIR :=
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@ -34,8 +34,8 @@ export UBIQUITOUS_ROOT ?= ..
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ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
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include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/config.mk
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endif
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ifneq ($(findstring $(BOARD), ok1028a-c), )
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include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/config.mk
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ifneq ($(findstring $(BOARD), 3568), )
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include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/config.mk
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endif
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export BSP_BUILD_DIR := $(KERNEL_ROOT)
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export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools
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@ -0,0 +1,936 @@
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|||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/hardkernel_init.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/kern_init.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/clock/clock_common_op.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/core.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.c \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/context_switch.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/context_switch.S
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/smp.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/boot.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/cortexA55.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/cortexA55.S
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/clock.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/clock.c \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/include/generic_timer.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/clock/clock_common_op.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/bootmmu.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/mmio_access.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/registers.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/mmu.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/mmu.c \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/pagetable_attr.o: \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/pagetable_attr.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/spinlock.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
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||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/trap_common.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/exception_registers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_common_opa.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/mmio_access.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/trap.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/exception_registers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/error_debug.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/error_debug.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/exception_registers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/sys_exit.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_exit.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/sys_state.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/sys_mmap.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_mmap.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/kalloc.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/sys_kill.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_kill.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/build/sys_semaphore.o: \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_semaphore.c \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/ksemaphore.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/irq_numbers.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/syscall.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/bitmap64.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h \
|
||||
/home/xiuos/Desktop/xiuos/Ubiquitous/XiZi_AIoT/hardkernel/mmu/mmu_common.h
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# The following three platforms support compatiable instructions.
|
||||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := armv8-a
|
||||
endif
|
||||
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
# The following three platforms support compatiable instructions.
|
||||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
SRC_DIR := cortex-a72
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := cortex-a55
|
||||
endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ Modification:
|
|||
1. first version
|
||||
*************************************************/
|
||||
|
||||
/*********cortex-a72 general register************
|
||||
/*********cortex-a55 general register************
|
||||
EL0 | EL1 | EL2 | EL3
|
||||
|
||||
x0;
|
||||
|
|
@ -63,7 +63,7 @@ Modification:
|
|||
x28;
|
||||
x29;
|
||||
x30;
|
||||
*********cortex-a72 special register************
|
||||
*********cortex-a55 special register************
|
||||
XZR
|
||||
PC
|
||||
SP_EL0 SP_EL1 SP_EL2 SP_EL3
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
/**
|
||||
* @file core.h
|
||||
* @brief cortex-a72 core function
|
||||
* @brief cortex-a55 core function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2024.04.11
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
/*************************************************
|
||||
File name: core.h
|
||||
Description: cortex-a72 core function
|
||||
Description: cortex-a55 core function
|
||||
Others:
|
||||
History:
|
||||
Author: AIIT XUOS Lab
|
||||
|
|
@ -71,23 +71,14 @@ Modification:
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "cortex_a72.h"
|
||||
#include "cortex_a55.h"
|
||||
|
||||
#define NR_CPU 4 // maximum number of CPUs
|
||||
#define NR_CPU 1 // maximum number of CPUs
|
||||
|
||||
__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
|
||||
{
|
||||
uint64_t val = 0;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mrs %0, spsr_el1"
|
||||
: "=r"(val)
|
||||
:
|
||||
:);
|
||||
val &= ~DIS_INT;
|
||||
val &= ~SPSR_MODE_MASK;
|
||||
val |= ARM_MODE_EL0_t;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
|
|
@ -45,30 +45,36 @@ ENTRY( _ENTRY )
|
|||
ENTRY( _boot_start )
|
||||
|
||||
MEMORY {
|
||||
phy_ddr3 (rwx) : ORIGIN = 0x0000000040000000, LENGTH = 1024M
|
||||
vir_ddr3 (rwx) : ORIGIN = 0x0000006040635000, LENGTH = 1024M
|
||||
phy_ddr3 (rwx) : ORIGIN = 0x0000000010000000, LENGTH = 1024M
|
||||
vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.start_sec : {
|
||||
. = ALIGN(0x1000);
|
||||
. = ORIGIN(phy_ddr3);
|
||||
/* initialization start checkpoint. */
|
||||
|
||||
_start_image_addr = .;
|
||||
|
||||
boot.o(.text)
|
||||
bootmmu.o(.text .text.*)
|
||||
/* ns16550.o(.text .text.*) */
|
||||
|
||||
boot.o(.rodata .rodata.*)
|
||||
bootmmu.o(.rodata .rodata.*)
|
||||
/* ns16550.o(.rodata .rodata.*) */
|
||||
|
||||
boot.o(.data .data.*)
|
||||
bootmmu.o(.data .data.*)
|
||||
/* ns16550.o(.data .data.*) */
|
||||
|
||||
PROVIDE(boot_start_addr = .);
|
||||
|
||||
boot.o(.bss .bss.* COMMON)
|
||||
bootmmu.o(.bss .bss.* COMMON)
|
||||
/* ns16550.o(.bss .bss.* COMMON) */
|
||||
|
||||
/* stack for booting code. */
|
||||
. = ALIGN(0x1000);
|
||||
|
|
@ -81,7 +87,7 @@ SECTIONS
|
|||
PROVIDE(boot_end_addr = .);
|
||||
} > phy_ddr3
|
||||
|
||||
.text : AT(0x40635000) {
|
||||
.text : AT(0x1040E000) {
|
||||
. = ALIGN(0x1000);
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
} > vir_ddr3
|
||||
|
|
@ -103,17 +109,19 @@ SECTIONS
|
|||
PROVIDE(_binary_default_fs_start = .);
|
||||
*(.rawdata_memfs*)
|
||||
PROVIDE(_binary_default_fs_end = .);
|
||||
PROVIDE(__init_array_start = .);
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > vir_ddr3
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(kernel_data_begin = .);
|
||||
_image_size = . - 0x0000006010000000;
|
||||
|
||||
_image_size = . - 0x0000006040000000;
|
||||
.bss : {
|
||||
PROVIDE(kernel_data_begin = .);
|
||||
PROVIDE(__bss_start__ = .);
|
||||
*(.bss .bss.* COMMON)
|
||||
PROVIDE(__bss_end__ = .);
|
||||
} > vir_ddr3
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(__bss_end__ = .);
|
||||
PROVIDE(kernel_data_end = .);
|
||||
} > vir_ddr3
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
SRC_FILES := boot.S \
|
||||
smp.c \
|
||||
cortexA72.S
|
||||
cortexA55.S
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
#include "core.h"
|
||||
|
||||
#define HCR_VALUE (1 << 31)
|
||||
#define SPSR_EL2_VALUE (7 << 6) | (5 << 0)
|
||||
#define SCTLR_EL1_VALUE (0x30D00800)
|
||||
|
||||
.section ".text", "ax"
|
||||
.global _boot_start
|
||||
.global primary_cpu_init
|
||||
.global el2_setup
|
||||
|
||||
_boot_start:
|
||||
bl el2_setup
|
||||
|
||||
/* set NSACR, both Secure and Non-secure access are allowed to NEON */
|
||||
mov x0, #(3 << 20)
|
||||
msr cpacr_el1, x0
|
||||
isb
|
||||
|
||||
// clear some registers
|
||||
msr elr_el1, XZR
|
||||
|
||||
ldr x0, =stacks_top
|
||||
mov x1, #MODE_STACK_SIZE
|
||||
|
||||
// get cpu id, and subtract the offset from the stacks base address
|
||||
mrs x2, mpidr_el1
|
||||
and x2, x2, #0x3
|
||||
mov x5, x2
|
||||
mul x3, x2, x1
|
||||
sub x0, x0, x3
|
||||
mov sp, x0
|
||||
|
||||
mov x2, #ARM_MODE_EL1_h | DIS_INT
|
||||
msr spsr_el1, x2
|
||||
|
||||
// bl el2_setup
|
||||
|
||||
// check cpu id - cpu0 is primary cpu
|
||||
mrs x2, mpidr_el1
|
||||
and x2, x2, #0x3
|
||||
mov x5, x2
|
||||
cmp x5, #0
|
||||
beq primary_cpu_init
|
||||
bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM
|
||||
|
||||
bl .
|
||||
|
||||
primary_cpu_init:
|
||||
/* init .bss */
|
||||
/* clear the .bss section (zero init) */
|
||||
ldr x1, =boot_start_addr
|
||||
ldr x2, =boot_end_addr
|
||||
mov x3, #0
|
||||
1:
|
||||
cmp x1, x2
|
||||
stp x3, x3, [x1], #16
|
||||
b.lt 1b
|
||||
|
||||
bl bootmain
|
||||
|
||||
.func el2_setup
|
||||
el2_setup:
|
||||
mrs x0, CurrentEL
|
||||
lsr x0, x0, #2
|
||||
and x0, x0, #3
|
||||
cmp x0, #2
|
||||
beq 1f
|
||||
ret
|
||||
|
||||
/* Hyp configuration. */
|
||||
1:
|
||||
mov x0, #(1 << 31)
|
||||
msr hcr_el2, x0
|
||||
|
||||
/* Generic timers. */
|
||||
mrs x0, cnthctl_el2
|
||||
orr x0, x0, #3 // Enable EL1 physicaltimers
|
||||
msr cnthctl_el2, x0
|
||||
|
||||
/* Populate ID registers. */
|
||||
mrs x0, midr_el1
|
||||
mrs x1, mpidr_el1
|
||||
msr vpidr_el2, x0
|
||||
msr vmpidr_el2, x1
|
||||
|
||||
/* Disable Coprocessor traps. */
|
||||
mov x0, #0x33ff
|
||||
msr cptr_el2, x0 // Disable copro. traps to EL2
|
||||
|
||||
msr hstr_el2, xzr // Disable CP15 traps to EL2
|
||||
|
||||
mov x0, sp
|
||||
msr sp_el1, x0
|
||||
|
||||
mrs x0, sctlr_el1
|
||||
orr x0, x0, #(1 << 0)
|
||||
bic x0, x0, #(1 << 1)
|
||||
orr x0, x0, #(1 << 2)
|
||||
msr sctlr_el1, x0
|
||||
|
||||
/* spsr */
|
||||
mov x0, #SPSR_EL2_VALUE
|
||||
msr spsr_el2, x0
|
||||
msr elr_el2, lr
|
||||
eret
|
||||
.endfunc
|
||||
|
||||
.end
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
export CROSS_COMPILE ?= aarch64-none-elf-
|
||||
export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
|
||||
export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
|
||||
export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
|
||||
export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
|
||||
# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
|
||||
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
|
||||
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds -Wl,--start-group,-lgcc,-lc,--end-group
|
||||
export CXXFLAGS :=
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DCHIP_LS1028
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
/*!
|
||||
* @file cortexA72.s
|
||||
* @brief This file contains cortexA72 functions
|
||||
* @file cortexA55.s
|
||||
* @brief This file contains cortexA55 functions
|
||||
*
|
||||
*/
|
||||
/*************************************************
|
||||
File name: cortexA72.S
|
||||
File name: cortexA55.S
|
||||
Description: This file contains cortexA9 functions
|
||||
Others:
|
||||
History:
|
||||
1. Date: 202-05-08
|
||||
1. Date: 2024-05-08
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. No modifications
|
||||
|
|
@ -32,6 +32,6 @@ psci_call:
|
|||
|
||||
|
||||
# ------------------------------------------------------------
|
||||
# End of cortexA72.s
|
||||
# End of cortexA55.s
|
||||
# ------------------------------------------------------------
|
||||
.end
|
||||
|
|
@ -28,16 +28,16 @@
|
|||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/**
|
||||
* @file cortex_a72.h
|
||||
* @brief some cortex A72 core functions
|
||||
* @file cortex_a55.h
|
||||
* @brief some cortex A55 core functions
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2024.04.24
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: cortex_a72.h
|
||||
Description: some cortex A72 core functions
|
||||
File name: cortex_a55.h
|
||||
Description: some cortex A55 core functions
|
||||
Others:
|
||||
History:
|
||||
Author: AIIT XUOS Lab
|
||||
|
|
@ -45,8 +45,8 @@ Modification:
|
|||
1. No modifications
|
||||
*************************************************/
|
||||
|
||||
#if !defined(__CORTEX_A72_H__)
|
||||
#define __CORTEX_A72_H__
|
||||
#if !defined(__CORTEX_A55_H__)
|
||||
#define __CORTEX_A55_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
|
@ -231,4 +231,4 @@ void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif //__CORTEX_A72_H__
|
||||
#endif //__CORTEX_A55_H__
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
// #include "memlayout.h"
|
||||
#include "core.h"
|
||||
// #include "registers.h"
|
||||
// #include "cortex_a72.h"
|
||||
// qemu -kernel loads the kernel at 0x40000000
|
||||
// and causes each CPU to jump there.
|
||||
// kernel.ld causes the following code to
|
||||
// be placed at 0x40000000.
|
||||
.section ".text"
|
||||
//.global _entry
|
||||
.global _boot_start
|
||||
.global primary_cpu_init
|
||||
|
||||
_boot_start:
|
||||
// set up a stack for C.
|
||||
// stack0 is declared in start.c,
|
||||
// with a 4096-byte stack per CPU.
|
||||
// sp = stack0 + ((cpuid+1) * 4096)
|
||||
// cpuid = mpidr_el1 & 0xff
|
||||
// save r0 for cores 1-3, r0 arg field passed by ROM
|
||||
// r0 is a function pointer for secondary cpus
|
||||
|
||||
// mov x4, x0
|
||||
|
||||
mrs x0, spsr_el1 /* Enter EL1 (Exception Level 1) */
|
||||
bic x0, x0, #0x1f
|
||||
MOV x1, #0xC5
|
||||
ORR x0, x0, x1
|
||||
msr spsr_el1, x0
|
||||
|
||||
|
||||
/* set NSACR, both Secure and Non-secure access are allowed to NEON */
|
||||
MRS X1, CPACR_EL1
|
||||
ORR X1, X1, #(0X3 << 20)
|
||||
MSR CPACR_EL1, X1
|
||||
ISB
|
||||
|
||||
// clear some registers
|
||||
msr elr_el1, XZR
|
||||
|
||||
ldr x0, =stacks_top
|
||||
mov x1, #MODE_STACK_SIZE
|
||||
|
||||
// get cpu id, and subtract the offset from the stacks base address
|
||||
mrs x2, mpidr_el1
|
||||
and x2, x2, #0x3
|
||||
mov x5, x2
|
||||
mul x3, x2, x1
|
||||
sub x0, x0, x3
|
||||
|
||||
MOV X2, #ARM_MODE_EL1_h | DIS_INT
|
||||
MSR SPSR_EL1, X2
|
||||
mov sp, x0
|
||||
SUB x0, x0,x1
|
||||
|
||||
// check cpu id - cpu0 is primary cpu
|
||||
cmp x5, #0
|
||||
beq primary_cpu_init
|
||||
bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM
|
||||
|
||||
bl .
|
||||
|
||||
primary_cpu_init:
|
||||
/* init .bss */
|
||||
/* clear the .bss section (zero init) */
|
||||
ldr x1, =boot_start_addr
|
||||
ldr x2, =boot_end_addr
|
||||
mov x3, #0
|
||||
1:
|
||||
cmp x1, x2
|
||||
stp x3, x3, [x1], #16
|
||||
b.lt 1b
|
||||
|
||||
// branch to c library entry point
|
||||
mov x0, #0 // argc
|
||||
mov x1, #0 // argv
|
||||
mov x2, #0 // env
|
||||
|
||||
bl bootmain
|
||||
|
||||
.end
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
|
||||
SRC_DIR := cortex-a9
|
||||
endif
|
||||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
SRC_DIR := cortex-a72
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := cortex-a55
|
||||
endif
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := armv8-a
|
||||
endif
|
||||
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
SRC_DIR := cortex-a72
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := cortex-a55
|
||||
endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -22,27 +22,27 @@
|
|||
|
||||
static void enable_timer()
|
||||
{
|
||||
uint32_t c = r_cntv_ctl_el0();
|
||||
uint32_t c = r_cntp_ctl_el0();
|
||||
c |= CNTV_CTL_ENABLE;
|
||||
c &= ~CNTV_CTL_IMASK;
|
||||
w_cntv_ctl_el0(c);
|
||||
w_cntp_ctl_el0(c);
|
||||
}
|
||||
|
||||
static void disable_timer()
|
||||
{
|
||||
uint32_t c = r_cntv_ctl_el0();
|
||||
uint32_t c = r_cntp_ctl_el0();
|
||||
c |= CNTV_CTL_IMASK;
|
||||
c &= ~CNTV_CTL_ENABLE;
|
||||
w_cntv_ctl_el0(c);
|
||||
w_cntp_ctl_el0(c);
|
||||
}
|
||||
|
||||
static void reload_timer()
|
||||
{
|
||||
// interval 100ms
|
||||
static uint32_t ms = 10;
|
||||
// interval 1ms
|
||||
static uint32_t ms = 1;
|
||||
uint32_t interval = ms * 1000;
|
||||
uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000);
|
||||
w_cntv_tval_el0(interval_clk);
|
||||
w_cntp_tval_el0(interval_clk);
|
||||
}
|
||||
|
||||
void _sys_clock_init()
|
||||
|
|
@ -54,7 +54,7 @@ void _sys_clock_init()
|
|||
|
||||
static uint32_t _get_clock_int()
|
||||
{
|
||||
return 27;
|
||||
return 30;
|
||||
}
|
||||
|
||||
static uint64_t _get_tick()
|
||||
|
|
@ -15,28 +15,28 @@
|
|||
#include <stdint.h>
|
||||
|
||||
// armv8 generic timer
|
||||
static inline uint32_t r_cntv_ctl_el0()
|
||||
static inline uint32_t r_cntp_ctl_el0()
|
||||
{
|
||||
uint32_t x;
|
||||
__asm__ volatile("mrs %0, cntv_ctl_el0" : "=r"(x));
|
||||
__asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x));
|
||||
return x;
|
||||
}
|
||||
|
||||
static inline void w_cntv_ctl_el0(uint32_t x)
|
||||
static inline void w_cntp_ctl_el0(uint32_t x)
|
||||
{
|
||||
__asm__ volatile("msr cntv_ctl_el0, %0" : : "r"(x));
|
||||
__asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x));
|
||||
}
|
||||
|
||||
static inline uint32_t r_cntv_tval_el0()
|
||||
static inline uint32_t r_cntp_tval_el0()
|
||||
{
|
||||
uint32_t x;
|
||||
__asm__ volatile("mrs %0, cntv_tval_el0" : "=r"(x));
|
||||
__asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x));
|
||||
return x;
|
||||
}
|
||||
|
||||
static inline void w_cntv_tval_el0(uint32_t x)
|
||||
static inline void w_cntp_tval_el0(uint32_t x)
|
||||
{
|
||||
__asm__ volatile("msr cntv_tval_el0, %0" : : "r"(x));
|
||||
__asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x));
|
||||
}
|
||||
|
||||
static inline uint64_t r_cntvct_el0()
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := armv8-a
|
||||
endif
|
||||
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_DIR := cortex-a72
|
||||
SRC_DIR := cortex-a55
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -28,13 +28,16 @@ Modification:
|
|||
*************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
#include "exception_registers.h"
|
||||
|
||||
#include "assert.h"
|
||||
#include "core.h"
|
||||
#include "exception_registers.h"
|
||||
#include "multicores.h"
|
||||
#include "syscall.h"
|
||||
#include "task.h"
|
||||
|
||||
#include "mmu.h"
|
||||
|
||||
extern void dabort_handler(struct trapframe* r);
|
||||
extern void iabort_handler(struct trapframe* r);
|
||||
|
||||
|
|
@ -73,7 +76,6 @@ void syscall_arch_handler(struct trapframe* tf)
|
|||
|
||||
uint64_t esr = r_esr_el1();
|
||||
uint64_t ec = (esr >> 0x1A) & 0x3F;
|
||||
w_esr_el1(0);
|
||||
switch (ec) {
|
||||
case 0B010101:
|
||||
software_irq_dispatch(tf);
|
||||
|
|
@ -87,11 +89,30 @@ void syscall_arch_handler(struct trapframe* tf)
|
|||
iabort_handler(tf);
|
||||
break;
|
||||
default: {
|
||||
ERROR("USYSCALL: unexpected ec: %016lx", esr);
|
||||
ERROR("USYSCALL: unexpected\n");
|
||||
ERROR(" esr: %016lx\n", esr);
|
||||
ERROR(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
|
||||
w_esr_el1(0);
|
||||
extern void dump_tf(struct trapframe * tf);
|
||||
dump_tf(tf);
|
||||
|
||||
uint32_t sctlr = 0;
|
||||
SCTLR_R(sctlr);
|
||||
DEBUG("SCTLR: %x\n", sctlr);
|
||||
uint32_t spsr = 0;
|
||||
__asm__ volatile("mrs %0, spsr_el1" : "=r"(spsr)::"memory");
|
||||
DEBUG("SPSR: %x\n", spsr);
|
||||
uint64_t tcr = 0;
|
||||
__asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr)::"memory");
|
||||
DEBUG("TCR: %x\n", tcr);
|
||||
uint64_t mair = 0;
|
||||
__asm__ volatile("mrs %0, mair_el1" : "=r"(mair)::"memory");
|
||||
DEBUG("MAIR: %x\n", mair);
|
||||
|
||||
// kill error task
|
||||
xizi_enter_kernel();
|
||||
assert(cur_cpu()->task != NULL);
|
||||
ERROR("Error Task: %s\n", cur_cpu()->task->name);
|
||||
sys_exit(cur_cpu()->task);
|
||||
context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler);
|
||||
panic("dabort end should never be reashed.\n");
|
||||
|
|
@ -29,7 +29,7 @@ Modification:
|
|||
#include <string.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "cortex_a72.h"
|
||||
#include "cortex_a55.h"
|
||||
#include "exception_registers.h"
|
||||
#include "gicv3_common_opa.h"
|
||||
#include "trap_common.h"
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S
|
||||
|
||||
ifeq ($(BOARD), ok1028a-c)
|
||||
ifeq ($(BOARD), 3568)
|
||||
SRC_DIR := gicv3
|
||||
SRC_FILES += $(BOARD)/
|
||||
endif
|
||||
|
|
@ -39,51 +39,53 @@ Modification:
|
|||
2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler())
|
||||
*************************************************/
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "exception_registers.h"
|
||||
|
||||
#include "assert.h"
|
||||
#include "core.h"
|
||||
#include "log.h"
|
||||
#include "multicores.h"
|
||||
#include "spinlock.h"
|
||||
#include "task.h"
|
||||
#include "trap_common.h"
|
||||
|
||||
void dump_tf(struct trapframe* tf)
|
||||
{
|
||||
KPrintf(" sp: 0x%x\n", tf->sp);
|
||||
KPrintf(" pc: 0x%x\n", tf->pc);
|
||||
KPrintf(" spsr: 0x%x\n", tf->spsr);
|
||||
KPrintf(" x0: 0x%x\n", tf->x0);
|
||||
KPrintf(" x1: 0x%x\n", tf->x1);
|
||||
KPrintf(" x2: 0x%x\n", tf->x2);
|
||||
KPrintf(" x3: 0x%x\n", tf->x3);
|
||||
KPrintf(" x4: 0x%x\n", tf->x4);
|
||||
KPrintf(" x5: 0x%x\n", tf->x5);
|
||||
KPrintf(" x6: 0x%x\n", tf->x6);
|
||||
KPrintf(" x7: 0x%x\n", tf->x7);
|
||||
KPrintf(" x8: 0x%x\n", tf->x8);
|
||||
KPrintf(" x9: 0x%x\n", tf->x9);
|
||||
KPrintf(" x10: 0x%x\n", tf->x10);
|
||||
KPrintf(" x11: 0x%x\n", tf->x11);
|
||||
KPrintf(" x12: 0x%x\n", tf->x12);
|
||||
KPrintf(" x13: 0x%x\n", tf->x13);
|
||||
KPrintf(" x14: 0x%x\n", tf->x14);
|
||||
KPrintf(" x15: 0x%x\n", tf->x15);
|
||||
KPrintf(" x16: 0x%x\n", tf->x16);
|
||||
KPrintf(" x17: 0x%x\n", tf->x17);
|
||||
KPrintf(" x18: 0x%x\n", tf->x18);
|
||||
KPrintf(" x19: 0x%x\n", tf->x19);
|
||||
KPrintf(" x20: 0x%x\n", tf->x20);
|
||||
KPrintf(" x21: 0x%x\n", tf->x21);
|
||||
KPrintf(" x22: 0x%x\n", tf->x22);
|
||||
KPrintf(" x23: 0x%x\n", tf->x23);
|
||||
KPrintf(" x24: 0x%x\n", tf->x24);
|
||||
KPrintf(" x25: 0x%x\n", tf->x25);
|
||||
KPrintf(" x26: 0x%x\n", tf->x26);
|
||||
KPrintf(" x27: 0x%x\n", tf->x27);
|
||||
KPrintf(" x28: 0x%x\n", tf->x28);
|
||||
KPrintf(" x29: 0x%x\n", tf->x29);
|
||||
KPrintf(" x30: 0x%x\n", tf->x30);
|
||||
KPrintf(" sp: 0x%016lx\n", tf->sp);
|
||||
KPrintf(" pc: 0x%016lx\n", tf->pc);
|
||||
KPrintf(" spsr: 0x%016lx\n", tf->spsr);
|
||||
KPrintf(" x0: 0x%016lx\n", tf->x0);
|
||||
KPrintf(" x1: 0x%016lx\n", tf->x1);
|
||||
KPrintf(" x2: 0x%016lx\n", tf->x2);
|
||||
KPrintf(" x3: 0x%016lx\n", tf->x3);
|
||||
KPrintf(" x4: 0x%016lx\n", tf->x4);
|
||||
KPrintf(" x5: 0x%016lx\n", tf->x5);
|
||||
KPrintf(" x6: 0x%016lx\n", tf->x6);
|
||||
KPrintf(" x7: 0x%016lx\n", tf->x7);
|
||||
KPrintf(" x8: 0x%016lx\n", tf->x8);
|
||||
KPrintf(" x9: 0x%016lx\n", tf->x9);
|
||||
KPrintf(" x10: 0x%016lx\n", tf->x10);
|
||||
KPrintf(" x11: 0x%016lx\n", tf->x11);
|
||||
KPrintf(" x12: 0x%016lx\n", tf->x12);
|
||||
KPrintf(" x13: 0x%016lx\n", tf->x13);
|
||||
KPrintf(" x14: 0x%016lx\n", tf->x14);
|
||||
KPrintf(" x15: 0x%016lx\n", tf->x15);
|
||||
KPrintf(" x16: 0x%016lx\n", tf->x16);
|
||||
KPrintf(" x17: 0x%016lx\n", tf->x17);
|
||||
KPrintf(" x18: 0x%016lx\n", tf->x18);
|
||||
KPrintf(" x19: 0x%016lx\n", tf->x19);
|
||||
KPrintf(" x20: 0x%016lx\n", tf->x20);
|
||||
KPrintf(" x21: 0x%016lx\n", tf->x21);
|
||||
KPrintf(" x22: 0x%016lx\n", tf->x22);
|
||||
KPrintf(" x23: 0x%016lx\n", tf->x23);
|
||||
KPrintf(" x24: 0x%016lx\n", tf->x24);
|
||||
KPrintf(" x25: 0x%016lx\n", tf->x25);
|
||||
KPrintf(" x26: 0x%016lx\n", tf->x26);
|
||||
KPrintf(" x27: 0x%016lx\n", tf->x27);
|
||||
KPrintf(" x28: 0x%016lx\n", tf->x28);
|
||||
KPrintf(" x29: 0x%016lx\n", tf->x29);
|
||||
KPrintf(" x30: 0x%016lx\n", tf->x30);
|
||||
}
|
||||
|
||||
void dabort_reason(struct trapframe* r)
|
||||
|
|
@ -91,8 +93,9 @@ void dabort_reason(struct trapframe* r)
|
|||
uint32_t fault_status, fault_address;
|
||||
__asm__ __volatile__("mrs %0, esr_el1" : "=r"(fault_status));
|
||||
__asm__ __volatile__("mrs %0, far_el1" : "=r"(fault_address));
|
||||
LOG("program counter: 0x%x caused\n", r->pc);
|
||||
LOG("data abort at 0x%x, status 0x%x\n", fault_address, fault_status);
|
||||
w_esr_el1(0);
|
||||
LOG("program counter: 0x%016lx caused\n", r->pc);
|
||||
LOG("data abort at 0x%016lx, status 0x%016lx\n", fault_address, fault_status);
|
||||
if ((fault_status & 0x3f) == 0x21) // Alignment failure
|
||||
KPrintf("reason: alignment\n");
|
||||
else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0
|
||||
|
|
@ -131,8 +134,9 @@ void iabort_reason(struct trapframe* r)
|
|||
uint32_t fault_status, fault_address;
|
||||
__asm__ __volatile__("mrs %0, esr_el1" : "=r"(fault_status));
|
||||
__asm__ __volatile__("mrs %0, far_el1" : "=r"(fault_address));
|
||||
LOG("program counter: 0x%x caused\n", r->pc);
|
||||
LOG("data abort at 0x%x, status 0x%x\n", fault_address, fault_status);
|
||||
LOG("program counter: 0x%016lx caused\n", r->pc);
|
||||
LOG("data abort at 0x%016lx, status 0x%016lx\n", fault_address, fault_status);
|
||||
w_esr_el1(0);
|
||||
if ((fault_status & 0x3f) == 0x21) // Alignment failure
|
||||
KPrintf("reason: alignment\n");
|
||||
else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0
|
||||
|
|
@ -30,8 +30,8 @@ Modification:
|
|||
|
||||
// clang-format off
|
||||
// interrupt controller GICv3
|
||||
#define GICV3 MMIO_P2V_WO(0x08000000ULL)
|
||||
#define GICV3_REDIST MMIO_P2V_WO(0x080a0000ULL)
|
||||
#define GICV3 MMIO_P2V_WO(0xFD400000ULL)
|
||||
#define GICV3_REDIST MMIO_P2V_WO(0xFD460000ULL)
|
||||
|
||||
#define D_CTLR 0x0
|
||||
#define D_TYPER 0x4
|
||||
|
|
@ -143,13 +143,13 @@ Modification:
|
|||
.balign 0x800
|
||||
alltraps:
|
||||
// Current EL with sp0
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
|
||||
// Current EL with spx
|
||||
.balign 0x80
|
||||
|
|
@ -157,9 +157,9 @@ alltraps:
|
|||
.balign 0x80
|
||||
b el1irq
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
|
||||
// Lower EL using aarch64
|
||||
.balign 0x80
|
||||
|
|
@ -167,18 +167,26 @@ alltraps:
|
|||
.balign 0x80
|
||||
b el0irq
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
|
||||
// Lower EL using aarch32
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b .
|
||||
b badtrap
|
||||
.balign 0x80
|
||||
b badtrap
|
||||
|
||||
badtrap:
|
||||
msr daifset, #0xf
|
||||
savereg
|
||||
|
||||
mov x0, sp
|
||||
bl kernel_intr_handler
|
||||
b .
|
||||
|
||||
el1sync:
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := armv8-a
|
||||
endif
|
||||
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ uint32_t boot_pgdir[NR_PDE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 };
|
|||
static void build_boot_pgdir()
|
||||
{
|
||||
// dev mem
|
||||
uint32_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SZ) >> LEVEL3_PDE_SHIFT;
|
||||
uint32_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SIZE) >> LEVEL3_PDE_SHIFT;
|
||||
for (uint32_t i = DEV_PHYMEM_BASE >> LEVEL3_PDE_SHIFT; i < dev_mem_end_idx; i++) {
|
||||
boot_pgdir[i] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0;
|
||||
boot_pgdir[MMIO_P2V_WO(i << LEVEL3_PDE_SHIFT) >> LEVEL3_PDE_SHIFT] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0;
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ Modification:
|
|||
/* Deivce memory layout */
|
||||
#define DEV_PHYMEM_BASE (0x00000000)
|
||||
#define DEV_VRTMEM_BASE (0x80000000)
|
||||
#define DEV_MEM_SZ (0x10000000)
|
||||
#define DEV_MEM_SIZE (0x10000000)
|
||||
|
||||
/* Kernel memory layout */
|
||||
#define KERN_MEM_BASE (0x90000000) // First kernel virtual address
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ Modification:
|
|||
/* Deivce memory layout */
|
||||
#define DEV_PHYMEM_BASE (0xE0000000)
|
||||
#define DEV_VRTMEM_BASE (0x80000000)
|
||||
#define DEV_MEM_SZ (0x1FFFFFFF)
|
||||
#define DEV_MEM_SIZE (0x1FFFFFFF)
|
||||
|
||||
/* Kernel memory layout */
|
||||
#define KERN_MEM_BASE (0xA0000000) // First kernel virtual address
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_DIR := cortex-a72
|
||||
SRC_DIR := cortex-a55
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -33,11 +33,11 @@ Modification:
|
|||
|
||||
#define ARCH_BIT 64
|
||||
|
||||
/* A72 physical memory layout */
|
||||
#define PHY_MEM_BASE (0x0000000040000000ULL)
|
||||
#define PHY_USER_FREEMEM_BASE (0x0000000046000000ULL)
|
||||
#define PHY_USER_FREEMEM_TOP (0x0000000048000000ULL)
|
||||
#define PHY_MEM_STOP (0x0000000048000000ULL)
|
||||
/* A55 physical memory layout */
|
||||
#define PHY_MEM_BASE (0x0000000010000000ULL)
|
||||
#define PHY_USER_FREEMEM_BASE (0x0000000030000000ULL)
|
||||
#define PHY_USER_FREEMEM_TOP (0x0000000040000000ULL)
|
||||
#define PHY_MEM_STOP (0x0000000040000000ULL)
|
||||
|
||||
/* PTE-PAGE_SIZE */
|
||||
#define LEVEL4_PTE_SHIFT 12
|
||||
|
|
@ -61,20 +61,20 @@ Modification:
|
|||
#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
|
||||
|
||||
/* Deivce memory layout */
|
||||
#define DEV_PHYMEM_BASE (0x0000000000000000ULL)
|
||||
#define DEV_VRTMEM_BASE (0x0000004000000000ULL)
|
||||
#define DEV_MEM_SZ (0x0000000010000000ULL)
|
||||
#define DEV_PHYMEM_BASE (0x00000000F0000000ULL)
|
||||
#define DEV_VRTMEM_BASE (0x00000040F0000000ULL)
|
||||
#define DEV_MEM_SIZE (0x0000000010000000ULL)
|
||||
|
||||
/* User memory layout */
|
||||
#define USER_STACK_SIZE PAGE_SIZE
|
||||
#define USER_MEM_BASE (0x0000000000000000ULL)
|
||||
#define USER_MEM_TOP DEV_VRTMEM_BASE
|
||||
#define USER_MEM_TOP (0x0000004000000000ULL)
|
||||
#define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
|
||||
#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL)
|
||||
#define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL)
|
||||
|
||||
/* Kernel memory layout */
|
||||
#define KERN_MEM_BASE (0x0000006040000000ULL) // First kernel virtual address
|
||||
#define KERN_MEM_BASE (0x0000006010000000ULL) // First kernel virtual address
|
||||
#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
|
||||
|
||||
#define V2P(a) (((uint64_t)(a)) - KERN_OFFSET)
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
/**
|
||||
* @file bootmmu.c
|
||||
* @brief build pagetable and enable mmu in boot time
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2024.04.26
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: bootmmu.c
|
||||
Description: build pagetable and enable mmu in boot time
|
||||
Others:
|
||||
History:
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. first version
|
||||
*************************************************/
|
||||
#include "core.h"
|
||||
#include "memlayout.h"
|
||||
#include "mmio_access.h"
|
||||
#include "mmu.h"
|
||||
#include "pagetable.h"
|
||||
#include "registers.h"
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
extern uint64_t kernel_data_end[];
|
||||
extern uint64_t kernel_data_begin[];
|
||||
|
||||
// clang-format off
|
||||
#define L2_TYPE_TAB 2
|
||||
#define L2_PTE_VALID 1
|
||||
|
||||
#define L3_TYPE_TAB 2
|
||||
#define L3_PTE_VALID 1
|
||||
|
||||
#define L4_TYPE_PAGE (3 << 0)
|
||||
#define L4_PTE_DEV ((0b00) << 2) // Device memory
|
||||
#define L4_PTE_NORMAL ((0b01) << 2) // Device memory
|
||||
#define L4_PTE_AF (1 << 10) // Data Access Permissions
|
||||
|
||||
#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never
|
||||
#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
|
||||
#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never
|
||||
|
||||
#define IDX_MASK (0b111111111)
|
||||
#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
|
||||
// clang-format on
|
||||
|
||||
uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
|
||||
uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
|
||||
uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
|
||||
static void build_boot_pgdir()
|
||||
{
|
||||
static bool built = false;
|
||||
if (!built) {
|
||||
uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
|
||||
|
||||
// dev mem
|
||||
boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
|
||||
uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE);
|
||||
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
|
||||
boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
|
||||
|
||||
for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
|
||||
boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN;
|
||||
if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
|
||||
boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
|
||||
} else {
|
||||
// boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
|
||||
boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
|
||||
}
|
||||
|
||||
cur_mem_paddr += PAGE_SIZE;
|
||||
}
|
||||
|
||||
// if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
|
||||
// boot_dev_l3pgdir[i] = cur_mem_paddr | 0x401;
|
||||
// } else {
|
||||
// boot_dev_l3pgdir[i] = cur_mem_paddr | 0x711;
|
||||
// }
|
||||
// cur_mem_paddr += PAGE_SIZE * 0x200;
|
||||
}
|
||||
|
||||
// identical mem
|
||||
boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
|
||||
cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE);
|
||||
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
|
||||
boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
|
||||
|
||||
for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
|
||||
// boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF;
|
||||
boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
|
||||
|
||||
cur_mem_paddr += PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
built = true;
|
||||
}
|
||||
}
|
||||
|
||||
#include "log.h"
|
||||
|
||||
static void load_boot_pgdir()
|
||||
{
|
||||
|
||||
TTBR0_W((uintptr_t)boot_l2pgdir);
|
||||
TTBR1_W(0);
|
||||
|
||||
#define TCR_TRUE_VALUE (0x0000000080813519ULL)
|
||||
uint64_t tcr = 0;
|
||||
TCR_R(tcr);
|
||||
tcr &= (uint64_t)~0xFF;
|
||||
tcr |= 0x19;
|
||||
TCR_W(tcr);
|
||||
|
||||
// Enable paging using read/modify/write
|
||||
// uint32_t val = 0;
|
||||
// SCTLR_R(val);
|
||||
// debug_printf_("Old SCTLR: %016lx\r\n", val);
|
||||
// val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
|
||||
// debug_printf_("New SCTLR: %08x\r\n", val);
|
||||
// val &= (uint32_t) ~(0x1 << 2);
|
||||
// debug_printf_("New SCTLR: %08x\r\n", val);
|
||||
// SCTLR_W(val);
|
||||
// debug_printf_("l2[0]: %p\r\n", boot_l2pgdir[0]);
|
||||
// debug_printf_("l2[1]: %p\r\n", boot_l2pgdir[1]);
|
||||
// debug_printf_("l2[2]: %p\r\n", boot_l2pgdir[2]);
|
||||
// debug_printf_("l2[3]: %p\r\n", boot_l2pgdir[3]);
|
||||
// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)boot_l2pgdir);
|
||||
// debug_printf_("pgdir[%d] = %p\r\n", 384, boot_l2pgdir[384]);
|
||||
// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)P2V(boot_l2pgdir));
|
||||
|
||||
// flush all TLB
|
||||
// debug_printf_("Flushing TLB.\r\n");
|
||||
DSB();
|
||||
CLEARTLB(0);
|
||||
ISB();
|
||||
}
|
||||
|
||||
static inline unsigned int current_el(void)
|
||||
{
|
||||
unsigned int el;
|
||||
asm volatile("mrs %0, CurrentEL" : "=r"(el) : : "cc");
|
||||
return el >> 2;
|
||||
}
|
||||
|
||||
extern void main(void);
|
||||
static bool _bss_inited = false;
|
||||
void bootmain()
|
||||
{
|
||||
build_boot_pgdir();
|
||||
load_boot_pgdir();
|
||||
__asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET));
|
||||
if (!_bss_inited) {
|
||||
memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
|
||||
_bss_inited = true;
|
||||
}
|
||||
main();
|
||||
}
|
||||
|
|
@ -61,35 +61,36 @@ void GetPdeAttr(uintptr_t* attr);
|
|||
/*
|
||||
Enable MMU, cache, write buffer, etc.
|
||||
*/
|
||||
#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val))
|
||||
#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val))
|
||||
#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory")
|
||||
#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory")
|
||||
|
||||
/*
|
||||
Read and write mmu pagetable register base addr
|
||||
*/
|
||||
#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val))
|
||||
#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val))
|
||||
#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory")
|
||||
#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory")
|
||||
|
||||
/*
|
||||
Read and write mmu pagetable register base addr
|
||||
*/
|
||||
#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val))
|
||||
#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val))
|
||||
#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory")
|
||||
#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory")
|
||||
|
||||
/*
|
||||
Translation Control Register（TCR）
|
||||
*/
|
||||
#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val))
|
||||
#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val))
|
||||
#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory")
|
||||
#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory")
|
||||
|
||||
#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val))
|
||||
#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val))
|
||||
#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory")
|
||||
#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory")
|
||||
|
||||
/*
|
||||
Flush TLB when loading a new page table.
|
||||
@note If nG is not set in the pte attribute, process switching need flush tlb.
|
||||
*/
|
||||
#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1")
|
||||
// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory")
|
||||
#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory")
|
||||
|
||||
/*
|
||||
When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register.
|
||||
|
|
@ -45,7 +45,9 @@ void load_pgdir(uintptr_t pgdir_paddr)
|
|||
struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
|
||||
|
||||
TTBR0_W((uint64_t)pgdir_paddr);
|
||||
DSB();
|
||||
CLEARTLB(0);
|
||||
ISB();
|
||||
p_icache_done->invalidateall();
|
||||
p_dcache_done->flushall();
|
||||
}
|
||||
|
|
@ -52,22 +52,26 @@ Modification:
|
|||
|
||||
void GetUsrPteAttr(uintptr_t* attr)
|
||||
{
|
||||
*attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
|
||||
// *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
|
||||
*attr = 0x713 | ARMV8_PTE_AP_U;
|
||||
}
|
||||
|
||||
void GetUsrDevPteAttr(uintptr_t* attr)
|
||||
{
|
||||
*attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
|
||||
// *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
|
||||
*attr = 0x403 | ARMV8_PTE_AP_U;
|
||||
}
|
||||
|
||||
void GetDevPteAttr(uintptr_t* attr)
|
||||
{
|
||||
*attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
|
||||
// *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
|
||||
*attr = 0x403ULL;
|
||||
}
|
||||
|
||||
void GetKernPteAttr(uintptr_t* attr)
|
||||
{
|
||||
*attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
|
||||
// *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
|
||||
*attr = 0x713ULL;
|
||||
}
|
||||
|
||||
void GetPdeAttr(uintptr_t* attr)
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
/**
|
||||
* @file bootmmu.c
|
||||
* @brief build pagetable and enable mmu in boot time
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2024.04.26
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: bootmmu.c
|
||||
Description: build pagetable and enable mmu in boot time
|
||||
Others:
|
||||
History:
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. first version
|
||||
*************************************************/
|
||||
#include "core.h"
|
||||
#include "memlayout.h"
|
||||
#include "mmio_access.h"
|
||||
#include "mmu.h"
|
||||
#include "pagetable.h"
|
||||
#include "registers.h"
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
extern uint64_t kernel_data_end[];
|
||||
extern uint64_t kernel_data_begin[];
|
||||
|
||||
// clang-format off
|
||||
#define L2_TYPE_TAB 2
|
||||
#define L2_PTE_VALID 1
|
||||
|
||||
#define L3_TYPE_TAB 2
|
||||
#define L3_PTE_VALID 1
|
||||
|
||||
#define L4_TYPE_PAGE (3 << 0)
|
||||
#define L4_PTE_DEV ((0b00) << 2) // Device memory
|
||||
#define L4_PTE_NORMAL ((0b01) << 2) // Device memory
|
||||
#define L4_PTE_AF (1 << 10) // Data Access Permissions
|
||||
|
||||
#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never
|
||||
#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
|
||||
#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never
|
||||
|
||||
#define IDX_MASK (0b111111111)
|
||||
#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
|
||||
// clang-format on
|
||||
|
||||
uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
|
||||
uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
uint64_t boot_virt_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
uint64_t boot_virt_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
|
||||
uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
|
||||
|
||||
static void build_boot_pgdir()
|
||||
{
|
||||
uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
|
||||
// dev mem
|
||||
boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
|
||||
uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, PAGE_SIZE);
|
||||
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
|
||||
boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
|
||||
|
||||
for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
|
||||
boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN;
|
||||
|
||||
cur_mem_paddr += PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
// identical mem
|
||||
boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
|
||||
|
||||
cur_mem_paddr = ALIGNDOWN((uint64_t)PHY_MEM_BASE, PAGE_SIZE);
|
||||
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
|
||||
boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
|
||||
|
||||
for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
|
||||
boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF;
|
||||
|
||||
cur_mem_paddr += PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void load_boot_pgdir()
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
TTBR0_W((uintptr_t)boot_l2pgdir);
|
||||
TTBR1_W(0);
|
||||
|
||||
TCR_W(TCR_VALUE);
|
||||
MAIR_W((MT_DEVICE_nGnRnE << (8 * AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC << (8 * AI_NORMAL_NC_IDX)));
|
||||
|
||||
// Enable paging using read/modify/write
|
||||
SCTLR_R(val);
|
||||
val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
|
||||
SCTLR_W(val);
|
||||
|
||||
// flush all TLB
|
||||
DSB();
|
||||
CLEARTLB(0);
|
||||
ISB();
|
||||
}
|
||||
|
||||
extern void main(void);
|
||||
static bool _bss_inited = false;
|
||||
void bootmain()
|
||||
{
|
||||
build_boot_pgdir();
|
||||
load_boot_pgdir();
|
||||
__asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_MEM_BASE - PHY_MEM_BASE));
|
||||
if (!_bss_inited) {
|
||||
memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
|
||||
_bss_inited = true;
|
||||
}
|
||||
main();
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
# The following three platforms support compatiable instructions.
|
||||
ifneq ($(findstring $(BOARD), ok1028a-c), )
|
||||
ifneq ($(findstring $(BOARD), 3568), )
|
||||
SRC_DIR := armv8-a
|
||||
endif
|
||||
ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# The following three platforms support compatiable instructions.
|
||||
SRC_DIR := cortex-a72
|
||||
SRC_DIR := cortex-a55
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_FILES := uart.c
|
||||
SRC_FILES := uart.c ns16550.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* NS16550 Serial Port
|
||||
* originally from linux source (arch/powerpc/boot/ns16550.h)
|
||||
*
|
||||
* Cleanup and unification
|
||||
* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
|
||||
*
|
||||
* modified slightly to
|
||||
* have addresses as offsets from CONFIG_SYS_ISA_BASE
|
||||
* added a few more definitions
|
||||
* added prototypes for ns16550.c
|
||||
* reduced no of com ports to 2
|
||||
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
|
||||
*
|
||||
* added support for port on 64-bit bus
|
||||
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note that the following macro magic uses the fact that the compiler
|
||||
* will not allocate storage for arrays of size 0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* For driver model we always use one byte per register, and sort out the
|
||||
* differences in the driver
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-1)
|
||||
|
||||
#define UART_REG(x) \
|
||||
unsigned char x; \
|
||||
unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
|
||||
|
||||
/**
|
||||
* struct ns16550_platdata - information about a NS16550 port
|
||||
*
|
||||
* @base: Base register address
|
||||
* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
|
||||
* @clock: UART base clock speed in Hz
|
||||
*/
|
||||
struct ns16550_platdata {
|
||||
unsigned long base;
|
||||
int reg_shift;
|
||||
int clock;
|
||||
int reg_offset;
|
||||
uint32_t fcr;
|
||||
};
|
||||
|
||||
struct udevice;
|
||||
|
||||
struct NS16550 {
|
||||
UART_REG(rbr); /* 0 */
|
||||
UART_REG(ier); /* 1 */
|
||||
UART_REG(fcr); /* 2 */
|
||||
UART_REG(lcr); /* 3 */
|
||||
UART_REG(mcr); /* 4 */
|
||||
UART_REG(lsr); /* 5 */
|
||||
UART_REG(msr); /* 6 */
|
||||
UART_REG(spr); /* 7 */
|
||||
#ifdef CONFIG_SOC_DA8XX
|
||||
UART_REG(reg8); /* 8 */
|
||||
UART_REG(reg9); /* 9 */
|
||||
UART_REG(revid1); /* A */
|
||||
UART_REG(revid2); /* B */
|
||||
UART_REG(pwr_mgmt); /* C */
|
||||
UART_REG(mdr1); /* D */
|
||||
#else
|
||||
UART_REG(mdr1); /* 8 */
|
||||
UART_REG(reg9); /* 9 */
|
||||
UART_REG(regA); /* A */
|
||||
UART_REG(regB); /* B */
|
||||
UART_REG(regC); /* C */
|
||||
UART_REG(regD); /* D */
|
||||
UART_REG(regE); /* E */
|
||||
UART_REG(uasr); /* F */
|
||||
UART_REG(scr); /* 10*/
|
||||
UART_REG(ssr); /* 11*/
|
||||
#endif
|
||||
#ifdef CONFIG_DM_SERIAL
|
||||
struct ns16550_platdata* plat;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define thr rbr
|
||||
#define iir fcr
|
||||
#define dll rbr
|
||||
#define dlm ier
|
||||
|
||||
typedef struct NS16550* NS16550_t;
|
||||
|
||||
/*
|
||||
* These are the definitions for the FIFO Control Register
|
||||
*/
|
||||
#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
|
||||
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
|
||||
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
|
||||
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
|
||||
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
|
||||
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
|
||||
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
|
||||
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
|
||||
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
|
||||
|
||||
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
|
||||
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
|
||||
|
||||
/* Ingenic JZ47xx specific UART-enable bit. */
|
||||
#define UART_FCR_UME 0x10
|
||||
|
||||
/* Clear & enable FIFOs */
|
||||
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
|
||||
|
||||
/*
|
||||
* These are the definitions for the Modem Control Register
|
||||
*/
|
||||
#define UART_MCR_DTR 0x01 /* DTR */
|
||||
#define UART_MCR_RTS 0x02 /* RTS */
|
||||
#define UART_MCR_OUT1 0x04 /* Out 1 */
|
||||
#define UART_MCR_OUT2 0x08 /* Out 2 */
|
||||
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
||||
#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
|
||||
|
||||
#define UART_MCR_DMA_EN 0x04
|
||||
#define UART_MCR_TX_DFR 0x08
|
||||
|
||||
/*
|
||||
* These are the definitions for the Line Control Register
|
||||
*
|
||||
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
|
||||
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
|
||||
*/
|
||||
#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
|
||||
#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
|
||||
#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
|
||||
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
|
||||
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
|
||||
#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
|
||||
#define UART_LCR_PEN 0x08 /* Parity eneble */
|
||||
#define UART_LCR_EPS 0x10 /* Even Parity Select */
|
||||
#define UART_LCR_STKP 0x20 /* Stick Parity */
|
||||
#define UART_LCR_SBRK 0x40 /* Set Break */
|
||||
#define UART_LCR_BKSE 0x80 /* Bank select enable */
|
||||
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Line Status Register
|
||||
*/
|
||||
#define UART_LSR_DR 0x01 /* Data ready */
|
||||
#define UART_LSR_OE 0x02 /* Overrun */
|
||||
#define UART_LSR_PE 0x04 /* Parity error */
|
||||
#define UART_LSR_FE 0x08 /* Framing error */
|
||||
#define UART_LSR_BI 0x10 /* Break */
|
||||
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
|
||||
#define UART_LSR_TEMT 0x40 /* Xmitter empty */
|
||||
#define UART_LSR_ERR 0x80 /* Error */
|
||||
|
||||
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
|
||||
#define UART_MSR_RI 0x40 /* Ring Indicator */
|
||||
#define UART_MSR_DSR 0x20 /* Data Set Ready */
|
||||
#define UART_MSR_CTS 0x10 /* Clear to Send */
|
||||
#define UART_MSR_DDCD 0x08 /* Delta DCD */
|
||||
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
|
||||
#define UART_MSR_DDSR 0x02 /* Delta DSR */
|
||||
#define UART_MSR_DCTS 0x01 /* Delta CTS */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Interrupt Identification Register
|
||||
*/
|
||||
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
|
||||
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
|
||||
|
||||
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
|
||||
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
|
||||
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
|
||||
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Interrupt Enable Register
|
||||
*/
|
||||
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
|
||||
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
|
||||
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
|
||||
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
|
||||
|
||||
/* useful defaults for LCR */
|
||||
#define UART_LCR_8N1 0x03
|
||||
|
||||
void NS16550_init(NS16550_t com_port, int baud_divisor);
|
||||
void NS16550_putc(NS16550_t com_port, char c);
|
||||
char NS16550_getc(NS16550_t com_port);
|
||||
int NS16550_tstc(NS16550_t com_port);
|
||||
void NS16550_reinit(NS16550_t com_port, int baud_divisor);
|
||||
|
||||
void _debug_uart_init(void);
|
||||
void _debug_uart_putc(int ch);
|
||||
int _debug_uart_getc(void);
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* COM1 NS16550 support
|
||||
* originally from linux source (arch/powerpc/boot/ns16550.c)
|
||||
* modified to use CONFIG_SYS_ISA_MEM and new defines
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "mmio_access.h"
|
||||
#include "ns16550.h"
|
||||
|
||||
#define UART_ADDR MMIO_P2V_WO(0xFE660000)
|
||||
// #define UART_ADDR (0xFE660000)
|
||||
|
||||
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
|
||||
#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
|
||||
|
||||
#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v))
|
||||
#define in_le32(a) (*(volatile uint32_t*)(a))
|
||||
|
||||
#ifndef CONFIG_SYS_NS16550_IER
|
||||
#define CONFIG_SYS_NS16550_IER 0x00
|
||||
#endif /* CONFIG_SYS_NS16550_IER */
|
||||
|
||||
#define serial_dout(reg, value) \
|
||||
serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
|
||||
2, value)
|
||||
#define serial_din(reg) \
|
||||
serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
|
||||
2)
|
||||
|
||||
static inline void serial_out_shift(void* addr, int shift, int value)
|
||||
{
|
||||
out_le32(addr, value);
|
||||
}
|
||||
|
||||
static inline int serial_in_shift(void* addr, int shift)
|
||||
{
|
||||
return in_le32(addr);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_NS16550_CLK
|
||||
#define CONFIG_SYS_NS16550_CLK 0
|
||||
#endif
|
||||
|
||||
#define DIV_ROUND_CLOSEST(x, divisor) ( \
|
||||
{ \
|
||||
typeof(x) __x = x; \
|
||||
typeof(divisor) __d = divisor; \
|
||||
(((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \
|
||||
})
|
||||
|
||||
int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
|
||||
{
|
||||
const unsigned int mode_x_div = 16;
|
||||
|
||||
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
|
||||
}
|
||||
|
||||
void _debug_uart_init(void)
|
||||
{
|
||||
struct NS16550* com_port = (struct NS16550*)UART_ADDR;
|
||||
|
||||
/*
|
||||
* We copy the code from above because it is already horribly messy.
|
||||
* Trying to refactor to nicely remove the duplication doesn't seem
|
||||
* feasible. The better fix is to move all users of this driver to
|
||||
* driver model.
|
||||
*/
|
||||
int baud_divisor = ns16550_calc_divisor(com_port, 24000000,
|
||||
1500000);
|
||||
serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
|
||||
serial_dout(&com_port->mcr, UART_MCRVAL);
|
||||
serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
|
||||
|
||||
serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
|
||||
serial_dout(&com_port->dll, baud_divisor & 0xff);
|
||||
serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
|
||||
serial_dout(&com_port->lcr, UART_LCRVAL);
|
||||
}
|
||||
|
||||
void _debug_uart_putc(int ch)
|
||||
{
|
||||
static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
|
||||
|
||||
if (ch == '\n') {
|
||||
_debug_uart_putc('\r');
|
||||
}
|
||||
|
||||
while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
|
||||
;
|
||||
serial_dout(&com_port->thr, ch);
|
||||
}
|
||||
|
||||
int _debug_uart_getc(void)
|
||||
{
|
||||
static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
|
||||
|
||||
while (!(serial_din(&com_port->lsr) & UART_LSR_DR))
|
||||
;
|
||||
|
||||
return serial_din(&com_port->rbr);
|
||||
}
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
//
|
||||
// low-level driver routines for pl011 UART.
|
||||
//
|
||||
|
||||
#include "uart.h"
|
||||
#include "actracer.h"
|
||||
#include "ns16550.h"
|
||||
#include "uart_common_ope.h"
|
||||
|
||||
// the UART control registers are memory-mapped
|
||||
// at address UART0. this macro returns the
|
||||
// address of one of the registers.
|
||||
|
||||
// the transmit output buffer.
|
||||
#define UART_TX_BUF_SIZE 32
|
||||
// static char uart_tx_buf[UART_TX_BUF_SIZE];
|
||||
uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
|
||||
uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
|
||||
|
||||
void uartinit(void)
|
||||
{
|
||||
// // disable uart
|
||||
// UART_WRITE_REG(CR, 0);
|
||||
|
||||
// // disable interrupts.
|
||||
// UART_WRITE_REG(IMSC, 0);
|
||||
|
||||
// // in qemu, it is not necessary to set baudrate.
|
||||
// // enable FIFOs.
|
||||
// // set word length to 8 bits, no parity.
|
||||
// UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
|
||||
|
||||
// // enable RXE, TXE and enable uart.
|
||||
// UART_WRITE_REG(CR, 0x301);
|
||||
|
||||
// // enable transmit and receive interrupts.
|
||||
// UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
|
||||
|
||||
_debug_uart_init();
|
||||
}
|
||||
|
||||
// if the UART is idle, and a character is waiting
|
||||
// in the transmit buffer, send it.
|
||||
// caller must hold uart_tx_lock.
|
||||
// called from both the top- and bottom-half.
|
||||
void uartstart()
|
||||
{
|
||||
// while (1) {
|
||||
// if (uart_tx_w == uart_tx_r) {
|
||||
// // transmit buffer is empty.
|
||||
// return;
|
||||
// }
|
||||
|
||||
// if (UART_READ_REG(FR) & FR_TXFF) {
|
||||
// // the UART transmit holding register is full,
|
||||
// // so we cannot give it another byte.
|
||||
// // it will interrupt when it's ready for a new byte.
|
||||
// return;
|
||||
// }
|
||||
|
||||
// int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
|
||||
// uart_tx_r += 1;
|
||||
|
||||
// // maybe uartputc() is waiting for space in the buffer.
|
||||
|
||||
// UART_WRITE_REG(DR, c);
|
||||
// }
|
||||
}
|
||||
|
||||
void uartputc(uint8_t c)
|
||||
{
|
||||
// while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
|
||||
// ;
|
||||
// uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
|
||||
// uart_tx_w += 1;
|
||||
// uartstart();
|
||||
// return;
|
||||
_debug_uart_putc((int)c);
|
||||
}
|
||||
|
||||
// read one input character from the UART.
|
||||
// return -1 if none is waiting.
|
||||
static uint8_t uartgetc(void)
|
||||
{
|
||||
// if (UART_READ_REG(FR) & FR_RXFE)
|
||||
// return 0xFF;
|
||||
// else
|
||||
// return UART_READ_REG(DR);
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
static uint32_t UartGetIrqnum()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct XiziSerialDriver hardkernel_serial_driver = {
|
||||
.sys_serial_init = uartinit,
|
||||
.get_serial_irqnum = UartGetIrqnum,
|
||||
.putc = uartputc,
|
||||
.getc = uartgetc,
|
||||
};
|
||||
|
||||
struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
|
||||
{
|
||||
hardkernel_serial_driver.sys_serial_init();
|
||||
return &hardkernel_serial_driver;
|
||||
}
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
//
|
||||
// low-level driver routines for pl011 UART.
|
||||
//
|
||||
|
||||
#include "uart.h"
|
||||
#include "actracer.h"
|
||||
#include "uart_common_ope.h"
|
||||
|
||||
// the UART control registers are memory-mapped
|
||||
// at address UART0. this macro returns the
|
||||
// address of one of the registers.
|
||||
|
||||
// the transmit output buffer.
|
||||
#define UART_TX_BUF_SIZE 32
|
||||
static char uart_tx_buf[UART_TX_BUF_SIZE];
|
||||
uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
|
||||
uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
|
||||
|
||||
void uartinit(void)
|
||||
{
|
||||
// disable uart
|
||||
UART_WRITE_REG(CR, 0);
|
||||
|
||||
// disable interrupts.
|
||||
UART_WRITE_REG(IMSC, 0);
|
||||
|
||||
// in qemu, it is not necessary to set baudrate.
|
||||
// enable FIFOs.
|
||||
// set word length to 8 bits, no parity.
|
||||
UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
|
||||
|
||||
// enable RXE, TXE and enable uart.
|
||||
UART_WRITE_REG(CR, 0x301);
|
||||
|
||||
// enable transmit and receive interrupts.
|
||||
UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
|
||||
}
|
||||
|
||||
// if the UART is idle, and a character is waiting
|
||||
// in the transmit buffer, send it.
|
||||
// caller must hold uart_tx_lock.
|
||||
// called from both the top- and bottom-half.
|
||||
void uartstart()
|
||||
{
|
||||
while (1) {
|
||||
if (uart_tx_w == uart_tx_r) {
|
||||
// transmit buffer is empty.
|
||||
return;
|
||||
}
|
||||
|
||||
if (UART_READ_REG(FR) & FR_TXFF) {
|
||||
// the UART transmit holding register is full,
|
||||
// so we cannot give it another byte.
|
||||
// it will interrupt when it's ready for a new byte.
|
||||
return;
|
||||
}
|
||||
|
||||
int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
|
||||
uart_tx_r += 1;
|
||||
|
||||
// maybe uartputc() is waiting for space in the buffer.
|
||||
|
||||
UART_WRITE_REG(DR, c);
|
||||
}
|
||||
}
|
||||
|
||||
// add a character to the output buffer and tell the
|
||||
// UART to start sending if it isn't already.
|
||||
// blocks if the output buffer is full.
|
||||
// because it may block, it can't be called
|
||||
// from interrupts; it's only suitable for use
|
||||
// by write().
|
||||
void uartputc(uint8_t c)
|
||||
{
|
||||
while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
|
||||
;
|
||||
uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
|
||||
uart_tx_w += 1;
|
||||
uartstart();
|
||||
return;
|
||||
}
|
||||
|
||||
// read one input character from the UART.
|
||||
// return -1 if none is waiting.
|
||||
static uint8_t uartgetc(void)
|
||||
{
|
||||
if (UART_READ_REG(FR) & FR_RXFE)
|
||||
return 0xFF;
|
||||
else
|
||||
return UART_READ_REG(DR);
|
||||
}
|
||||
|
||||
// handle a uart interrupt, raised because input has
|
||||
// arrived, or the uart is ready for more output, or
|
||||
// both. called from trap.c.
|
||||
void uartintr(void)
|
||||
{
|
||||
// read and process incoming characters.
|
||||
while (1) {
|
||||
int c = uartgetc();
|
||||
if (c == 0xFF)
|
||||
break;
|
||||
}
|
||||
|
||||
// send buffered characters.
|
||||
uartstart();
|
||||
|
||||
// clear transmit and receive interrupts.
|
||||
UART_WRITE_REG(ICR, INT_RX_ENABLE | INT_TX_ENABLE);
|
||||
}
|
||||
|
||||
static uint32_t UartGetIrqnum()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct XiziSerialDriver hardkernel_serial_driver = {
|
||||
.sys_serial_init = uartinit,
|
||||
.get_serial_irqnum = UartGetIrqnum,
|
||||
.putc = uartputc,
|
||||
.getc = uartgetc,
|
||||
};
|
||||
|
||||
struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
|
||||
{
|
||||
hardkernel_serial_driver.sys_serial_init();
|
||||
return &hardkernel_serial_driver;
|
||||
}
|
||||
|
|
@ -38,20 +38,20 @@ KERNELPATHS += \
|
|||
-I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/
|
||||
endif
|
||||
|
||||
ifeq ($(BOARD), ok1028a-c)
|
||||
ifeq ($(BOARD), 3568)
|
||||
KERNELPATHS += \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a72/$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a72/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3 \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a72/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a72/
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a55/$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a55/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a55/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a55/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3 \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a55/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a55/
|
||||
endif
|
||||
|
||||
KERNELPATHS += \
|
||||
|
|
|
|||
|
|
@ -10,10 +10,10 @@ cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -
|
|||
board_specs = stub.o
|
||||
#cflags = -Wall -g -std=c11
|
||||
endif
|
||||
ifeq ($(BOARD), ok1028a-c)
|
||||
ifeq ($(BOARD), 3568)
|
||||
toolchain ?= aarch64-none-elf-
|
||||
user_ldflags = -N -Ttext 0
|
||||
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
board_specs = stub.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
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File diff suppressed because it is too large
Load Diff
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File diff suppressed because it is too large
Load Diff
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File diff suppressed because it is too large
Load Diff
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File diff suppressed because it is too large
Load Diff
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File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -20,8 +20,9 @@ int main(int argc, char* argv[])
|
|||
{
|
||||
struct Session session;
|
||||
printf("init: connecting MemFS\n");
|
||||
while (connect_session(&session, "MemFS", 8092) < 0)
|
||||
;
|
||||
while (connect_session(&session, "MemFS", 8092) < 0) {
|
||||
yield(SYS_TASK_YIELD_NO_REASON);
|
||||
}
|
||||
printf("init: connect MemFS success\n");
|
||||
|
||||
int fd;
|
||||
|
|
|
|||
|
|
@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi-
|
|||
user_ldflags = -N -Ttext 0
|
||||
cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
endif
|
||||
ifeq ($(BOARD), ok1028a-c)
|
||||
ifeq ($(BOARD), 3568)
|
||||
toolchain ?= aarch64-none-elf-
|
||||
user_ldflags = -N -Ttext 0
|
||||
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
endif
|
||||
|
||||
cc = ${toolchain}gcc
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/// this file is only used for debug
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "libserial.h"
|
||||
#include "usyscall.h"
|
||||
|
||||
/*
|
||||
* For driver model we always use one byte per register, and sort out the
|
||||
* differences in the driver
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-1)
|
||||
|
||||
#define UART_REG(x) \
|
||||
unsigned char x; \
|
||||
unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
|
||||
|
||||
/**
|
||||
* struct ns16550_platdata - information about a NS16550 port
|
||||
*
|
||||
* @base: Base register address
|
||||
* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
|
||||
* @clock: UART base clock speed in Hz
|
||||
*/
|
||||
struct ns16550_platdata {
|
||||
unsigned long base;
|
||||
int reg_shift;
|
||||
int clock;
|
||||
int reg_offset;
|
||||
uint32_t fcr;
|
||||
};
|
||||
|
||||
struct udevice;
|
||||
|
||||
struct NS16550 {
|
||||
UART_REG(rbr); /* 0 */
|
||||
UART_REG(ier); /* 1 */
|
||||
UART_REG(fcr); /* 2 */
|
||||
UART_REG(lcr); /* 3 */
|
||||
UART_REG(mcr); /* 4 */
|
||||
UART_REG(lsr); /* 5 */
|
||||
UART_REG(msr); /* 6 */
|
||||
UART_REG(spr); /* 7 */
|
||||
#ifdef CONFIG_SOC_DA8XX
|
||||
UART_REG(reg8); /* 8 */
|
||||
UART_REG(reg9); /* 9 */
|
||||
UART_REG(revid1); /* A */
|
||||
UART_REG(revid2); /* B */
|
||||
UART_REG(pwr_mgmt); /* C */
|
||||
UART_REG(mdr1); /* D */
|
||||
#else
|
||||
UART_REG(mdr1); /* 8 */
|
||||
UART_REG(reg9); /* 9 */
|
||||
UART_REG(regA); /* A */
|
||||
UART_REG(regB); /* B */
|
||||
UART_REG(regC); /* C */
|
||||
UART_REG(regD); /* D */
|
||||
UART_REG(regE); /* E */
|
||||
UART_REG(uasr); /* F */
|
||||
UART_REG(scr); /* 10*/
|
||||
UART_REG(ssr); /* 11*/
|
||||
#endif
|
||||
#ifdef CONFIG_DM_SERIAL
|
||||
struct ns16550_platdata* plat;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define thr rbr
|
||||
#define iir fcr
|
||||
#define dll rbr
|
||||
#define dlm ier
|
||||
|
||||
typedef struct NS16550* NS16550_t;
|
||||
|
||||
/*
|
||||
* These are the definitions for the FIFO Control Register
|
||||
*/
|
||||
#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
|
||||
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
|
||||
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
|
||||
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
|
||||
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
|
||||
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
|
||||
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
|
||||
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
|
||||
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
|
||||
|
||||
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
|
||||
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
|
||||
|
||||
/* Ingenic JZ47xx specific UART-enable bit. */
|
||||
#define UART_FCR_UME 0x10
|
||||
|
||||
/* Clear & enable FIFOs */
|
||||
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
|
||||
|
||||
/*
|
||||
* These are the definitions for the Modem Control Register
|
||||
*/
|
||||
#define UART_MCR_DTR 0x01 /* DTR */
|
||||
#define UART_MCR_RTS 0x02 /* RTS */
|
||||
#define UART_MCR_OUT1 0x04 /* Out 1 */
|
||||
#define UART_MCR_OUT2 0x08 /* Out 2 */
|
||||
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
||||
#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
|
||||
|
||||
#define UART_MCR_DMA_EN 0x04
|
||||
#define UART_MCR_TX_DFR 0x08
|
||||
|
||||
/*
|
||||
* These are the definitions for the Line Control Register
|
||||
*
|
||||
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
|
||||
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
|
||||
*/
|
||||
#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
|
||||
#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
|
||||
#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
|
||||
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
|
||||
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
|
||||
#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
|
||||
#define UART_LCR_PEN 0x08 /* Parity eneble */
|
||||
#define UART_LCR_EPS 0x10 /* Even Parity Select */
|
||||
#define UART_LCR_STKP 0x20 /* Stick Parity */
|
||||
#define UART_LCR_SBRK 0x40 /* Set Break */
|
||||
#define UART_LCR_BKSE 0x80 /* Bank select enable */
|
||||
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Line Status Register
|
||||
*/
|
||||
#define UART_LSR_DR 0x01 /* Data ready */
|
||||
#define UART_LSR_OE 0x02 /* Overrun */
|
||||
#define UART_LSR_PE 0x04 /* Parity error */
|
||||
#define UART_LSR_FE 0x08 /* Framing error */
|
||||
#define UART_LSR_BI 0x10 /* Break */
|
||||
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
|
||||
#define UART_LSR_TEMT 0x40 /* Xmitter empty */
|
||||
#define UART_LSR_ERR 0x80 /* Error */
|
||||
|
||||
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
|
||||
#define UART_MSR_RI 0x40 /* Ring Indicator */
|
||||
#define UART_MSR_DSR 0x20 /* Data Set Ready */
|
||||
#define UART_MSR_CTS 0x10 /* Clear to Send */
|
||||
#define UART_MSR_DDCD 0x08 /* Delta DCD */
|
||||
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
|
||||
#define UART_MSR_DDSR 0x02 /* Delta DSR */
|
||||
#define UART_MSR_DCTS 0x01 /* Delta CTS */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Interrupt Identification Register
|
||||
*/
|
||||
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
|
||||
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
|
||||
|
||||
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
|
||||
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
|
||||
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
|
||||
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Interrupt Enable Register
|
||||
*/
|
||||
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
|
||||
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
|
||||
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
|
||||
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
|
||||
|
||||
/* useful defaults for LCR */
|
||||
#define UART_LCR_8N1 0x03
|
||||
|
||||
#define UART_ADDR (0xFE660000)
|
||||
|
||||
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
|
||||
#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
|
||||
|
||||
#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v))
|
||||
#define in_le32(a) (*(volatile uint32_t*)(a))
|
||||
|
||||
#ifndef CONFIG_SYS_NS16550_IER
|
||||
#define CONFIG_SYS_NS16550_IER 0x00
|
||||
#endif /* CONFIG_SYS_NS16550_IER */
|
||||
|
||||
#define serial_dout(reg, value) \
|
||||
serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
|
||||
2, value)
|
||||
#define serial_din(reg) \
|
||||
serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
|
||||
2)
|
||||
|
||||
static inline void serial_out_shift(void* addr, int shift, int value)
|
||||
{
|
||||
out_le32(addr, value);
|
||||
}
|
||||
|
||||
static inline int serial_in_shift(void* addr, int shift)
|
||||
{
|
||||
return in_le32(addr);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_NS16550_CLK
|
||||
#define CONFIG_SYS_NS16550_CLK 0
|
||||
#endif
|
||||
|
||||
bool init_uart_mmio()
|
||||
{
|
||||
static int mapped = 0;
|
||||
if (mapped == 0) {
|
||||
if (-1 == mmap(UART_ADDR, UART_ADDR, 4096, true)) {
|
||||
return false;
|
||||
}
|
||||
mapped = 1;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void putc(char ch)
|
||||
{
|
||||
static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
|
||||
|
||||
if (ch == '\n') {
|
||||
putc('\r');
|
||||
}
|
||||
|
||||
while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
|
||||
;
|
||||
serial_dout(&com_port->thr, ch);
|
||||
}
|
||||
|
||||
char getc(void)
|
||||
{
|
||||
static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
|
||||
|
||||
while (!(serial_din(&com_port->lsr) & UART_LSR_DR))
|
||||
;
|
||||
|
||||
return serial_din(&com_port->rbr);
|
||||
}
|
||||
|
|
@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi-
|
|||
user_ldflags = -N -Ttext 0
|
||||
cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
endif
|
||||
ifeq ($(BOARD), ok1028a-c)
|
||||
ifeq ($(BOARD), 3568)
|
||||
toolchain ?= aarch64-none-elf-
|
||||
user_ldflags = -N -Ttext 0
|
||||
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
endif
|
||||
|
||||
cc = ${toolchain}gcc
|
||||
|
|
|
|||
|
|
@ -1,113 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/// this file is only used for debug
|
||||
#include "libserial.h"
|
||||
#include "usyscall.h"
|
||||
|
||||
#define USER_UART_BASE 0x6FFFF000
|
||||
|
||||
#define UART0_BASE (0x09000000ULL)
|
||||
#define UART0_REG(reg) ((volatile uint32_t*)(USER_UART_BASE + reg))
|
||||
|
||||
// the UART control registers.
|
||||
// pl011
|
||||
#define DR 0x00
|
||||
#define FR 0x18
|
||||
#define FR_RXFE (1 << 4) // recieve fifo empty
|
||||
#define FR_TXFF (1 << 5) // transmit fifo full
|
||||
#define FR_RXFF (1 << 6) // recieve fifo full
|
||||
#define FR_TXFE (1 << 7) // transmit fifo empty
|
||||
#define IBRD 0x24
|
||||
#define FBRD 0x28
|
||||
#define LCRH 0x2c
|
||||
#define LCRH_FEN (1 << 4)
|
||||
#define LCRH_WLEN_8BIT (3 << 5)
|
||||
#define CR 0x30
|
||||
#define IMSC 0x38
|
||||
#define INT_RX_ENABLE (1 << 4)
|
||||
#define INT_TX_ENABLE (1 << 5)
|
||||
#define ICR 0x44
|
||||
|
||||
#define UART_READ_REG(reg) (*(UART0_REG(reg)))
|
||||
#define UART_WRITE_REG(reg, v) (*(UART0_REG(reg)) = (v))
|
||||
|
||||
#define UART_TX_BUF_SIZE 32
|
||||
static char uart_tx_buf[UART_TX_BUF_SIZE];
|
||||
uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
|
||||
uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
|
||||
|
||||
bool init_uart_mmio()
|
||||
{
|
||||
static int mapped = 0;
|
||||
if (mapped == 0) {
|
||||
if (-1 == mmap(USER_UART_BASE, UART0_BASE, 4096, true)) {
|
||||
return false;
|
||||
}
|
||||
mapped = 1;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
// if the UART is idle, and a character is waiting
|
||||
// in the transmit buffer, send it.
|
||||
// caller must hold uart_tx_lock.
|
||||
// called from both the top- and bottom-half.
|
||||
void uartstart()
|
||||
{
|
||||
while (1) {
|
||||
if (uart_tx_w == uart_tx_r) {
|
||||
// transmit buffer is empty.
|
||||
return;
|
||||
}
|
||||
|
||||
if (UART_READ_REG(FR) & FR_TXFF) {
|
||||
// the UART transmit holding register is full,
|
||||
// so we cannot give it another byte.
|
||||
// it will interrupt when it's ready for a new byte.
|
||||
return;
|
||||
}
|
||||
|
||||
int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
|
||||
uart_tx_r += 1;
|
||||
|
||||
// maybe uartputc() is waiting for space in the buffer.
|
||||
|
||||
UART_WRITE_REG(DR, c);
|
||||
}
|
||||
}
|
||||
|
||||
// add a character to the output buffer and tell the
|
||||
// UART to start sending if it isn't already.
|
||||
// blocks if the output buffer is full.
|
||||
// because it may block, it can't be called
|
||||
// from interrupts; it's only suitable for use
|
||||
// by write().
|
||||
void putc(char c)
|
||||
{
|
||||
while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
|
||||
;
|
||||
uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
|
||||
uart_tx_w += 1;
|
||||
uartstart();
|
||||
return;
|
||||
}
|
||||
|
||||
// read one input character from the UART.
|
||||
// return -1 if none is waiting.
|
||||
char getc(void)
|
||||
{
|
||||
if (UART_READ_REG(FR) & FR_RXFE)
|
||||
return 0xFF;
|
||||
else
|
||||
return UART_READ_REG(DR);
|
||||
}
|
||||
|
|
@ -9,10 +9,10 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group
|
|||
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
#cflags = -Wall -g -std=c11
|
||||
endif
|
||||
ifeq ($(BOARD), ok1028a-c)
|
||||
ifeq ($(BOARD), 3568)
|
||||
toolchain ?= aarch64-none-elf-
|
||||
user_ldflags = -N -Ttext 0
|
||||
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
endif
|
||||
|
||||
cc = ${toolchain}gcc
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue