Function usb_mmap instead of naive_mmap

This reverts commit 99967e9f9b.

Ubiquitous/XiZi_AIoT/Makefile

@@ -4,7 +4,7 @@ MAKEFLAGS += --no-print-directory
 .PHONY:COMPILE_APP COMPILE_KERNEL
 
 riscv_support := 
-arm_support += imx6q-sabrelite zynq7000-zc702 ok1028a-c
+arm_support += imx6q-sabrelite zynq7000-zc702 3568
 emulator_support += 
 support := $(riscv_support) $(arm_support) $(emulator_support) 
 SRC_DIR :=
@@ -34,8 +34,8 @@ export UBIQUITOUS_ROOT ?= ..
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
 include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/config.mk
 endif
-ifneq ($(findstring $(BOARD), ok1028a-c), )
-include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/config.mk
+ifneq ($(findstring $(BOARD), 3568), )
+include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/config.mk
 endif
 export BSP_BUILD_DIR := $(KERNEL_ROOT)
 export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools
@@ -133,6 +133,8 @@ clean:
 	@rm -rf services/tools/mkfs/mkfs
 	@rm -rf services/app/fs.img
 	@rm -rf services/app/user.map
+	@rm -rf services/net/net_server/user.map
+	@rm -rf services/net/net_server/bin
 
 distclean:
 	@echo Clean all configuration

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile

@@ -1,5 +1,5 @@
 # The following three platforms support compatiable instructions.
-ifneq ($(findstring $(BOARD), ok1028a-c), )
+ifneq ($(findstring $(BOARD), 3568), )
 SRC_DIR := armv8-a
 endif
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h

@@ -74,7 +74,7 @@ Modification:
 
 #include "cortex_a9.h"
 
-#define NR_CPU 4
+#define NR_CPU 1
 
 __attribute__((always_inline, optimize("O0"))) static inline uint32_t user_mode()
 {

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile

@@ -1,6 +1,6 @@
 # The following three platforms support compatiable instructions.
-ifneq ($(findstring $(BOARD), ok1028a-c), )
-SRC_DIR := cortex-a72
+ifneq ($(findstring $(BOARD), 3568), )
+SRC_DIR := cortex-a55
 endif
 
 

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.c

@@ -29,7 +29,7 @@ Modification:
 1. first version
 *************************************************/
 
-/*********cortex-a72 general register************
+/*********cortex-a55 general register************
    EL0            |         EL1        |       EL2      |       EL3
 
      x0;
@@ -63,7 +63,7 @@ Modification:
      x28;
      x29;
      x30;
-*********cortex-a72  special register************
+*********cortex-a55  special register************
                                                 XZR
                                                 PC
      SP_EL0             SP_EL1            SP_EL2           SP_EL3

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h

@@ -12,7 +12,7 @@
 
 /**
  * @file core.h
- * @brief cortex-a72 core function
+ * @brief cortex-a55 core function
  * @version 1.0
  * @author AIIT XUOS Lab
  * @date 2024.04.11
@@ -20,7 +20,7 @@
 
 /*************************************************
 File name: core.h
-Description: cortex-a72 core function
+Description: cortex-a55 core function
 Others:
 History:
 Author: AIIT XUOS Lab
@@ -71,7 +71,7 @@ Modification:
 #include <stdint.h>
 #include <string.h>
 
-#include "cortex_a72.h"
+#include "cortex_a55.h"
 
 #define NR_CPU 4 // maximum number of CPUs
 
@@ -79,15 +79,6 @@ __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode
 {
     uint64_t val = 0;
 
-    __asm__ __volatile__(
-        "mrs %0, spsr_el1"
-        : "=r"(val)
-        :
-        :);
-    val &= ~DIS_INT;
-    val &= ~SPSR_MODE_MASK;
-    val |= ARM_MODE_EL0_t;
-
     return val;
 }
 

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds

@@ -45,30 +45,36 @@ ENTRY( _ENTRY )
 ENTRY( _boot_start )
 
 MEMORY {
-  phy_ddr3 (rwx)      : ORIGIN = 0x0000000040000000, LENGTH = 1024M
-  vir_ddr3 (rwx)      : ORIGIN = 0x0000006040635000, LENGTH = 1024M
+  phy_ddr3 (rwx)      : ORIGIN = 0x0000000010000000, LENGTH = 1024M
+  vir_ddr3 (rwx)      : ORIGIN = 0x000000601040E000, LENGTH = 1024M
 }
 
 
 SECTIONS
 {
   .start_sec : {
-		. = ALIGN(0x1000);
+		. = ORIGIN(phy_ddr3);
 		/* initialization start checkpoint. */
 
-  boot.o(.text)
-  bootmmu.o(.text .text.*)
+    _start_image_addr = .;
 
-  boot.o(.rodata .rodata.*)
-  bootmmu.o(.rodata .rodata.*)
+    boot.o(.text)
+    bootmmu.o(.text .text.*)
+    /* ns16550.o(.text .text.*) */
 
-  boot.o(.data .data.*)
-  bootmmu.o(.data .data.*)
+    boot.o(.rodata .rodata.*)
+    bootmmu.o(.rodata .rodata.*)
+    /* ns16550.o(.rodata .rodata.*) */
 
-	PROVIDE(boot_start_addr = .);
+    boot.o(.data .data.*)
+    bootmmu.o(.data .data.*)
+    /* ns16550.o(.data .data.*) */
 
-  boot.o(.bss .bss.* COMMON)
-  bootmmu.o(.bss .bss.* COMMON)
+	  PROVIDE(boot_start_addr = .);
+
+    boot.o(.bss .bss.* COMMON)
+    bootmmu.o(.bss .bss.* COMMON)
+    /* ns16550.o(.bss .bss.* COMMON) */
   
 		/* stack for booting code. */
 		. = ALIGN(0x1000);
@@ -81,7 +87,7 @@ SECTIONS
 		PROVIDE(boot_end_addr = .);
 	} > phy_ddr3
 
-  .text : AT(0x40635000) {
+  .text : AT(0x1040E000) {
     . = ALIGN(0x1000);
     *(.text .text.* .gnu.linkonce.t.*)
   } > vir_ddr3
@@ -103,17 +109,19 @@ SECTIONS
 		PROVIDE(_binary_default_fs_start = .);
 		*(.rawdata_memfs*)
 		PROVIDE(_binary_default_fs_end = .);
+    PROVIDE(__init_array_start = .);
+    PROVIDE(__init_array_end = .);
   } > vir_ddr3
 
   . = ALIGN(0x1000);
-  PROVIDE(kernel_data_begin = .);
+  _image_size = . - 0x0000006010000000;
 
-  _image_size = . - 0x0000006040000000;
   .bss : {
+    PROVIDE(kernel_data_begin = .);
     PROVIDE(__bss_start__ = .);
 		*(.bss .bss.* COMMON)
+    . = ALIGN(0x1000);
 		PROVIDE(__bss_end__ = .);
+	  PROVIDE(kernel_data_end = .);
   } > vir_ddr3
-  . = ALIGN(0x1000);
-	PROVIDE(kernel_data_end = .);
 }

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/Makefile

@@ -1,5 +1,6 @@
 SRC_FILES := boot.S \
+			 xizi_smp.S \
 			 smp.c \
-			 cortexA72.S
+			 cortexA55.S
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S

@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *    http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#include "core.h"
+
+#define HCR_VALUE (1 << 31)
+#define SPSR_EL2_VALUE (7 << 6) | (5 << 0)
+#define SCTLR_EL1_VALUE (0x30D00800)
+
+/* Macros for MAIR setting. */
+#define MAIR(attr, mt)	((attr) << ((mt) * 8))
+#define MT_DEVICE_nGnRnE	0
+#define MT_DEVICE_nGnRE		1
+#define MT_DEVICE_GRE		2
+#define MT_NORMAL_NC		3
+#define MT_NORMAL	    	4
+#define MT_NORMAL_WT		5
+
+.section ".text", "ax"
+.global _boot_start
+.global primary_cpu_init
+.global el2_setup
+/* The function for setting memory types and MAIR registers. */
+.global __cpu_mair_setup
+
+_boot_start:
+    bl el2_setup
+
+    /* set NSACR, both Secure and Non-secure access are allowed to NEON */
+    mov     x0,         #(3 << 20)
+    msr     cpacr_el1,  x0
+    isb
+
+    // clear some registers
+    msr     elr_el1,    XZR
+
+    ldr     x0, =stacks_top
+    mov     x1, #MODE_STACK_SIZE
+
+    // get cpu id, and subtract the offset from the stacks base address
+    mrs     x2, mpidr_el1
+    and     x2, x2, #0xFFF
+    lsr     x2, x2, #8
+    mov     x5, x2
+    mul     x3, x2, x1
+    sub     x0, x0, x3
+    mov     sp, x0
+
+    mov     x2,         #ARM_MODE_EL1_h | DIS_INT  
+    msr     spsr_el1,   x2
+
+    // check cpu id - cpu0 is primary cpu
+    mrs     x2, mpidr_el1
+    and     x2, x2, #0xFFF
+    lsr     x2, x2, #8
+    mov     x5, x2
+    cmp     x5, #0
+    beq     primary_cpu_init
+    bl      __cpu_mair_setup
+    bl      bootmain     // for secondary cpus, jump to argument function pointer passed in by ROM
+
+    bl      .
+
+primary_cpu_init:
+   	/* init .bss */
+     /* clear the .bss section (zero init) */
+    ldr x1,	=boot_start_addr
+    ldr x2,	=boot_end_addr
+    mov x3,	#0
+1:  
+    cmp x1,	x2
+    stp x3, x3, [x1], #16
+    b.lt    1b  
+
+    bl __cpu_mair_setup
+	bl bootmain
+
+    .func el2_setup
+el2_setup:
+    mrs x0, CurrentEL
+    lsr x0, x0, #2
+    and x0, x0, #3
+    cmp x0, #2
+    beq 1f
+    ret
+
+    /* Hyp configuration. */
+1:
+    mov x0, #(1 << 31)
+    msr hcr_el2, x0
+
+    /* Generic timers. */ 
+    mrs  x0, cnthctl_el2
+    orr  x0, x0, #3       // Enable EL1 physicaltimers
+    msr  cnthctl_el2, x0
+
+    /* Populate ID registers. */
+    mrs  x0,    midr_el1
+    mrs  x1,    mpidr_el1
+    msr  vpidr_el2,  x0
+    msr  vmpidr_el2, x1
+
+    /* Disable Coprocessor traps. */
+    mov x0, #0x33ff
+    msr  cptr_el2, x0 // Disable copro. traps to EL2
+    
+    msr  hstr_el2, xzr // Disable CP15 traps to EL2
+
+    mov x0, sp
+    msr sp_el1, x0
+
+    mrs x0, sctlr_el1
+    orr x0, x0, #(1 << 0)
+    bic x0, x0, #(1 << 1)
+    orr x0, x0, #(1 << 2)
+    msr sctlr_el1, x0
+
+    /* spsr */
+    mov x0, #SPSR_EL2_VALUE
+    msr spsr_el2, x0
+    msr elr_el2, lr
+    eret
+    .endfunc
+
+    .func __cpu_mair_setup
+__cpu_mair_setup:
+	tlbi	vmalle1				// Invalidate local TLB
+	dsb	nsh
+
+//	mov	x0, #3 << 20
+//	msr	cpacr_el1, x0			// Enable FP/ASIMD
+//	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
+//	msr	mdscr_el1, x0			// access to the DCC from EL0
+	isb					// Unmask debug exceptions now,
+//	enable_dbg				// since this is per-cpu
+	/*
+	 * Memory region attributes for LPAE:
+	 *
+	 *   n = AttrIndx[2:0]
+	 *			n	MAIR
+	 *   DEVICE_nGnRnE	000	00000000
+	 *   DEVICE_nGnRE	001	00000100
+	 *   DEVICE_GRE		010	00001100
+	 *   NORMAL_NC		011	01000100
+	 *   NORMAL		100	11111111
+	 *   NORMAL_WT		101	10111011
+	 */
+	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
+		     MAIR(0x04, MT_DEVICE_nGnRE) | \
+		     MAIR(0x0c, MT_DEVICE_GRE) | \
+		     MAIR(0x44, MT_NORMAL_NC) | \
+		     MAIR(0xff, MT_NORMAL) | \
+		     MAIR(0xbb, MT_NORMAL_WT)
+	msr	mair_el1, x5
+
+    ret
+    .endfunc
+
+
+    .end  

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/config.mk

@@ -1,8 +1,7 @@
 export CROSS_COMPILE ?= aarch64-none-elf-
-export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
-export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC 
-# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
-export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
+export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
+export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
+export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds -Wl,--start-group,-lgcc,-lc,--end-group
 export CXXFLAGS := 
 
 export DEFINES := -DHAVE_CCONFIG_H -DCHIP_LS1028

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/cortexA55.S

@@ -1,14 +1,14 @@
 /*!
- * @file cortexA72.s
- * @brief This file contains cortexA72 functions
+ * @file cortexA55.s
+ * @brief This file contains cortexA55 functions
  *
  */
 /*************************************************
-File name: cortexA72.S
+File name: cortexA55.S
 Description: This file contains cortexA9 functions
 Others: 
 History:
-1. Date: 202-05-08
+1. Date: 2024-05-08
 Author: AIIT XUOS Lab
 Modification:
 1. No modifications
@@ -21,7 +21,8 @@ Modification:
     .func cpu_get_current
 cpu_get_current:
     mrs   x0, mpidr_el1
-    and   x0, x0, #3
+    and   x0, x0, #0xFFF
+    lsr   x0, x0, #8
     ret
     .endfunc
 
@@ -32,6 +33,6 @@ psci_call:
 
 
 # ------------------------------------------------------------
-# End of cortexA72.s
+# End of cortexA55.s
 # ------------------------------------------------------------
     .end

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/include/cortex_a55.h

@@ -28,16 +28,16 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /**
- * @file cortex_a72.h
- * @brief some cortex A72 core functions
+ * @file cortex_a55.h
+ * @brief some cortex A55 core functions
  * @version 1.0
  * @author AIIT XUOS Lab
  * @date 2024.04.24
  */
 
 /*************************************************
-File name: cortex_a72.h
-Description: some cortex A72 core functions
+File name: cortex_a55.h
+Description: some cortex A55 core functions
 Others:
 History:
 Author: AIIT XUOS Lab
@@ -45,8 +45,8 @@ Modification:
 1. No modifications
 *************************************************/
 
-#if !defined(__CORTEX_A72_H__)
-#define __CORTEX_A72_H__
+#if !defined(__CORTEX_A55_H__)
+#define __CORTEX_A55_H__
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -231,4 +231,4 @@ void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
 }
 #endif
 
-#endif //__CORTEX_A72_H__
+#endif //__CORTEX_A55_H__

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c

@@ -48,12 +48,34 @@ Modification:
 #include <stdint.h>
 
 #define PSCI_CPUON 0xc4000003
+struct xizi_smccc_res {
+    unsigned long a0;
+    unsigned long a1;
+    unsigned long a2;
+    unsigned long a3;
+};
 
 extern void _boot_start();
-void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid);
+extern void __print();
+
+extern void __xizi_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
+    unsigned long a3, unsigned long a4, unsigned long a5,
+    unsigned long a6, unsigned long a7, struct xizi_smccc_res* res);
+
+static struct xizi_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
+    unsigned long arg0,
+    unsigned long arg1,
+    unsigned long arg2)
+{
+    struct xizi_smccc_res res;
+
+    __xizi_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
+    return res;
+}
+
 void cpu_start_secondary(uint8_t cpu_id)
 {
-    psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
+    __invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0);
 }
 
 void start_smp_cache_broadcast(int cpu_id)

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/xizi_smp.S

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *    http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+.global __xizi_smccc_smc
+
+.func __xizi_smccc_smc
+__xizi_smccc_smc:
+    smc #0
+    ldr	x4, [sp]
+    stp	x0, x1, [x4, #0]
+    stp	x2, x3, [x4, #16]
+    ldr	x4, [sp, #8]
+    cbz	x4, 1f /* no quirk structure */
+    ldr	x9, [x4, #0]
+    cmp	x9, #1
+    b.ne	1f
+    str	x6, [x4, 8]
+1:  ret
+.endfunc

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S

@@ -1,81 +0,0 @@
-// #include "memlayout.h"
-#include "core.h"
-// #include "registers.h"
-// #include "cortex_a72.h"
-        // qemu -kernel loads the kernel at 0x40000000
-        // and causes each CPU to jump there.
-        // kernel.ld causes the following code to
-        // be placed at 0x40000000.
-.section ".text"
-//.global _entry
-.global _boot_start
-.global primary_cpu_init
-
-_boot_start:
-        // set up a stack for C.
-        // stack0 is declared in start.c,
-        // with a 4096-byte stack per CPU.
-        // sp = stack0 + ((cpuid+1) * 4096)
-        // cpuid = mpidr_el1 & 0xff
-        // save r0 for cores 1-3, r0 arg field passed by ROM
-        // r0 is a function pointer for secondary cpus
-
-        // mov x4, 	x0
-
-        mrs	x0, 	spsr_el1    /* Enter EL1 (Exception Level 1) */
-        bic	x0, 	x0, #0x1f
-        MOV     x1,     #0xC5
-        ORR     x0,     x0, x1
-        msr	spsr_el1,	x0                
-
-
-        /* set NSACR, both Secure and Non-secure access are allowed to NEON */
-        MRS     X1,     CPACR_EL1
-        ORR     X1,     X1, #(0X3 << 20)
-        MSR     CPACR_EL1, X1
-        ISB
-
-        // clear some registers
-        msr     elr_el1, XZR
-
-        ldr     x0, =stacks_top
-        mov     x1, #MODE_STACK_SIZE
-
-         // get cpu id, and subtract the offset from the stacks base address
-        mrs     x2,     mpidr_el1
-        and     x2,     x2, #0x3
-        mov     x5,     x2
-        mul     x3,     x2, x1
-        sub     x0,     x0, x3
-        
-        MOV     X2,     #ARM_MODE_EL1_h | DIS_INT  
-        MSR     SPSR_EL1, X2
-        mov     sp,     x0
-        SUB     x0,     x0,x1
-
-            // check cpu id - cpu0 is primary cpu
-        cmp     x5, 	#0
-        beq     primary_cpu_init
-        bl      bootmain     // for secondary cpus, jump to argument function pointer passed in by ROM
-
-        bl      .
-
-primary_cpu_init:
-   	/* init .bss */
-         /* clear the .bss section (zero init) */
-        ldr     x1,	=boot_start_addr
-        ldr     x2,	=boot_end_addr
-        mov     x3,	#0
-        1:  
-        cmp     x1,	x2
-        stp     x3,     x3, [x1], #16
-        b.lt     1b        
-
-        // branch to c library entry point 
-        mov     x0,		#0 // argc
-        mov     x1,		#0 // argv
-        mov     x2,		#0 // env
-
-	bl bootmain
-
-	.end

Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile

@@ -1,8 +1,8 @@
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := cortex-a9
 endif
-ifneq ($(findstring $(BOARD), ok1028a-c), )
-SRC_DIR := cortex-a72
+ifneq ($(findstring $(BOARD), 3568), )
+SRC_DIR := cortex-a55
 endif
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := l1_cache.c cache.S
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/cache.S

@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * This file is based on sample code from ARMv8 ARM.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#define ASM_NL		 ;
+
+#define SYMBOL_NAME(X)		X
+
+// #define SYMBOL_NAME_LABEL(X)	X##:
+
+#define SYMBOL_NAME_LABEL(X)	X:
+
+#ifndef __ALIGN
+#define __ALIGN .align		4
+#endif
+
+#ifndef __ALIGN_STR
+#define __ALIGN_STR		".align 4"
+#endif
+
+#define ALIGN			__ALIGN
+#define ALIGN_STR		__ALIGN_STR
+
+#define LENTRY(name) \
+	ALIGN ASM_NL \
+	SYMBOL_NAME_LABEL(name)
+
+#define ENTRY(name) \
+	.globl SYMBOL_NAME(name) ASM_NL \
+	LENTRY(name)
+
+#define WEAK(name) \
+	.weak SYMBOL_NAME(name) ASM_NL \
+	LENTRY(name)
+
+
+#define END(name) \
+	.size name, .-name
+
+#define ENDPROC(name) \
+	.type name STT_FUNC ASM_NL \
+	END(name)
+
+#define CR_M		(1 << 0)	/* MMU enable			*/
+#define CR_A		(1 << 1)	/* Alignment abort enable	*/
+#define CR_C		(1 << 2)	/* Dcache enable		*/
+#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
+#define CR_I		(1 << 12)	/* Icache enable		*/
+#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
+#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
+
+.macro switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	b.eq	\el3_label
+	cmp	\xreg, 0x8
+	b.eq	\el2_label
+	cmp	\xreg, 0x4
+	b.eq	\el1_label
+.endm
+
+
+/*
+ * void __asm_dcache_level(level)
+ * flush or invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 clean & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+ENTRY(__asm_dcache_level)
+	lsl	x12, x0, #1
+	msr	csselr_el1, x12		/* select cache level */
+	isb				/* sync change of cssidr_el1 */
+	mrs	x6, ccsidr_el1		/* read the new cssidr_el1 */
+	and	x2, x6, #7		/* x2 <- log2(cache line size)-4 */
+	add	x2, x2, #4		/* x2 <- log2(cache line size) */
+	mov	x3, #0x3ff
+	and	x3, x3, x6, lsr #3	/* x3 <- max number of #ways */
+	clz	w5, w3			/* bit position of #ways */
+	mov	x4, #0x7fff
+	and	x4, x4, x6, lsr #13	/* x4 <- max number of #sets */
+	/* x12 <- cache level << 1 */
+	/* x2 <- line length offset */
+	/* x3 <- number of cache ways - 1 */
+	/* x4 <- number of cache sets - 1 */
+	/* x5 <- bit position of #ways */
+
+loop_set:
+	mov	x6, x3			/* x6 <- working copy of #ways */
+loop_way:
+	lsl	x7, x6, x5
+	orr	x9, x12, x7		/* map way and level to cisw value */
+	lsl	x7, x4, x2
+	orr	x9, x9, x7		/* map set number to cisw value */
+	tbz	w1, #0, 1f
+	dc	isw, x9
+	b	2f
+1:	dc	cisw, x9		/* clean & invalidate by set/way */
+2:	subs	x6, x6, #1		/* decrement the way */
+	b.ge	loop_way
+	subs	x4, x4, #1		/* decrement the set */
+	b.ge	loop_set
+
+	ret
+ENDPROC(__asm_dcache_level)
+
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+
+ENTRY(__asm_dcache_all)
+	mov	x1, x0
+	dsb	sy
+	mrs	x10, clidr_el1		/* read clidr_el1 */
+	lsr	x11, x10, #24
+	and	x11, x11, #0x7		/* x11 <- loc */
+	cbz	x11, finished		/* if loc is 0, exit */
+	mov	x15, lr
+	mov	x0, #0			/* start flush at cache level 0 */
+	/* x0  <- cache level */
+	/* x10 <- clidr_el1 */
+	/* x11 <- loc */
+	/* x15 <- return address */
+
+loop_level:
+	lsl	x12, x0, #1
+	add	x12, x12, x0		/* x0 <- tripled cache level */
+	lsr	x12, x10, x12
+	and	x12, x12, #7		/* x12 <- cache type */
+	cmp	x12, #2
+	b.lt	skip			/* skip if no cache or icache */
+	bl	__asm_dcache_level	/* x1 = 0 flush, 1 invalidate */
+skip:
+	add	x0, x0, #1		/* increment cache level */
+	cmp	x11, x0
+	b.gt	loop_level
+
+	mov	x0, #0
+	msr	csselr_el1, x0		/* restore csselr_el1 */
+	dsb	sy
+	isb
+	mov	lr, x15
+
+finished:
+	ret
+ENDPROC(__asm_dcache_all)
+
+
+ENTRY(__asm_flush_dcache_all)
+	mov	x0, #0
+	b	__asm_dcache_all
+ENDPROC(__asm_flush_dcache_all)
+
+
+ENTRY(__asm_invalidate_dcache_all)
+	mov	x0, #0x1
+	b	__asm_dcache_all
+ENDPROC(__asm_invalidate_dcache_all)
+
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+
+ENTRY(__asm_flush_dcache_range)
+	isb
+	mrs	x3, ctr_el0
+	lsr	x3, x3, #16
+	and	x3, x3, #0xf
+	mov	x2, #4
+	lsl	x2, x2, x3		/* cache line size */
+
+	/* x2 <- minimal cache line size in cache system */
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	civac, x0	/* clean & invalidate data or unified cache */
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	isb
+	ret
+ENDPROC(__asm_flush_dcache_range)
+
+/*
+ * void __asm_invalidate_dcache_range(start, end)
+ *
+ * invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+
+ENTRY(__asm_invalidate_dcache_range)
+	mrs	x3, ctr_el0
+	ubfm	x3, x3, #16, #19
+	mov	x2, #4
+	lsl	x2, x2, x3		/* cache line size */
+
+	/* x2 <- minimal cache line size in cache system */
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	ivac, x0	/* invalidate data or unified cache */
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	isb
+	ret
+ENDPROC(__asm_invalidate_dcache_range)
+
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+
+ENTRY(__asm_invalidate_icache_all)
+	ic	ialluis
+	isb	sy
+	ret
+ENDPROC(__asm_invalidate_icache_all)
+
+
+
+ENTRY(__asm_invalidate_l3_dcache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_invalidate_l3_dcache)
+	.weak	__asm_invalidate_l3_dcache
+
+
+
+ENTRY(__asm_flush_l3_dcache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_flush_l3_dcache)
+	.weak	__asm_flush_l3_dcache
+
+
+
+ENTRY(__asm_invalidate_l3_icache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_invalidate_l3_icache)
+	.weak	__asm_invalidate_l3_icache
+
+
+/*
+ * void __asm_switch_ttbr(ulong new_ttbr)
+ *
+ * Safely switches to a new page table.
+ */
+
+ENTRY(__asm_switch_ttbr)
+	/* x2 = SCTLR (alive throghout the function) */
+	switch_el x4, 3f, 2f, 1f
+3:	mrs	x2, sctlr_el3
+	b	0f
+2:	mrs	x2, sctlr_el2
+	b	0f
+1:	mrs	x2, sctlr_el1
+0:
+
+	/* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
+	movn	x1, #(CR_M | CR_C | CR_I)
+	and	x1, x2, x1
+	switch_el x4, 3f, 2f, 1f
+3:	msr	sctlr_el3, x1
+	b	0f
+2:	msr	sctlr_el2, x1
+	b	0f
+1:	msr	sctlr_el1, x1
+0:	isb
+
+	/* This call only clobbers x30 (lr) and x9 (unused) */
+	mov	x3, x30
+	bl	__asm_invalidate_tlb_all
+
+	/* From here on we're running safely with caches disabled */
+
+	/* Set TTBR to our first argument */
+	switch_el x4, 3f, 2f, 1f
+3:	msr	ttbr0_el3, x0
+	b	0f
+2:	msr	ttbr0_el2, x0
+	b	0f
+1:	msr	ttbr0_el1, x0
+0:	isb
+
+	/* Restore original SCTLR and thus enable caches again */
+	switch_el x4, 3f, 2f, 1f
+3:	msr	sctlr_el3, x2
+	b	0f
+2:	msr	sctlr_el2, x2
+	b	0f
+1:	msr	sctlr_el1, x2
+0:	isb
+
+	ret	x3
+ENDPROC(__asm_switch_ttbr)
+
+ENTRY(__asm_invalidate_tlb_all)
+	switch_el x9, 3f, 2f, 1f
+3:	tlbi	alle3
+	dsb	sy
+	isb
+	b	0f
+2:	tlbi	alle2
+	dsb	sy
+	isb
+	b	0f
+1:	tlbi	vmalle1
+	dsb	sy
+	isb
+0:
+	ret
+ENDPROC(__asm_invalidate_tlb_all)

Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.c

@@ -20,6 +20,10 @@ Modification:
 *************************************************/
 
 #include "l1_cache.h"
+extern void __asm_flush_dcache_all();
+extern void __asm_flush_l3_dcache();
+extern void __asm_invalidate_icache_all();
+extern void __asm_invalidate_l3_icache();
 
 void InvalidateL1Dcache(uintptr_t start, uintptr_t end)
 {
@@ -153,34 +157,14 @@ void FlushL1Dcache(uintptr_t start, uintptr_t end)
 
 void FlushL1DcacheAll(void)
 {
-    uint64_t ccsidr_el1; // Cache Size ID
-    int num_sets; // number of sets
-    int num_ways; // number of ways
-    uint32_t wayset; // wayset parameter
-
-    __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID
-
-    // Fill number of sets  and number of ways from ccsidr_el1 register  This walues are decremented by 1
-    num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1;
-    num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1;
-
-    // clean and invalidate all lines (all Sets in all ways)
-    for (int way = 0; way < num_ways; way++) {
-        for (int set = 0; set < num_sets; set++) {
-            wayset = (way << 30) | (set << 5);
-            __asm__ __volatile__("dc cisw, %0" : : "r"(wayset));
-        }
-    }
-
-    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
-    DSB();
+    __asm_flush_dcache_all();
+    __asm_flush_l3_dcache();
 }
 
 void InvalidateL1IcacheAll()
 {
-    __asm__ __volatile__("ic iallu\n\t");
-    // synchronize context on this processor
-    ISB();
+    __asm_invalidate_icache_all();
+    __asm_invalidate_l3_icache();
 }
 
 void InvalidateL1Icache(uintptr_t start, uintptr_t end)

Ubiquitous/XiZi_AIoT/hardkernel/cache/cache_common_ope.c

@@ -92,7 +92,7 @@ static inline void invalidate_icache(uintptr_t start, uintptr_t end)
 
 static inline void invalidate_icache_all(void)
 {
-    // InvalidateL1IcacheAll();
+    InvalidateL1IcacheAll();
 }
 
 /****************************************************************************
@@ -151,7 +151,7 @@ static inline void flush_dcache(uintptr_t start, uintptr_t end)
 
 static inline void flush_dcache_all(void)
 {
-    // FlushL1DcacheAll();
+    FlushL1DcacheAll();
     // FlushL2CacheAll();
 }
 

Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/Makefile

@@ -1,4 +1,4 @@
-ifneq ($(findstring $(BOARD), ok1028a-c), )
+ifneq ($(findstring $(BOARD), 3568), )
 SRC_DIR := armv8-a
 endif
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )

Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/Makefile

@@ -1,5 +1,5 @@
-ifneq ($(findstring $(BOARD), ok1028a-c), )
-SRC_DIR := cortex-a72
+ifneq ($(findstring $(BOARD), 3568), )
+SRC_DIR := cortex-a55
 endif
 
 

Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/clock.c

@@ -22,27 +22,27 @@
 
 static void enable_timer()
 {
-    uint32_t c = r_cntv_ctl_el0();
+    uint32_t c = r_cntp_ctl_el0();
     c |= CNTV_CTL_ENABLE;
     c &= ~CNTV_CTL_IMASK;
-    w_cntv_ctl_el0(c);
+    w_cntp_ctl_el0(c);
 }
 
 static void disable_timer()
 {
-    uint32_t c = r_cntv_ctl_el0();
+    uint32_t c = r_cntp_ctl_el0();
     c |= CNTV_CTL_IMASK;
     c &= ~CNTV_CTL_ENABLE;
-    w_cntv_ctl_el0(c);
+    w_cntp_ctl_el0(c);
 }
 
 static void reload_timer()
 {
-    // interval 100ms
-    static uint32_t ms = 10;
+    // interval 1ms
+    static uint32_t ms = 1;
     uint32_t interval = ms * 1000;
     uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000);
-    w_cntv_tval_el0(interval_clk);
+    w_cntp_tval_el0(interval_clk);
 }
 
 void _sys_clock_init()
@@ -54,7 +54,7 @@ void _sys_clock_init()
 
 static uint32_t _get_clock_int()
 {
-    return 27;
+    return 30;
 }
 
 static uint64_t _get_tick()
@@ -64,7 +64,7 @@ static uint64_t _get_tick()
 
 static uint64_t _get_second()
 {
-    return 0;
+    return _get_tick() / r_cntfrq_el0();
 }
 
 static bool _is_timer_expired()

Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a55/3568/include/generic_timer.h

@@ -15,28 +15,28 @@
 #include <stdint.h>
 
 // armv8 generic timer
-static inline uint32_t r_cntv_ctl_el0()
+static inline uint32_t r_cntp_ctl_el0()
 {
     uint32_t x;
-    __asm__ volatile("mrs %0, cntv_ctl_el0" : "=r"(x));
+    __asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x));
     return x;
 }
 
-static inline void w_cntv_ctl_el0(uint32_t x)
+static inline void w_cntp_ctl_el0(uint32_t x)
 {
-    __asm__ volatile("msr cntv_ctl_el0, %0" : : "r"(x));
+    __asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x));
 }
 
-static inline uint32_t r_cntv_tval_el0()
+static inline uint32_t r_cntp_tval_el0()
 {
     uint32_t x;
-    __asm__ volatile("mrs %0, cntv_tval_el0" : "=r"(x));
+    __asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x));
     return x;
 }
 
-static inline void w_cntv_tval_el0(uint32_t x)
+static inline void w_cntp_tval_el0(uint32_t x)
 {
-    __asm__ volatile("msr cntv_tval_el0, %0" : : "r"(x));
+    __asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x));
 }
 
 static inline uint64_t r_cntvct_el0()

Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c

@@ -220,6 +220,7 @@ bool secondary_cpu_hardkernel_init(int cpu_id, struct TraceTag* _hardkernel_tag)
     p_icache_driver->enable();
     p_dcache_driver->enable();
     // clock
+    p_clock_driver->sys_clock_init();
     p_intr_driver->single_irq_enable(p_clock_driver->get_clock_int(), cpu_id, 0);
     // mmu
     secondary_cpu_load_kern_pgdir(&init_mmu_tag, &init_intr_tag);

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile

@@ -1,4 +1,4 @@
-ifneq ($(findstring $(BOARD), ok1028a-c), )
+ifneq ($(findstring $(BOARD), 3568), )
 SRC_DIR := armv8-a
 endif
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile

@@ -1,3 +1,3 @@
-SRC_DIR := cortex-a72
+SRC_DIR := cortex-a55
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap.c

@@ -28,13 +28,16 @@ Modification:
 *************************************************/
 #include <stdint.h>
 
+#include "exception_registers.h"
+
 #include "assert.h"
 #include "core.h"
-#include "exception_registers.h"
 #include "multicores.h"
 #include "syscall.h"
 #include "task.h"
 
+#include "mmu.h"
+
 extern void dabort_handler(struct trapframe* r);
 extern void iabort_handler(struct trapframe* r);
 
@@ -73,7 +76,6 @@ void syscall_arch_handler(struct trapframe* tf)
 
     uint64_t esr = r_esr_el1();
     uint64_t ec = (esr >> 0x1A) & 0x3F;
-    w_esr_el1(0);
     switch (ec) {
     case 0B010101:
         software_irq_dispatch(tf);
@@ -87,11 +89,30 @@ void syscall_arch_handler(struct trapframe* tf)
         iabort_handler(tf);
         break;
     default: {
-        ERROR("USYSCALL: unexpected ec: %016lx", esr);
+        ERROR("USYSCALL: unexpected\n");
+        ERROR("          esr: %016lx\n", esr);
         ERROR("          elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
+        w_esr_el1(0);
+        extern void dump_tf(struct trapframe * tf);
+        dump_tf(tf);
+
+        uint32_t sctlr = 0;
+        SCTLR_R(sctlr);
+        DEBUG("SCTLR: %x\n", sctlr);
+        uint32_t spsr = 0;
+        __asm__ volatile("mrs %0, spsr_el1" : "=r"(spsr)::"memory");
+        DEBUG("SPSR: %x\n", spsr);
+        uint64_t tcr = 0;
+        __asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr)::"memory");
+        DEBUG("TCR: %x\n", tcr);
+        uint64_t mair = 0;
+        __asm__ volatile("mrs %0, mair_el1" : "=r"(mair)::"memory");
+        DEBUG("MAIR: %x\n", mair);
+
         // kill error task
         xizi_enter_kernel();
         assert(cur_cpu()->task != NULL);
+        ERROR("Error Task: %s\n", cur_cpu()->task->name);
         sys_exit(cur_cpu()->task);
         context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler);
         panic("dabort end should never be reashed.\n");

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/3568/trap_common.c

@@ -29,7 +29,7 @@ Modification:
 #include <string.h>
 
 #include "core.h"
-#include "cortex_a72.h"
+#include "cortex_a55.h"
 #include "exception_registers.h"
 #include "gicv3_common_opa.h"
 #include "trap_common.h"
@@ -70,7 +70,12 @@ static void _cpu_irq_disable(void)
 
 static void _single_irq_enable(int irq, int cpu, int prio)
 {
-    gic_setup_ppi((uint32_t)cpu, (uint32_t)irq);
+    if (irq < 32) {
+        gic_setup_ppi((uint32_t)cpu, (uint32_t)irq);
+    }
+    else {
+        gic_setup_spi((uint32_t)cpu, (uint32_t)irq);
+    }
 }
 
 static void _single_irq_disable(int irq, int cpu)

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/Makefile

@@ -1,6 +1,6 @@
 SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S
 
-ifeq ($(BOARD), ok1028a-c)
+ifeq ($(BOARD), 3568)
 SRC_DIR := gicv3
 SRC_FILES += $(BOARD)/
 endif

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/error_debug.c

@@ -39,51 +39,53 @@ Modification:
 2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler())
 *************************************************/
 #include <stddef.h>
+#include <stdint.h>
+
+#include "exception_registers.h"
 
 #include "assert.h"
 #include "core.h"
 #include "log.h"
 #include "multicores.h"
-#include "spinlock.h"
 #include "task.h"
 #include "trap_common.h"
 
 void dump_tf(struct trapframe* tf)
 {
-    KPrintf("   sp:   0x%x\n", tf->sp);
-    KPrintf("   pc:   0x%x\n", tf->pc);
-    KPrintf("   spsr: 0x%x\n", tf->spsr);
-    KPrintf("     x0: 0x%x\n", tf->x0);
-    KPrintf("     x1: 0x%x\n", tf->x1);
-    KPrintf("     x2: 0x%x\n", tf->x2);
-    KPrintf("     x3: 0x%x\n", tf->x3);
-    KPrintf("     x4: 0x%x\n", tf->x4);
-    KPrintf("     x5: 0x%x\n", tf->x5);
-    KPrintf("     x6: 0x%x\n", tf->x6);
-    KPrintf("     x7: 0x%x\n", tf->x7);
-    KPrintf("     x8: 0x%x\n", tf->x8);
-    KPrintf("     x9: 0x%x\n", tf->x9);
-    KPrintf("    x10: 0x%x\n", tf->x10);
-    KPrintf("    x11: 0x%x\n", tf->x11);
-    KPrintf("    x12: 0x%x\n", tf->x12);
-    KPrintf("    x13: 0x%x\n", tf->x13);
-    KPrintf("    x14: 0x%x\n", tf->x14);
-    KPrintf("    x15: 0x%x\n", tf->x15);
-    KPrintf("    x16: 0x%x\n", tf->x16);
-    KPrintf("    x17: 0x%x\n", tf->x17);
-    KPrintf("    x18: 0x%x\n", tf->x18);
-    KPrintf("    x19: 0x%x\n", tf->x19);
-    KPrintf("    x20: 0x%x\n", tf->x20);
-    KPrintf("    x21: 0x%x\n", tf->x21);
-    KPrintf("    x22: 0x%x\n", tf->x22);
-    KPrintf("    x23: 0x%x\n", tf->x23);
-    KPrintf("    x24: 0x%x\n", tf->x24);
-    KPrintf("    x25: 0x%x\n", tf->x25);
-    KPrintf("    x26: 0x%x\n", tf->x26);
-    KPrintf("    x27: 0x%x\n", tf->x27);
-    KPrintf("    x28: 0x%x\n", tf->x28);
-    KPrintf("    x29: 0x%x\n", tf->x29);
-    KPrintf("    x30: 0x%x\n", tf->x30);
+    KPrintf("   sp:   0x%016lx\n", tf->sp);
+    KPrintf("   pc:   0x%016lx\n", tf->pc);
+    KPrintf("   spsr: 0x%016lx\n", tf->spsr);
+    KPrintf("     x0: 0x%016lx\n", tf->x0);
+    KPrintf("     x1: 0x%016lx\n", tf->x1);
+    KPrintf("     x2: 0x%016lx\n", tf->x2);
+    KPrintf("     x3: 0x%016lx\n", tf->x3);
+    KPrintf("     x4: 0x%016lx\n", tf->x4);
+    KPrintf("     x5: 0x%016lx\n", tf->x5);
+    KPrintf("     x6: 0x%016lx\n", tf->x6);
+    KPrintf("     x7: 0x%016lx\n", tf->x7);
+    KPrintf("     x8: 0x%016lx\n", tf->x8);
+    KPrintf("     x9: 0x%016lx\n", tf->x9);
+    KPrintf("    x10: 0x%016lx\n", tf->x10);
+    KPrintf("    x11: 0x%016lx\n", tf->x11);
+    KPrintf("    x12: 0x%016lx\n", tf->x12);
+    KPrintf("    x13: 0x%016lx\n", tf->x13);
+    KPrintf("    x14: 0x%016lx\n", tf->x14);
+    KPrintf("    x15: 0x%016lx\n", tf->x15);
+    KPrintf("    x16: 0x%016lx\n", tf->x16);
+    KPrintf("    x17: 0x%016lx\n", tf->x17);
+    KPrintf("    x18: 0x%016lx\n", tf->x18);
+    KPrintf("    x19: 0x%016lx\n", tf->x19);
+    KPrintf("    x20: 0x%016lx\n", tf->x20);
+    KPrintf("    x21: 0x%016lx\n", tf->x21);
+    KPrintf("    x22: 0x%016lx\n", tf->x22);
+    KPrintf("    x23: 0x%016lx\n", tf->x23);
+    KPrintf("    x24: 0x%016lx\n", tf->x24);
+    KPrintf("    x25: 0x%016lx\n", tf->x25);
+    KPrintf("    x26: 0x%016lx\n", tf->x26);
+    KPrintf("    x27: 0x%016lx\n", tf->x27);
+    KPrintf("    x28: 0x%016lx\n", tf->x28);
+    KPrintf("    x29: 0x%016lx\n", tf->x29);
+    KPrintf("    x30: 0x%016lx\n", tf->x30);
 }
 
 void dabort_reason(struct trapframe* r)
@@ -91,8 +93,9 @@ void dabort_reason(struct trapframe* r)
     uint32_t fault_status, fault_address;
     __asm__ __volatile__("mrs %0, esr_el1" : "=r"(fault_status));
     __asm__ __volatile__("mrs %0, far_el1" : "=r"(fault_address));
-    LOG("program counter: 0x%x caused\n", r->pc);
-    LOG("data abort at 0x%x, status 0x%x\n", fault_address, fault_status);
+    w_esr_el1(0);
+    LOG("program counter: 0x%016lx caused\n", r->pc);
+    LOG("data abort at 0x%016lx, status 0x%016lx\n", fault_address, fault_status);
     if ((fault_status & 0x3f) == 0x21) // Alignment failure
         KPrintf("reason: alignment\n");
     else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0
@@ -131,8 +134,9 @@ void iabort_reason(struct trapframe* r)
     uint32_t fault_status, fault_address;
     __asm__ __volatile__("mrs %0, esr_el1" : "=r"(fault_status));
     __asm__ __volatile__("mrs %0, far_el1" : "=r"(fault_address));
-    LOG("program counter: 0x%x caused\n", r->pc);
-    LOG("data abort at 0x%x, status 0x%x\n", fault_address, fault_status);
+    LOG("program counter: 0x%016lx caused\n", r->pc);
+    LOG("data abort at 0x%016lx, status 0x%016lx\n", fault_address, fault_status);
+    w_esr_el1(0);
     if ((fault_status & 0x3f) == 0x21) // Alignment failure
         KPrintf("reason: alignment\n");
     else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3/gicv3_registers.h

@@ -30,8 +30,8 @@ Modification:
 
 // clang-format off
 // interrupt controller GICv3
-#define GICV3               MMIO_P2V_WO(0x08000000ULL)
-#define GICV3_REDIST        MMIO_P2V_WO(0x080a0000ULL)
+#define GICV3               MMIO_P2V_WO(0xFD400000ULL)
+#define GICV3_REDIST        MMIO_P2V_WO(0xFD460000ULL)
 
 #define D_CTLR 0x0
 #define D_TYPER 0x4

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/hard_spinlock.S

@@ -55,62 +55,56 @@ Modification:
 #define UNLOCKED 0xFF
 // int spinlock_lock(spinlock_t * lock, uint64_t timeout)
     .global _spinlock_lock
-    .func _spinlock_lock
+.func _spinlock_lock
 _spinlock_lock:
-mov     w2, #1
+    mov     w2, #1
+    sevl
+1: 
+    wfe
 
-sevl
-wfe
+2: 
+    ldaxrb  w1, [x0]                     // check if the spinlock is currently unlocked
+    cmp     w1, #UNLOCKED
+    bne     1b
 
-ldaxrb  w1, [x0]                     // check if the spinlock is currently unlocked
-cmp     w1, #UNLOCKED
-bne     _spinlock_lock
+    mrs     x1, mpidr_el1                // get our CPU ID
+    and     x1, x1, #0xFFF
+    lsr     x1, x1, #8
+    stxrb   w2, w1, [x0]
+    cmp     x2, #0
+    bne     2b        // check if the write was successful, if the write failed, start over
 
-mrs     x1, mpidr_el1                // get our CPU ID
-and     x1, x1, #3
-stxrb   w2, w1, [x0]
-cmp     x2, #0
-bne     _spinlock_lock        // check if the write was successful, if the write failed, start over
+    dmb    ish                        // Ensure that accesses to shared resource have completed
 
-dmb    ish                        // Ensure that accesses to shared resource have completed
-
-mov    x0, #0
-ret
-
-    .endfunc 
+    mov    x0, #0
+    ret
+.endfunc 
 
 
 // void spinlock_unlock(spinlock_t * lock)
     .global _spinlock_unlock
     .func _spinlock_unlock
 _spinlock_unlock:
+    mrs     x1, mpidr_el1                // get our CPU ID
+    and     x1, x1, #0xFFF
+    lsr     x1, x1, #8
 
-mrs     x1, mpidr_el1                // get our CPU ID
-and     x1, x1, #3
+    ldr     w2, [x0]
+    cmp     w1, w2
+    bne     1f                                       //doesn't match,jump to 1
 
-ldr     w2, [x0]
-cmp     w1, w2
-bne     1f                                       //doesn't match,jump to 1
-
-
-dmb     ish
-
-mov     w1, #UNLOCKED 
-str     w1, [x0]
-
-dsb     ish                                //Ensure that no instructions following the barrier execute until
-                                           // all memory accesses prior to the barrier have completed.
-
-
-sevl                                          // send event to wake up other cores waiting on spinlock
-
-mov     x0, #0                               // return success
-ret
+    dmb     ish
+    mov     w1, #UNLOCKED 
+    str     w1, [x0]
+    dsb     ish                                 //Ensure that no instructions following the barrier execute until
+                                                // all memory accesses prior to the barrier have completed.
+    sevl                                          // send event to wake up other cores waiting on spinlock
 
+    mov     x0, #0                               // return success
+    ret
 1:
-mov     x0, #1                              //doesn't match, so exit with failure
-ret
-
+    mov     x0, #1                              //doesn't match, so exit with failure
+    ret
 .endfunc
 
 .end

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a55/trampoline.S

@@ -143,13 +143,13 @@ Modification:
 .balign 0x800
 alltraps:
 // Current EL with sp0
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 
 // Current EL with spx
 .balign 0x80
@@ -157,9 +157,9 @@ alltraps:
 .balign 0x80
   b el1irq
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 
 // Lower EL using aarch64
 .balign 0x80
@@ -167,32 +167,34 @@ alltraps:
 .balign 0x80
   b el0irq
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 
 // Lower EL using aarch32
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
 .balign 0x80
-  b .
+  b badtrap
+
+badtrap:
+        savereg
+        mov x0, sp
+        bl  kernel_intr_handler 
+        b   .
 
 el1sync:
-        msr daifset, #0xf
         savereg
-        
         mov x0, sp
         bl  kernel_abort_handler 
         b   .
       
 el1irq:
-        msr daifset, #0xf
         usavereg
-      
         mov x0, sp
         bl intr_irq_dispatch
 
@@ -201,9 +203,7 @@ el1irq:
         eret
       
 el0sync:
-        msr daifset, #0xf
         usavereg
-      
         mov x0, sp
         bl syscall_arch_handler
       
@@ -212,9 +212,7 @@ el0sync:
         eret
 
 el0irq:
-        msr daifset, #0xf
         usavereg
-      
         mov x0, sp
         bl intr_irq_dispatch
       

Ubiquitous/XiZi_AIoT/hardkernel/intr/spinlock.c

@@ -59,7 +59,7 @@ __attribute__((optimize("O0"))) void spinlock_init(struct spinlock* lock, char*
 }
 
 extern int _spinlock_lock(struct spinlock* lock, uint32_t timeout);
-extern void _spinlock_unlock(struct spinlock* lock);
+extern int _spinlock_unlock(struct spinlock* lock);
 
 __attribute__((optimize("O0"))) void spinlock_lock(struct spinlock* lock)
 {
@@ -88,7 +88,9 @@ __attribute__((optimize("O0"))) void spinlock_unlock(struct spinlock* lock)
     _double_list_del(p_lock_node->prev, p_lock_node->next);
     _spinlock_unlock(&request_lock);
 
-    _spinlock_unlock(lock);
+    if (_spinlock_unlock(lock) != 0) {
+        ERROR("Core %d trying to unlock a lock belongs to %d.\n", cur_cpuid(), lock->owner_cpu);
+    }
 }
 
 __attribute__((optimize("O0"))) bool spinlock_try_lock(struct spinlock* lock)

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/Makefile

@@ -1,4 +1,4 @@
-ifneq ($(findstring $(BOARD), ok1028a-c), )
+ifneq ($(findstring $(BOARD), 3568), )
 SRC_DIR := armv8-a
 endif
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c

@@ -48,7 +48,7 @@ uint32_t boot_pgdir[NR_PDE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 };
 static void build_boot_pgdir()
 {
     // dev mem
-    uint32_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SZ) >> LEVEL3_PDE_SHIFT;
+    uint32_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SIZE) >> LEVEL3_PDE_SHIFT;
     for (uint32_t i = DEV_PHYMEM_BASE >> LEVEL3_PDE_SHIFT; i < dev_mem_end_idx; i++) {
         boot_pgdir[i] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0;
         boot_pgdir[MMIO_P2V_WO(i << LEVEL3_PDE_SHIFT) >> LEVEL3_PDE_SHIFT] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0;

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h

@@ -67,7 +67,7 @@ Modification:
 /* Deivce memory layout */
 #define DEV_PHYMEM_BASE     (0x00000000)
 #define DEV_VRTMEM_BASE     (0x80000000)
-#define DEV_MEM_SZ          (0x10000000)
+#define DEV_MEM_SIZE          (0x10000000)
 
 /* Kernel memory layout */
 #define KERN_MEM_BASE       (0x90000000) // First kernel virtual address

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h

@@ -66,7 +66,7 @@ Modification:
 /* Deivce memory layout */
 #define DEV_PHYMEM_BASE     (0xE0000000)
 #define DEV_VRTMEM_BASE     (0x80000000)
-#define DEV_MEM_SZ          (0x1FFFFFFF)
+#define DEV_MEM_SIZE          (0x1FFFFFFF)
 
 /* Kernel memory layout */
 #define KERN_MEM_BASE       (0xA0000000) // First kernel virtual address

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile

@@ -1,3 +1,3 @@
-SRC_DIR := cortex-a72
+SRC_DIR := cortex-a55
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h

@@ -33,11 +33,11 @@ Modification:
 
 #define ARCH_BIT        64
 
-/* A72 physical memory layout */
-#define PHY_MEM_BASE            (0x0000000040000000ULL)
-#define PHY_USER_FREEMEM_BASE   (0x0000000046000000ULL)
-#define PHY_USER_FREEMEM_TOP    (0x0000000048000000ULL)
-#define PHY_MEM_STOP            (0x0000000048000000ULL)
+/* A55 physical memory layout */
+#define PHY_MEM_BASE            (0x0000000010000000ULL)
+#define PHY_USER_FREEMEM_BASE   (0x0000000040000000ULL)
+#define PHY_USER_FREEMEM_TOP    (0x00000000E0000000ULL)
+#define PHY_MEM_STOP            (0x00000000E0000000ULL)
 
 /* PTE-PAGE_SIZE */
 #define LEVEL4_PTE_SHIFT    12
@@ -58,23 +58,23 @@ Modification:
 #define NUM_TOPLEVEL_PDE    NUM_LEVEL2_PDE 
 
 #define PAGE_SIZE           LEVEL4_PTE_SIZE
-#define MAX_NR_FREE_PAGES   ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
+#define MAX_NR_FREE_PAGES   ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
 
 /* Deivce memory layout */
-#define DEV_PHYMEM_BASE     (0x0000000000000000ULL)
-#define DEV_VRTMEM_BASE     (0x0000004000000000ULL)
-#define DEV_MEM_SZ          (0x0000000010000000ULL)
+#define DEV_PHYMEM_BASE     (0x00000000F0000000ULL)
+#define DEV_VRTMEM_BASE     (0x00000040F0000000ULL)
+#define DEV_MEM_SIZE        (0x0000000010000000ULL)
 
 /* User memory layout */
 #define USER_STACK_SIZE     PAGE_SIZE
 #define USER_MEM_BASE       (0x0000000000000000ULL)
-#define USER_MEM_TOP        DEV_VRTMEM_BASE
+#define USER_MEM_TOP        (0x0000004000000000ULL)
 #define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
 #define USER_IPC_USE_ALLOCATOR_WATERMARK    (0x0000003000010000ULL)
 #define USER_IPC_SPACE_TOP  (USER_IPC_SPACE_BASE + 0x10000000ULL) 
 
 /* Kernel memory layout */
-#define KERN_MEM_BASE       (0x0000006040000000ULL) // First kernel virtual address
+#define KERN_MEM_BASE       (0x0000006010000000ULL) // First kernel virtual address
 #define KERN_OFFSET         (KERN_MEM_BASE - PHY_MEM_BASE)
 
 #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET)

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c

@@ -51,9 +51,9 @@ extern uint64_t kernel_data_begin[];
 #define L4_PTE_NORMAL       ((0b01) << 2) // Device memory
 #define L4_PTE_AF           (1 << 10) // Data Access Permissions
 
-#define L4_PTE_PXN             (1UL << 53)   // Privileged eXecute Never
-#define L4_PTE_UXN             (1UL << 54)   // Unprivileged(user) eXecute Never
-#define L4_PTE_XN              (PTE_PXN|PTE_UXN)  // eXecute Never
+#define L4_PTE_PXN          (1UL << 53)   // Privileged eXecute Never
+#define L4_PTE_UXN          (1UL << 54)   // Unprivileged(user) eXecute Never
+#define L4_PTE_XN           (PTE_PXN|PTE_UXN)  // eXecute Never
 
 #define IDX_MASK            (0b111111111)
 #define L3_PDE_INDEX(idx)   ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
@@ -62,64 +62,69 @@ extern uint64_t kernel_data_begin[];
 uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
 
 uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
-uint64_t boot_virt_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
 uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
-uint64_t boot_virt_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
 
 uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
 uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
 
 static void build_boot_pgdir()
 {
-    uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
-    // dev mem
-    boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
-    boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+    static bool built = false;
+    if (!built) {
+        uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
 
-    uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, PAGE_SIZE);
-    for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
-        boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
+        // dev mem
+        boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
 
-        for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
-            boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN;
+        uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE);
+        for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
+            boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
 
-            cur_mem_paddr += PAGE_SIZE;
+            for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
+                boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN;
+                if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
+                    boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
+                } else {
+                    boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
+                }
+
+                cur_mem_paddr += PAGE_SIZE;
+            }
         }
-    }
 
-    // identical mem
-    boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
-    boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        // identical mem
+        boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
 
-    cur_mem_paddr = ALIGNDOWN((uint64_t)PHY_MEM_BASE, PAGE_SIZE);
-    for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
-        boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
+        cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE);
+        for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
+            boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
 
-        for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
-            boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF;
+            for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
+                boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
 
-            cur_mem_paddr += PAGE_SIZE;
+                cur_mem_paddr += PAGE_SIZE;
+            }
         }
+
+        built = true;
     }
 }
 
 static void load_boot_pgdir()
 {
-    uint64_t val;
 
     TTBR0_W((uintptr_t)boot_l2pgdir);
     TTBR1_W(0);
 
-    TCR_W(TCR_VALUE);
-    MAIR_W((MT_DEVICE_nGnRnE << (8 * AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC << (8 * AI_NORMAL_NC_IDX)));
+#define TCR_TRUE_VALUE (0x0000000080813519ULL)
+    uint64_t tcr = 0;
+    TCR_R(tcr);
+    tcr &= (uint64_t)~0xFF;
+    tcr |= 0x19;
+    TCR_W(tcr);
 
-    // Enable paging using read/modify/write
-    SCTLR_R(val);
-    val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
-    SCTLR_W(val);
-
-    // flush all TLB
-    DSB();
     CLEARTLB(0);
     ISB();
 }
@@ -130,7 +135,7 @@ void bootmain()
 {
     build_boot_pgdir();
     load_boot_pgdir();
-    __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_MEM_BASE - PHY_MEM_BASE));
+    __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET));
     if (!_bss_inited) {
         memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
         _bss_inited = true;

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/include/mmu.h

@@ -61,35 +61,36 @@ void GetPdeAttr(uintptr_t* attr);
 /*
 Enable MMU, cache, write buffer, etc.
 */
-#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val))
-#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val))
+#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory")
+#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory")
 
 /*
 Read and write mmu pagetable register base addr
 */
-#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val))
-#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val))
+#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory")
+#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory")
 
 /*
 Read and write mmu pagetable register base addr
 */
-#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val))
-#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val))
+#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory")
+#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory")
 
 /*
 Translation Control Register（TCR）
 */
-#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val))
-#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val))
+#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory")
+#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory")
 
-#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val))
-#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val))
+#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory")
+#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory")
 
 /*
 Flush TLB when loading a new page table.
 @note If nG is not set in the pte attribute, process switching need flush tlb.
 */
-#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1")
+// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory")
+#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory")
 
 /*
 When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register.

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/mmu.c

@@ -45,7 +45,9 @@ void load_pgdir(uintptr_t pgdir_paddr)
     struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
 
     TTBR0_W((uint64_t)pgdir_paddr);
+    DSB();
     CLEARTLB(0);
+    ISB();
     p_icache_done->invalidateall();
     p_dcache_done->flushall();
 }

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/pagetable_attr.c

@@ -52,22 +52,26 @@ Modification:
 
 void GetUsrPteAttr(uintptr_t* attr)
 {
-    *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
+    // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
+    *attr = 0x713 | ARMV8_PTE_AP_U;
 }
 
 void GetUsrDevPteAttr(uintptr_t* attr)
 {
-    *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
+    // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
+    *attr = 0x403 | ARMV8_PTE_AP_U;
 }
 
 void GetDevPteAttr(uintptr_t* attr)
 {
-    *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
+    // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID;
+    *attr = 0x403ULL;
 }
 
 void GetKernPteAttr(uintptr_t* attr)
 {
-    *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
+    // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID;
+    *attr = 0x713ULL;
 }
 
 void GetPdeAttr(uintptr_t* attr)

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/Makefile

@@ -1,5 +1,5 @@
 # The following three platforms support compatiable instructions.
-ifneq ($(findstring $(BOARD), ok1028a-c), )
+ifneq ($(findstring $(BOARD), 3568), )
 SRC_DIR := armv8-a
 endif
 ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/Makefile

@@ -1,4 +1,4 @@
 # The following three platforms support compatiable instructions.
-SRC_DIR := cortex-a72
+SRC_DIR := cortex-a55
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/Makefile

@@ -1,3 +1,3 @@
-SRC_FILES := l1_cache.c
+SRC_FILES := uart.c ns16550.c
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/include/ns16550.h

@@ -0,0 +1,198 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * added support for port on 64-bit bus
+ * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
+ */
+
+/*
+ * Note that the following macro magic uses the fact that the compiler
+ * will not allocate storage for arrays of size 0
+ */
+
+#include <stdint.h>
+
+/*
+ * For driver model we always use one byte per register, and sort out the
+ * differences in the driver
+ */
+#define CONFIG_SYS_NS16550_REG_SIZE (-1)
+
+#define UART_REG(x)  \
+    unsigned char x; \
+    unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
+
+/**
+ * struct ns16550_platdata - information about a NS16550 port
+ *
+ * @base:		Base register address
+ * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
+ * @clock:		UART base clock speed in Hz
+ */
+struct ns16550_platdata {
+    unsigned long base;
+    int reg_shift;
+    int clock;
+    int reg_offset;
+    uint32_t fcr;
+};
+
+struct udevice;
+
+struct NS16550 {
+    UART_REG(rbr); /* 0 */
+    UART_REG(ier); /* 1 */
+    UART_REG(fcr); /* 2 */
+    UART_REG(lcr); /* 3 */
+    UART_REG(mcr); /* 4 */
+    UART_REG(lsr); /* 5 */
+    UART_REG(msr); /* 6 */
+    UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+    UART_REG(reg8); /* 8 */
+    UART_REG(reg9); /* 9 */
+    UART_REG(revid1); /* A */
+    UART_REG(revid2); /* B */
+    UART_REG(pwr_mgmt); /* C */
+    UART_REG(mdr1); /* D */
+#else
+    UART_REG(mdr1); /* 8 */
+    UART_REG(reg9); /* 9 */
+    UART_REG(regA); /* A */
+    UART_REG(regB); /* B */
+    UART_REG(regC); /* C */
+    UART_REG(regD); /* D */
+    UART_REG(regE); /* E */
+    UART_REG(uasr); /* F */
+    UART_REG(scr); /* 10*/
+    UART_REG(ssr); /* 11*/
+#endif
+#ifdef CONFIG_DM_SERIAL
+    struct ns16550_platdata* plat;
+#endif
+};
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+typedef struct NS16550* NS16550_t;
+
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME 0x10
+
+/* Clear & enable FIFOs */
+#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR 0x01 /* DTR   */
+#define UART_MCR_RTS 0x02 /* RTS   */
+#define UART_MCR_OUT1 0x04 /* Out 1 */
+#define UART_MCR_OUT2 0x08 /* Out 2 */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
+
+#define UART_MCR_DMA_EN 0x04
+#define UART_MCR_TX_DFR 0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define UART_LCR_PEN 0x08 /* Parity eneble */
+#define UART_LCR_EPS 0x10 /* Even Parity Select */
+#define UART_LCR_STKP 0x20 /* Stick Parity */
+#define UART_LCR_SBRK 0x40 /* Set Break */
+#define UART_LCR_BKSE 0x80 /* Bank select enable */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR 0x01 /* Data ready */
+#define UART_LSR_OE 0x02 /* Overrun */
+#define UART_LSR_PE 0x04 /* Parity error */
+#define UART_LSR_FE 0x08 /* Framing error */
+#define UART_LSR_BI 0x10 /* Break */
+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define UART_LSR_TEMT 0x40 /* Xmitter empty */
+#define UART_LSR_ERR 0x80 /* Error */
+
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+/* useful defaults for LCR */
+#define UART_LCR_8N1 0x03
+
+void NS16550_init(NS16550_t com_port, int baud_divisor);
+void NS16550_putc(NS16550_t com_port, char c);
+char NS16550_getc(NS16550_t com_port);
+int NS16550_tstc(NS16550_t com_port);
+void NS16550_reinit(NS16550_t com_port, int baud_divisor);
+
+void _debug_uart_init(void);
+void _debug_uart_putc(int ch);
+int _debug_uart_getc(void);

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/ns16550.c

@@ -0,0 +1,103 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
+ */
+
+#include <stdint.h>
+
+#include "mmio_access.h"
+#include "ns16550.h"
+
+#define UART_ADDR MMIO_P2V_WO(0xFE660000)
+// #define UART_ADDR (0xFE660000)
+
+#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
+#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
+
+#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v))
+#define in_le32(a) (*(volatile uint32_t*)(a))
+
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER 0x00
+#endif /* CONFIG_SYS_NS16550_IER */
+
+#define serial_dout(reg, value)                                                   \
+    serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
+        2, value)
+#define serial_din(reg)                                                          \
+    serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
+        2)
+
+static inline void serial_out_shift(void* addr, int shift, int value)
+{
+    out_le32(addr, value);
+}
+
+static inline int serial_in_shift(void* addr, int shift)
+{
+    return in_le32(addr);
+}
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
+#define DIV_ROUND_CLOSEST(x, divisor) (                                                                                                      \
+    {                                                                                                                                        \
+        typeof(x) __x = x;                                                                                                                   \
+        typeof(divisor) __d = divisor;                                                                                                       \
+        (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \
+    })
+
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
+{
+    const unsigned int mode_x_div = 16;
+
+    return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
+}
+
+void _debug_uart_init(void)
+{
+    struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    /*
+     * We copy the code from above because it is already horribly messy.
+     * Trying to refactor to nicely remove the duplication doesn't seem
+     * feasible. The better fix is to move all users of this driver to
+     * driver model.
+     */
+    int baud_divisor = ns16550_calc_divisor(com_port, 24000000,
+        1500000);
+    serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
+    serial_dout(&com_port->mcr, UART_MCRVAL);
+    serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
+
+    serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
+    serial_dout(&com_port->dll, baud_divisor & 0xff);
+    serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
+    serial_dout(&com_port->lcr, UART_LCRVAL);
+}
+
+void _debug_uart_putc(int ch)
+{
+    static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    if (ch == '\n') {
+        _debug_uart_putc('\r');
+    }
+
+    while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
+        ;
+    serial_dout(&com_port->thr, ch);
+}
+
+int _debug_uart_getc(void)
+{
+    static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    while (!(serial_din(&com_port->lsr) & UART_LSR_DR))
+        ;
+
+    return serial_din(&com_port->rbr);
+}

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c

@@ -0,0 +1,45 @@
+//
+// low-level driver routines for pl011 UART.
+//
+
+#include "uart.h"
+#include "actracer.h"
+#include "ns16550.h"
+#include "uart_common_ope.h"
+
+// the UART control registers are memory-mapped
+// at address UART0. this macro returns the
+// address of one of the registers.
+
+void uartinit(void)
+{
+    _debug_uart_init();
+}
+
+void uartputc(uint8_t c)
+{
+    _debug_uart_putc((int)c);
+}
+
+static uint8_t uartgetc(void)
+{
+    return (uint8_t)_debug_uart_getc();
+}
+
+static uint32_t UartGetIrqnum()
+{
+    return 0;
+}
+
+static struct XiziSerialDriver hardkernel_serial_driver = {
+    .sys_serial_init = uartinit,
+    .get_serial_irqnum = UartGetIrqnum,
+    .putc = uartputc,
+    .getc = uartgetc,
+};
+
+struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
+{
+    hardkernel_serial_driver.sys_serial_init();
+    return &hardkernel_serial_driver;
+}

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/uart.c

@@ -1,128 +0,0 @@
-//
-// low-level driver routines for pl011 UART.
-//
-
-#include "uart.h"
-#include "actracer.h"
-#include "uart_common_ope.h"
-
-// the UART control registers are memory-mapped
-// at address UART0. this macro returns the
-// address of one of the registers.
-
-// the transmit output buffer.
-#define UART_TX_BUF_SIZE 32
-static char uart_tx_buf[UART_TX_BUF_SIZE];
-uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
-uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
-
-void uartinit(void)
-{
-    // disable uart
-    UART_WRITE_REG(CR, 0);
-
-    // disable interrupts.
-    UART_WRITE_REG(IMSC, 0);
-
-    // in qemu, it is not necessary to set baudrate.
-    // enable FIFOs.
-    // set word length to 8 bits, no parity.
-    UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
-
-    // enable RXE, TXE and enable uart.
-    UART_WRITE_REG(CR, 0x301);
-
-    // enable transmit and receive interrupts.
-    UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
-}
-
-// if the UART is idle, and a character is waiting
-// in the transmit buffer, send it.
-// caller must hold uart_tx_lock.
-// called from both the top- and bottom-half.
-void uartstart()
-{
-    while (1) {
-        if (uart_tx_w == uart_tx_r) {
-            // transmit buffer is empty.
-            return;
-        }
-
-        if (UART_READ_REG(FR) & FR_TXFF) {
-            // the UART transmit holding register is full,
-            // so we cannot give it another byte.
-            // it will interrupt when it's ready for a new byte.
-            return;
-        }
-
-        int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
-        uart_tx_r += 1;
-
-        // maybe uartputc() is waiting for space in the buffer.
-
-        UART_WRITE_REG(DR, c);
-    }
-}
-
-// add a character to the output buffer and tell the
-// UART to start sending if it isn't already.
-// blocks if the output buffer is full.
-// because it may block, it can't be called
-// from interrupts; it's only suitable for use
-// by write().
-void uartputc(uint8_t c)
-{
-    while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
-        ;
-    uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
-    uart_tx_w += 1;
-    uartstart();
-    return;
-}
-
-// read one input character from the UART.
-// return -1 if none is waiting.
-static uint8_t uartgetc(void)
-{
-    if (UART_READ_REG(FR) & FR_RXFE)
-        return 0xFF;
-    else
-        return UART_READ_REG(DR);
-}
-
-// handle a uart interrupt, raised because input has
-// arrived, or the uart is ready for more output, or
-// both. called from trap.c.
-void uartintr(void)
-{
-    // read and process incoming characters.
-    while (1) {
-        int c = uartgetc();
-        if (c == 0xFF)
-            break;
-    }
-
-    // send buffered characters.
-    uartstart();
-
-    // clear transmit and receive interrupts.
-    UART_WRITE_REG(ICR, INT_RX_ENABLE | INT_TX_ENABLE);
-}
-
-static uint32_t UartGetIrqnum()
-{
-    return 0;
-}
-
-static struct XiziSerialDriver hardkernel_serial_driver = {
-    .sys_serial_init = uartinit,
-    .get_serial_irqnum = UartGetIrqnum,
-    .putc = uartputc,
-    .getc = uartgetc,
-};
-
-struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
-{
-    hardkernel_serial_driver.sys_serial_init();
-    return &hardkernel_serial_driver;
-}

Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c

@@ -147,7 +147,7 @@ void* AchieveResource(TraceTag* tag)
 
 bool CreateResourceTag(TraceTag* new_tag, TraceTag* owner, char* name, tracemeta_ac_type type, void* p_resource)
 {
-    assert(new_tag != NULL && owner != NULL);
+    assert(owner != NULL);
     if (owner->meta == NULL) {
         ERROR("Tracer: Empty owner\n");
         return false;
@@ -168,7 +168,9 @@ bool CreateResourceTag(TraceTag* new_tag, TraceTag* owner, char* name, tracemeta
     doubleListAddOnHead(&new_node->list_node, &owner->meta->children_guard);
     new_node->parent = owner->meta;
 
-    new_tag->meta = new_node;
+    if (new_tag != NULL) {
+        new_tag->meta = new_node;
+    }
     return true;
 }
 
@@ -187,12 +189,42 @@ bool DeleteResource(TraceTag* target, TraceTag* owner)
     if (target->meta->name != NULL) {
         slab_free(&sys_tracer.node_name_allocator, target->meta->name);
     }
+
     // delete all children
-    /// @attention currently donot allow multilevel resource deletion
     if (target->meta->type == TRACER_OWNER) {
-        assert(IS_DOUBLE_LIST_EMPTY(&target->meta->children_guard));
+        while (!IS_DOUBLE_LIST_EMPTY(&target->meta->children_guard)) {
+            TraceTag tmp_node = {
+                .meta = DOUBLE_LIST_ENTRY(target->meta->children_guard.next, TracerNode, list_node),
+            };
+            DeleteResource(&tmp_node, target);
+        }
     }
     slab_free(&sys_tracer.node_allocator, target->meta);
     target->meta = NULL;
     return true;
+}
+
+void debug_list_tracetree_inner(TracerNode* cur_node)
+{
+    DEBUG("[%s] ", cur_node->name);
+    TracerNode* tmp = NULL;
+    DOUBLE_LIST_FOR_EACH_ENTRY(tmp, &cur_node->children_guard, list_node)
+    {
+        if (tmp->name != NULL) {
+            DEBUG("%s ", tmp->name);
+        } else {
+            DEBUG("ANON ");
+        }
+    }
+    DEBUG("\n");
+    DOUBLE_LIST_FOR_EACH_ENTRY(tmp, &cur_node->children_guard, list_node)
+    {
+        debug_list_tracetree_inner(tmp);
+    }
+}
+
+void debug_list_tracetree()
+{
+    TracerNode* ref_root = RequireRootTag()->meta;
+    debug_list_tracetree_inner(ref_root);
 }

Ubiquitous/XiZi_AIoT/path_kernel.mk

@@ -38,20 +38,20 @@ KERNELPATHS += \
 	-I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/ 
 endif
 
-ifeq ($(BOARD), ok1028a-c)
+ifeq ($(BOARD), 3568)
 KERNELPATHS += \
-	-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a72/$(BOARD)/include \
-	-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/include \
-	-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/ \
-	-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/$(BOARD)  \
-	-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/include  \
-	-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a72/include  \
-	-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/ \
-	-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/$(BOARD) \
-	-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3 \
-	-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_$(BOARD)/include \
-	-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a72/ \
-	-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a72/ 
+	-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a55/$(BOARD)/include \
+	-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/include \
+	-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/ \
+	-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a55/$(BOARD)  \
+	-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a55/include  \
+	-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv8-a/cortex-a55/include  \
+	-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/ \
+	-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/$(BOARD) \
+	-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a55/gicv3 \
+	-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_$(BOARD)/include \
+	-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv8-a/cortex-a55/ \
+	-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a55/ 
 endif
 
 KERNELPATHS += \

Ubiquitous/XiZi_AIoT/services/Makefile

@@ -1,4 +1,5 @@
-SRC_DIR := fs shell lib boards semaphore drivers tools app 
+
+SRC_DIR := fs shell lib boards semaphore drivers tools net app 
 
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/services/app/Makefile

@@ -10,10 +10,10 @@ cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -
 board_specs = stub.o
 #cflags = -Wall -g -std=c11 
 endif
-ifeq ($(BOARD), ok1028a-c)
+ifeq ($(BOARD), 3568)
 toolchain ?= aarch64-none-elf-
 user_ldflags = -N -Ttext 0
-cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie  
+cflags = -Wall -O2 -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 board_specs = stub.o
 endif
 
@@ -28,14 +28,24 @@ INC_DIR = 	-I$(KERNEL_ROOT)/services/shell/letter-shell \
 			-I$(KERNEL_ROOT)/services/lib/serial \
 			-I$(KERNEL_ROOT)/services/lib/usyscall \
 			-I$(KERNEL_ROOT)/services/fs/libfs \
+			-I$(KERNEL_ROOT)/services/net/libnet \
+			-I$(KERNEL_ROOT)/services/net/net_server \
+			-I$(KERNEL_ROOT)/services/net/net_server/arch \
+			-I$(KERNEL_ROOT)/services/net/net_server/include \
+			-I$(KERNEL_ROOT)/services/net/net_server/include/lwip \
+			-I$(KERNEL_ROOT)/services/net/net_server/include/lwip/apps \
+			-I$(KERNEL_ROOT)/services/net/net_server/include/lwip/priv \
+			-I$(KERNEL_ROOT)/services/net/net_server/include/lwip/prot \
+			-I$(KERNEL_ROOT)/services/net/net_server/include/netif \
+			-I$(KERNEL_ROOT)/services/net/net_server/include/compat \
 			-I$(KERNEL_ROOT)/services/semaphore \
 			-I$(KERNEL_ROOT)/services/boards/$(BOARD) \
 			-I$(KERNEL_ROOT)/services/app 
 
 ifeq ($(BOARD), imx6q-sabrelite)
-all: init test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server readme.txt | bin
+all: test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip  readme.txt | bin
 else 
-all: init test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore readme.txt | bin
+all: test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal usb_driver_service | bin
 endif
 	../tools/mkfs/mkfs ./fs.img $^
 	@mv $(filter-out readme.txt, $^) bin
@@ -87,10 +97,6 @@ shell: shell_port.o libserial.o printf.o shell_cmd_list.o shell.o shell_ext.o li
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm
 	
-init: init.o libfs.o libipc.o session.o libserial.o printf.o usyscall.o arch_usyscall.o libmem.o
-	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
-	@${objdump} -S $@ > $@.asm
-
 test_fault: test_fault.o libserial.o printf.o usyscall.o arch_usyscall.o 
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm
@@ -111,8 +117,16 @@ test_priority: test_priority.o libserial.o printf.o usyscall.o arch_usyscall.o l
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm
 
+test_net: test_net.o lwip_service.o libipc.o session.o libserial.o printf.o usyscall.o arch_usyscall.o libmem.o
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} -llwip -L$(KERNEL_ROOT)/services/net/net_server
+	@${objdump} -S $@ > $@.asm
+
 %.o: %.c
 	@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $< 
 
 %.o: %.S
-	@${cc} ${cflags} ${c_useropts} -o $@ -c $< 
+	@${cc} ${cflags} ${c_useropts} -o $@ -c $< 
+
+eth_hal: test_gmac.o hal_gmac.o hal_gmac_3568.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_gpio.o hal_timer.o hal_cru_rk3568.o system_rk3568.o hal_debug.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o 
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+	@${objdump} -S $@ > $@.asm

Ubiquitous/XiZi_AIoT/services/app/init.c

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2020 AIIT XUOS Lab
- * XiUOS is licensed under Mulan PSL v2.
- * You can use this software according to the terms and conditions of the Mulan PSL v2.
- * You may obtain a copy of Mulan PSL v2 at:
- *        http://license.coscl.org.cn/MulanPSL2
- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
- * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
- * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
- * See the Mulan PSL v2 for more details.
- */
-// init: The initial user-level program
-#include <stdbool.h>
-
-#include "libfs.h"
-#include "libserial.h"
-#include "usyscall.h"
-
-int main(int argc, char* argv[])
-{
-    struct Session session;
-    printf("init: connecting MemFS\n");
-    while (connect_session(&session, "MemFS", 8092) < 0)
-        ;
-    printf("init: connect MemFS success\n");
-
-    int fd;
-    char* shell_task_param[2] = { "/shell", 0 };
-    if ((fd = open(&session, shell_task_param[0])) < 0) {
-        printf("Open %s failed\n", shell_task_param[0]);
-        exit(1);
-    }
-
-    if (spawn(&session, fd, read, fsize, shell_task_param[0], shell_task_param) < 0) {
-        printf("Syscall Spawn shell failed\n");
-    }
-
-    close(&session, fd);
-
-    exit(0);
-    return 0;
-}

Ubiquitous/XiZi_AIoT/services/app/shell_port.c

@@ -50,7 +50,7 @@ int main(void)
 
     shellInit(&shell, shellBuffer, 512);
 
-    while (connect_session(&session_fs, "MemFS", 8092) < 0)
+    while (connect_session(&session_fs, "MemFS", 0x10000) < 0)
         ;
     if (!session_fs.buf) {
         printf("session connect faield\n");

Ubiquitous/XiZi_AIoT/services/app/simple_client.c

@@ -108,7 +108,7 @@ int main(int argc, char** argv)
     struct Session fs_session;
     static char id_buf[33] = { 0 };
     if (id > 1) {
-        if (connect_session(&fs_session, "MemFS", 8192) < 0) {
+        if (connect_session(&fs_session, "MemFS", 0x4000) < 0) {
             printf("connect fs_session failed\n");
         } else {
             int fd;

Ubiquitous/XiZi_AIoT/services/app/simple_server.c

@@ -30,8 +30,7 @@ int IPC_DO_SERVE_FUNC(Ipc_hello_string)(char* buf, int* len)
     return 0;
 }
 
-// IPC_SERVER_INTERFACE(Ipc_add, 2);
-IPC_SERVER_THREAD_INTERFACE(Ipc_add, 2);
+IPC_SERVER_INTERFACE(Ipc_add, 2);
 IPC_SERVER_INTERFACE(Ipc_hello_string, 2);
 IPC_SERVER_REGISTER_INTERFACES(IpcSimpleServer, 2, Ipc_hello_string, Ipc_add);
 

Ubiquitous/XiZi_AIoT/services/app/test_net.c

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+// test_net: Test the lwip network stack
+
+#include "libserial.h"
+#include "lwip_service.h"
+#include "usyscall.h"
+
+static char udp_ip_str[128] = {0};
+static uint16_t udp_socket_port = 8888;
+#define UDP_DEMO_SEND_TIMES      3
+
+int main(int argc, char* argv[])
+{
+    printf("lwip network stack test \n");
+
+    
+    int cnt = UDP_DEMO_SEND_TIMES;
+    char send_str[128];
+    int fd = -1;
+
+    memset(send_str, 0, sizeof(send_str));
+    struct Session sess;
+    connect_session(&sess, "LWIPServer", 4096);
+
+    printf("%s %d\n", __func__, __LINE__);
+
+    fd = ipc_socket(&sess, AF_INET, SOCK_DGRAM, 0);
+    if(fd < 0) {
+        printf("Socket error\n");
+        return 0;
+    }
+
+    printf("%s %d\n", __func__, __LINE__);
+
+    struct sockaddr_in udp_sock;
+    udp_sock.sin_family = AF_INET;
+    udp_sock.sin_port = htons(udp_socket_port);
+    udp_sock.sin_addr.s_addr = inet_addr(udp_ip_str);
+    memset(&(udp_sock.sin_zero), 0, sizeof(udp_sock.sin_zero));
+
+    printf("%s %d\n", __func__, __LINE__);
+    
+    if(ipc_connect(&sess, fd, (struct sockaddr *)&udp_sock, sizeof(struct sockaddr)) < 0) {
+        printf("Unable to connect %s:%d\n", udp_ip_str, udp_socket_port);
+        ipc_close(&sess,fd);
+        return 0;
+    }
+
+    printf("%s %d\n", __func__, __LINE__);
+
+    printf("UDP connect %s:%d success, start to send.\n",
+        udp_ip_str,
+        udp_socket_port);
+
+    while(cnt --) {
+        snprintf(send_str, sizeof(send_str), "UDP test package times %d\r\n", cnt);
+        ipc_send(&sess, fd, send_str, strlen(send_str), 0);
+        printf("Send UDP msg: %s ", send_str);
+    }
+
+    ipc_close(&sess,fd);
+    
+    free_session(&sess);
+
+    exit(0);
+    return 0;
+}

Ubiquitous/XiZi_AIoT/services/boards/3568/Makefile

@@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi-
 user_ldflags = -N -Ttext 0
 cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 endif
-ifeq ($(BOARD), ok1028a-c)
+ifeq ($(BOARD), 3568)
 toolchain ?= aarch64-none-elf-
 user_ldflags = -N -Ttext 0
-cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie  
+cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 endif
 
 cc = ${toolchain}gcc

Ubiquitous/XiZi_AIoT/services/boards/3568/libserial.c

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/// this file is only used for debug
+#include <stddef.h>
+#include <stdint.h>
+
+#include "libserial.h"
+#include "usyscall.h"
+
+/*
+ * For driver model we always use one byte per register, and sort out the
+ * differences in the driver
+ */
+#define CONFIG_SYS_NS16550_REG_SIZE (-1)
+
+#define UART_REG(x)  \
+    unsigned char x; \
+    unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
+
+/**
+ * struct ns16550_platdata - information about a NS16550 port
+ *
+ * @base:		Base register address
+ * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
+ * @clock:		UART base clock speed in Hz
+ */
+struct ns16550_platdata {
+    unsigned long base;
+    int reg_shift;
+    int clock;
+    int reg_offset;
+    uint32_t fcr;
+};
+
+struct udevice;
+
+struct NS16550 {
+    UART_REG(rbr); /* 0 */
+    UART_REG(ier); /* 1 */
+    UART_REG(fcr); /* 2 */
+    UART_REG(lcr); /* 3 */
+    UART_REG(mcr); /* 4 */
+    UART_REG(lsr); /* 5 */
+    UART_REG(msr); /* 6 */
+    UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+    UART_REG(reg8); /* 8 */
+    UART_REG(reg9); /* 9 */
+    UART_REG(revid1); /* A */
+    UART_REG(revid2); /* B */
+    UART_REG(pwr_mgmt); /* C */
+    UART_REG(mdr1); /* D */
+#else
+    UART_REG(mdr1); /* 8 */
+    UART_REG(reg9); /* 9 */
+    UART_REG(regA); /* A */
+    UART_REG(regB); /* B */
+    UART_REG(regC); /* C */
+    UART_REG(regD); /* D */
+    UART_REG(regE); /* E */
+    UART_REG(uasr); /* F */
+    UART_REG(scr); /* 10*/
+    UART_REG(ssr); /* 11*/
+#endif
+#ifdef CONFIG_DM_SERIAL
+    struct ns16550_platdata* plat;
+#endif
+};
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+typedef struct NS16550* NS16550_t;
+
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME 0x10
+
+/* Clear & enable FIFOs */
+#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR 0x01 /* DTR   */
+#define UART_MCR_RTS 0x02 /* RTS   */
+#define UART_MCR_OUT1 0x04 /* Out 1 */
+#define UART_MCR_OUT2 0x08 /* Out 2 */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
+
+#define UART_MCR_DMA_EN 0x04
+#define UART_MCR_TX_DFR 0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define UART_LCR_PEN 0x08 /* Parity eneble */
+#define UART_LCR_EPS 0x10 /* Even Parity Select */
+#define UART_LCR_STKP 0x20 /* Stick Parity */
+#define UART_LCR_SBRK 0x40 /* Set Break */
+#define UART_LCR_BKSE 0x80 /* Bank select enable */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR 0x01 /* Data ready */
+#define UART_LSR_OE 0x02 /* Overrun */
+#define UART_LSR_PE 0x04 /* Parity error */
+#define UART_LSR_FE 0x08 /* Framing error */
+#define UART_LSR_BI 0x10 /* Break */
+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define UART_LSR_TEMT 0x40 /* Xmitter empty */
+#define UART_LSR_ERR 0x80 /* Error */
+
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+/* useful defaults for LCR */
+#define UART_LCR_8N1 0x03
+
+#define UART_ADDR (0xFE660000)
+
+#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
+#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
+
+#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v))
+#define in_le32(a) (*(volatile uint32_t*)(a))
+
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER 0x00
+#endif /* CONFIG_SYS_NS16550_IER */
+
+#define serial_dout(reg, value)                                                   \
+    serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
+        2, value)
+#define serial_din(reg)                                                          \
+    serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
+        2)
+
+static inline void serial_out_shift(void* addr, int shift, int value)
+{
+    out_le32(addr, value);
+}
+
+static inline int serial_in_shift(void* addr, int shift)
+{
+    return in_le32(addr);
+}
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
+bool init_uart_mmio()
+{
+    static int mapped = 0;
+    if (mapped == 0) {
+        if (-1 == mmap(UART_ADDR, UART_ADDR, 4096, true)) {
+            return false;
+        }
+        mapped = 1;
+    }
+    return true;
+}
+
+void putc(char ch)
+{
+    static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    if (ch == '\n') {
+        putc('\r');
+    }
+
+    while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
+        ;
+    serial_dout(&com_port->thr, ch);
+}
+
+char getc(void)
+{
+    static struct NS16550* com_port = (struct NS16550*)UART_ADDR;
+
+    while (!(serial_din(&com_port->lsr) & UART_LSR_DR))
+        ;
+
+    return serial_din(&com_port->rbr);
+}

Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile

@@ -8,10 +8,10 @@ toolchain ?= arm-xilinx-eabi-
 user_ldflags = -N -Ttext 0
 cflags = -march=armv7-a -std=c11 -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 endif
-ifeq ($(BOARD), ok1028a-c)
+ifeq ($(BOARD), 3568)
 toolchain ?= aarch64-none-elf-
 user_ldflags = -N -Ttext 0
-cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie  
+cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 endif
 
 cc = ${toolchain}gcc

Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/libserial.c

@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2020 AIIT XUOS Lab
- * XiUOS is licensed under Mulan PSL v2.
- * You can use this software according to the terms and conditions of the Mulan PSL v2.
- * You may obtain a copy of Mulan PSL v2 at:
- *        http://license.coscl.org.cn/MulanPSL2
- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
- * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
- * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
- * See the Mulan PSL v2 for more details.
- */
-
-/// this file is only used for debug
-#include "libserial.h"
-#include "usyscall.h"
-
-#define USER_UART_BASE 0x6FFFF000
-
-#define UART0_BASE (0x09000000ULL)
-#define UART0_REG(reg) ((volatile uint32_t*)(USER_UART_BASE + reg))
-
-// the UART control registers.
-// pl011
-#define DR 0x00
-#define FR 0x18
-#define FR_RXFE (1 << 4) // recieve fifo empty
-#define FR_TXFF (1 << 5) // transmit fifo full
-#define FR_RXFF (1 << 6) // recieve fifo full
-#define FR_TXFE (1 << 7) // transmit fifo empty
-#define IBRD 0x24
-#define FBRD 0x28
-#define LCRH 0x2c
-#define LCRH_FEN (1 << 4)
-#define LCRH_WLEN_8BIT (3 << 5)
-#define CR 0x30
-#define IMSC 0x38
-#define INT_RX_ENABLE (1 << 4)
-#define INT_TX_ENABLE (1 << 5)
-#define ICR 0x44
-
-#define UART_READ_REG(reg) (*(UART0_REG(reg)))
-#define UART_WRITE_REG(reg, v) (*(UART0_REG(reg)) = (v))
-
-#define UART_TX_BUF_SIZE 32
-static char uart_tx_buf[UART_TX_BUF_SIZE];
-uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
-uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
-
-bool init_uart_mmio()
-{
-    static int mapped = 0;
-    if (mapped == 0) {
-        if (-1 == mmap(USER_UART_BASE, UART0_BASE, 4096, true)) {
-            return false;
-        }
-        mapped = 1;
-    }
-    return true;
-}
-
-// if the UART is idle, and a character is waiting
-// in the transmit buffer, send it.
-// caller must hold uart_tx_lock.
-// called from both the top- and bottom-half.
-void uartstart()
-{
-    while (1) {
-        if (uart_tx_w == uart_tx_r) {
-            // transmit buffer is empty.
-            return;
-        }
-
-        if (UART_READ_REG(FR) & FR_TXFF) {
-            // the UART transmit holding register is full,
-            // so we cannot give it another byte.
-            // it will interrupt when it's ready for a new byte.
-            return;
-        }
-
-        int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
-        uart_tx_r += 1;
-
-        // maybe uartputc() is waiting for space in the buffer.
-
-        UART_WRITE_REG(DR, c);
-    }
-}
-
-// add a character to the output buffer and tell the
-// UART to start sending if it isn't already.
-// blocks if the output buffer is full.
-// because it may block, it can't be called
-// from interrupts; it's only suitable for use
-// by write().
-void putc(char c)
-{
-    while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
-        ;
-    uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
-    uart_tx_w += 1;
-    uartstart();
-    return;
-}
-
-// read one input character from the UART.
-// return -1 if none is waiting.
-char getc(void)
-{
-    if (UART_READ_REG(FR) & FR_RXFE)
-        return 0xFF;
-    else
-        return UART_READ_REG(DR);
-}

Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile

@@ -9,10 +9,10 @@ user_ldflags = --start-group,-lgcc,-lc,--end-group
 cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 #cflags = -Wall -g -std=c11 
 endif
-ifeq ($(BOARD), ok1028a-c)
+ifeq ($(BOARD), 3568)
 toolchain ?= aarch64-none-elf-
 user_ldflags = -N -Ttext 0
-cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie  
+cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
 endif
 
 cc = ${toolchain}gcc

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/Makefile

@@ -1,3 +1,4 @@
-SRC_DIR := 
+
+SRC_DIR := hal
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/Makefile

@@ -0,0 +1,62 @@
+ifeq ($(BOARD), imx6q-sabrelite)
+toolchain ?= arm-none-eabi-
+user_ldflags = --specs=nosys.specs -Wl,-Map=user.map,-cref -N
+cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+endif
+
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = -Wl,--start-group,-lgcc,-lc,--end-group -N
+cflags = -std=c11 -O2 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+board_specs = stub.o
+#cflags = -Wall -g -std=c11 
+endif
+
+ifeq ($(BOARD), ok1028a-c)
+toolchain ?= aarch64-none-elf-
+user_ldflags = -N -Ttext 0
+cflags =  -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Werror -ggdb -Wno-unused  -fno-omit-frame-pointer -fno-stack-protector -fno-pie  
+board_specs = stub.o
+endif
+
+ifeq ($(BOARD), 3568)
+toolchain ?= aarch64-none-elf-
+user_ldflags = -N -Ttext 0
+cflags = -Wall -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie  
+board_specs = $(KERNEL_ROOT)/services/app/stub.o
+endif
+
+cc = ${toolchain}gcc
+ld = ${toolchain}g++
+objdump = ${toolchain}objdump
+c_useropts = -O2
+# c_useropts = -O0
+
+INC_DIR = 	-I$(KERNEL_ROOT)/services/app \
+		  	-I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+			-I$(KERNEL_ROOT)/services/lib/serial \
+			-I$(KERNEL_ROOT)/services/drivers/3568/include \
+			-I$(KERNEL_ROOT)/services/lib/usyscall \
+		  	-I$(KERNEL_ROOT)/services/lib/ipc \
+		  	-I$(KERNEL_ROOT)/services/lib/memory 
+
+
+objs =  hal_gmac.o \
+		hal_gmac_3568.o \
+		test_gmac.o \
+		hal_base.o \
+		hal_bsp.o \
+		hal_pinctrl_v2.o \
+		hal_cru.o \
+		hal_gpio.o \
+		hal_timer.o \
+		hal_cru_rk3568.o \
+		hal_debug.o \
+		system_rk3568.o \
+
+all: ${objs}
+	@mv $^ $(KERNEL_ROOT)/services/app
+
+%.o: %.c
+	@echo "cc $^"
+	@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_base.c

@@ -0,0 +1,454 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup HAL_BASE
+ *  @{
+ */
+
+/** @defgroup HAL_BASE_How_To_Use How To Use
+ *  @{
+
+ HAL system support is including delay system, HAL tick system and global system clock,
+
+ HAL system tick setting:
+
+ - Attach HAL_IncTick() to system tick interrupt handler;
+ - Notify the HAL system the system's tick frequency by calling HAL_SetTickFreq() unless
+    it is the same as default value HAL_TICK_FREQ_1KHZ;
+ - If you need a more accurate delay system, specify SYS_TIMER in hal_conf.h.
+
+ Init HAL system:
+
+ - Initialize the HAL system by calling HAL_Init():
+
+ Reset when SOC system is changed:
+
+ - Update system with new core clock and new SysTick clock source by calling HAL_SystemCoreClockUpdate();
+
+ APIs:
+
+ - Get system time by calling HAL_GetTick().
+ - Delay for a certain length of time, HAL_DelayMs(), HAL_DelayUs(), and HAL_CPUDelayUs().
+ - Blocking for a certain period of time to continuously query HW status, use HAL_GetTick()
+ to do timeout, this will be more accurate.
+ - Get current cpu usage by calling HAL_GetCPUUsage().
+
+ @} */
+
+/** @defgroup HAL_BASE_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+static __IO uint32_t uwTick;
+static eHAL_tickFreq uwTickFreq = HAL_TICK_FREQ_DEFAULT;
+
+/********************* Private Function Definition ***************************/
+#if defined(__CORTEX_A) || defined(__CORTEX_M)
+#if __CORTEX_M == 0U || !defined(__GNUC__)
+static void CPUCycleLoop(uint32_t cycles)
+{
+    uint32_t count;
+
+    if (cycles < 100U) {
+        return;
+    }
+
+    count = cycles / 3;
+    while (count-- > 0) {
+        __asm volatile ("nop");
+    }
+}
+#else
+static void CPUCycleLoop(uint32_t cycles)
+{
+    __ASM volatile (
+        "mov  r0, %0\n\t"
+        "adds r0, r0, #2\n\t"   //    1    2    Round to the nearest multiple of 4.
+        "lsrs r0, r0, #2\n\t"   //    1    2    Divide by 4 and set flags.
+        "beq  2f\n\t"           //    2    2    Skip if 0.
+        ".align 4\n\t"
+        "1:\n\t"
+        "adds r0, r0, #1\n\t"   //    1    2    Increment the counter.
+        "subs r0, r0, #2\n\t"   //    1    2    Decrement the counter by 2.
+        "bne  1b\n\t"           //   (1)2  2    2 CPU cycles (if branch is taken).
+        "nop\n\t"               //    1    2    Loop alignment padding.
+        "2:"
+        : : "r" (cycles)
+        );
+}
+#endif
+#elif defined(__RISC_V)
+static void CPUCycleLoop(uint32_t cycles)
+{
+    asm volatile (
+        "mv   a0, %0\n\t"
+        "addi a0, a0, 2\n\t"   //    1    2    Round to the nearest multiple of 4.
+        "li   a1, 4\n\t"
+        "div  a0, a0, a1\n\t"  //    1    2    Divide by 4 and set flags.
+        "li   a1, 2\n\t"
+        "bnez a0, 1f\n\t"      //    2    2    Skip if 0.
+        "j    2f\n\t"
+        ".align 6\n\t"
+        "1:\n\t"
+        "addi a0, a0, 1\n\t"   //    1    2    Increment the counter.
+        "sub  a0, a0, a1\n\t"  //    1    2    Decrement the counter by 2.
+        "bnez a0, 1b\n\t"      //   (1)2  2    2 CPU cycles (if branch is taken).
+        "nop\n\t"              //    1    2    Loop alignment padding.
+        "2:"
+        : : "r" (cycles)
+        );
+}
+#endif
+
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+__attribute__((always_inline)) static inline HAL_Status TimerDelayUs(uint32_t us)
+{
+    uint64_t count, from, now, pass;
+
+    from = HAL_TIMER_GetCount(SYS_TIMER);
+    count = PLL_INPUT_OSC_RATE / 1000000 * us;
+    do {
+        now = HAL_TIMER_GetCount(SYS_TIMER);
+        pass = now > from ? now - from : from - now;
+    } while (pass < count);
+    return HAL_OK;
+}
+#endif
+
+/** @} */
+/********************* Public Function Definition ***************************/
+/** @defgroup HAL_BASE_Exported_Functions_Group4 Init and DeInit Functions
+
+ This section provides functions allowing to init and deinit the module:
+
+ *  @{
+ */
+
+/**
+ * @brief  Init HAL driver basic code.
+ * @return HAL_OK.
+ */
+HAL_Status HAL_Init(void)
+{
+#ifdef __CORTEX_M
+#ifdef HAL_NVIC_MODULE_ENABLED
+    /* Set Interrupt Group Priority */
+    HAL_NVIC_Init();
+
+    /* Set Interrupt Group Priority */
+    HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_DEFAULT);
+#endif
+#endif
+
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+    HAL_TIMER_SysTimerInit(SYS_TIMER);
+#endif
+
+#ifdef HAL_PINCTRL_MODULE_ENABLED
+    HAL_PINCTRL_Init();
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  HAL system update with new core clock and systick clock source.
+ * @param  hz: new core clock.
+ * @param  clkSource: new systick clock source.
+ * @return HAL_OK.
+ */
+HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource)
+{
+    uint32_t rate = hz;
+    HAL_Status ret = HAL_OK;
+
+#if defined(__CORTEX_M) && defined(HAL_SYSTICK_MODULE_ENABLED)
+    ret = HAL_SYSTICK_CLKSourceConfig(clkSource);
+    if (ret == HAL_OK && clkSource == HAL_SYSTICK_CLKSRC_EXT) {
+        rate = PLL_INPUT_OSC_RATE;
+    }
+    HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq()));
+    ret = HAL_OK;
+#endif
+
+    if (ret == HAL_OK) {
+        SystemCoreClock = rate;   /* Update global SystemCoreClock */
+    }
+
+    return ret;
+}
+
+/**
+ * @brief  HAL deinit.
+ * @return HAL_Status: HAL_OK.
+ */
+HAL_Status HAL_DeInit(void)
+{
+    /* TO-DO */
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Count plus tickFreq when interrupt occurs.
+ * @return HAL_Status: HAL_OK.
+ */
+HAL_Status HAL_IncTick(void)
+{
+    uwTick += uwTickFreq;
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Provides tick value in millisecond.
+ * @return uint32_t: tick value in millisecond.
+ * @attention this API allow direct use in the HAL layer.
+ */
+uint32_t HAL_GetTick(void)
+{
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+    uint64_t tick = HAL_TIMER_GetCount(SYS_TIMER);
+    uint32_t base = PLL_INPUT_OSC_RATE / 1000;
+
+    if (tick >> 62) {
+        tick = ~tick;
+    }
+
+    return (uint32_t)HAL_DivU64(tick, base);
+#else
+
+    return uwTick;
+#endif
+}
+
+/**
+ * @brief  Provides system timer count.
+ * @return uint64_t: timer count.
+ * @attention this API allow direct use in the HAL layer.
+ */
+uint64_t HAL_GetSysTimerCount(void)
+{
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+    uint64_t count = HAL_TIMER_GetCount(SYS_TIMER);
+    if (count >> 62) {
+        count = ~count;
+    }
+
+    return count;
+#else
+
+    return 0LLU;
+#endif
+}
+
+/**
+  * @brief Set new tick frequency.
+  * @return HAL_Status.
+  */
+HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq)
+{
+    HAL_ASSERT(IS_TICKFREQ(freq));
+
+    uwTickFreq = freq;
+
+    return HAL_OK;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @return uint32_t: tick period in Hz.
+  * @attention this API allow direct use in the HAL layer.
+  */
+eHAL_tickFreq HAL_GetTickFreq(void)
+{
+    return uwTickFreq;
+}
+
+/**
+ * @brief  SysTick mdelay.
+ * @param  ms: mdelay count.
+ * @return HAL_Status: HAL_OK.
+ * @attention this API allow direct use in the HAL layer. Blocking for a
+ *  certain period of time to continuously query HW status, use HAL_GetTick
+ *  to do timeout, that will be more accurate.
+ */
+__attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms)
+{
+    for (uint32_t i = 0; i < ms; i++) {
+        HAL_DelayUs(1000);
+    }
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  SysTick udelay.
+ * @param  us: udelay count.
+ * @return HAL_Status: HAL_OK.
+ * @attention this API allow direct use in the HAL layer. The longer the delay,
+ *  the more accurate. Actual delay is greater than the parameter.
+ */
+HAL_Status HAL_DelayUs(uint32_t us)
+{
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+
+    return TimerDelayUs(us);
+#else
+    return HAL_CPUDelayUs(us);
+#endif
+}
+
+/**
+ * @brief  CPU loop udelay.
+ * @param  us: udelay count.
+ * @return HAL_Status: HAL_OK.
+ * @attention this API allow direct use in the HAL layer. The longer the delay,
+ *  the more accurate. Actual delay is greater than the parameter.
+ *  During delay, CPU rate change result in delay imprecise, so call it in
+ *  following case:
+ *    1.IRQ disable
+ *    2.CRU code
+ */
+HAL_Status HAL_CPUDelayUs(uint32_t us)
+{
+    volatile uint32_t cycles;
+
+#if (__CORTEX_M == 0)
+    cycles = (uint32_t)HAL_DivU64((uint64_t)SystemCoreClock, 1000000) * us; /* Add few cycles penalty */
+#else
+    cycles = SystemCoreClock / 1000000 * us; /* Add few cycles penalty */
+#endif
+
+    CPUCycleLoop(cycles);
+
+    return HAL_OK;
+}
+
+#if defined(HAL_CPU_USAGE_ENABLED)
+static uint64_t g_last_enter_idle_time = 0;               /* Last time current CPU entered the idle state. */
+static uint64_t g_total_idle_time = 0;                    /* Total time for current CPU to enter idle state. */
+static uint64_t g_last_elapsed_time = 0;                  /* Last elapsed time for current CPU. */
+
+/**
+ * @brief  Get current CPU usage.
+ * @return 0-100
+ * @attention The cpu usage function depends on HAL_CPUEnterIdle function.
+ */
+uint32_t HAL_GetCPUUsage(void)
+{
+    uint64_t elapsed_time, active_time, current_time;
+    uint32_t usage;
+
+    current_time = HAL_GetSysTimerCount();
+    elapsed_time = current_time - g_last_elapsed_time;
+
+    /* Prevent the risk of dividing by 0 caused by repeated calls for a short time. */
+    if (!elapsed_time) {
+        return 0;
+    }
+
+    HAL_ASSERT(elapsed_time > g_total_idle_time);
+    active_time = elapsed_time - g_total_idle_time;
+    usage = (active_time * 100) / elapsed_time;
+    g_total_idle_time = 0;
+    g_last_elapsed_time = current_time;
+
+    return usage;
+}
+#endif
+
+/**
+ * @brief  CPU enter idle.
+ */
+void HAL_CPU_EnterIdle(void)
+{
+#if defined(HAL_CPU_USAGE_ENABLED)
+    uint64_t idle_time;
+
+    __disable_irq();
+    g_last_enter_idle_time = HAL_GetSysTimerCount();
+#endif
+
+    // __asm__ volatile ("wfi");
+
+#if defined(HAL_CPU_USAGE_ENABLED)
+    idle_time = HAL_GetSysTimerCount() - g_last_enter_idle_time;
+    g_total_idle_time += idle_time;
+    __enable_irq();
+#endif
+}
+
+/** @} */
+
+/** @} */
+
+/** @} */
+/********************* Public Function Definition ***************************/
+/** @defgroup HAL_BASE_EX_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  uint64_t numerator / uint32_t denominator with remainder
+ * @param  numerator
+ * @param  denominator
+ * @param  pRemainder [out] pointer to unsigned 32bit remainder
+ * @return uint64_t result. sets *pRemainder if pRemainder is not null
+ */
+uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder)
+{
+    uint64_t remainder = numerator;
+    uint64_t b = denominator;
+    uint64_t result;
+    uint64_t d = 1;
+    uint32_t high = numerator >> 32;
+
+    result = 0;
+    if (high >= denominator) {
+        high /= denominator;
+        result = (uint64_t)high << 32;
+        remainder -= (uint64_t)(high * denominator) << 32;
+    }
+
+    while ((int64_t)b > 0 && b < remainder) {
+        b = b + b;
+        d = d + d;
+    }
+
+    do {
+        if (remainder >= b) {
+            remainder -= b;
+            result += d;
+        }
+        b >>= 1;
+        d >>= 1;
+    } while (d);
+
+    if (pRemainder) {
+        *pRemainder = remainder;
+    }
+
+    return result;
+}

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_bsp.c

@@ -0,0 +1,420 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_bsp.h"
+
+#ifdef HAL_PL330_MODULE_ENABLED
+struct HAL_PL330_DEV g_pl330Dev0 =
+{
+    .pReg = DMA0,
+    .peripReqType = BURST,
+    .irq[0] = DMAC0_IRQn,
+    .irq[1] = DMAC0_ABORT_IRQn,
+    .pd = 0,
+};
+
+struct HAL_PL330_DEV g_pl330Dev1 =
+{
+    .pReg = DMA1,
+    .peripReqType = BURST,
+    .irq[0] = DMAC1_IRQn,
+    .irq[1] = DMAC1_ABORT_IRQn,
+    .pd = 0,
+};
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+const struct HAL_SPI_DEV g_spi0Dev = {
+    .base = SPI0_BASE,
+    .clkId = CLK_SPI0,
+    .clkGateID = CLK_SPI0_GATE,
+    .pclkGateID = PCLK_SPI0_GATE,
+    .irqNum = SPI0_IRQn,
+    .isSlave = false,
+    .txDma = {
+        .channel = DMA_REQ_SPI0_TX,
+        .direction = DMA_MEM_TO_DEV,
+        .addr = SPI0_BASE + 0x400,
+        .dmac = DMA0,
+    },
+    .rxDma = {
+        .channel = DMA_REQ_SPI0_RX,
+        .direction = DMA_DEV_TO_MEM,
+        .addr = SPI0_BASE + 0x800,
+        .dmac = DMA0,
+    },
+};
+
+const struct HAL_SPI_DEV g_spi1Dev = {
+    .base = SPI1_BASE,
+    .clkId = CLK_SPI1,
+    .clkGateID = CLK_SPI1_GATE,
+    .pclkGateID = PCLK_SPI1_GATE,
+    .irqNum = SPI1_IRQn,
+    .isSlave = false,
+    .txDma = {
+        .channel = DMA_REQ_SPI1_TX,
+        .direction = DMA_MEM_TO_DEV,
+        .addr = SPI1_BASE + 0x400,
+        .dmac = DMA0,
+    },
+    .rxDma = {
+        .channel = DMA_REQ_SPI1_RX,
+        .direction = DMA_DEV_TO_MEM,
+        .addr = SPI1_BASE + 0x800,
+        .dmac = DMA0,
+    },
+};
+
+const struct HAL_SPI_DEV g_spi2Dev = {
+    .base = SPI2_BASE,
+    .clkId = CLK_SPI2,
+    .clkGateID = CLK_SPI2_GATE,
+    .pclkGateID = PCLK_SPI2_GATE,
+    .irqNum = SPI2_IRQn,
+    .isSlave = false,
+    .txDma = {
+        .channel = DMA_REQ_SPI2_TX,
+        .direction = DMA_MEM_TO_DEV,
+        .addr = SPI2_BASE + 0x400,
+        .dmac = DMA0,
+    },
+    .rxDma = {
+        .channel = DMA_REQ_SPI2_RX,
+        .direction = DMA_DEV_TO_MEM,
+        .addr = SPI2_BASE + 0x800,
+        .dmac = DMA0,
+    },
+};
+
+const struct HAL_SPI_DEV g_spi3Dev = {
+    .base = SPI3_BASE,
+    .clkId = CLK_SPI3,
+    .clkGateID = CLK_SPI3_GATE,
+    .pclkGateID = PCLK_SPI3_GATE,
+    .irqNum = SPI3_IRQn,
+    .isSlave = false,
+    .txDma = {
+        .channel = DMA_REQ_SPI3_TX,
+        .direction = DMA_MEM_TO_DEV,
+        .addr = SPI3_BASE + 0x400,
+        .dmac = DMA0,
+    },
+    .rxDma = {
+        .channel = DMA_REQ_SPI3_RX,
+        .direction = DMA_DEV_TO_MEM,
+        .addr = SPI3_BASE + 0x800,
+        .dmac = DMA0,
+    },
+};
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+const struct HAL_UART_DEV g_uart0Dev =
+{
+    .pReg = UART0,
+    .sclkID = CLK_UART0,
+    .irqNum = UART0_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart1Dev =
+{
+    .pReg = UART1,
+    .sclkID = CLK_UART1,
+    .sclkGateID = SCLK_UART1_GATE,
+    .pclkGateID = PCLK_UART1_GATE,
+    .irqNum = UART1_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart2Dev =
+{
+    .pReg = UART2,
+    .sclkID = CLK_UART2,
+    .sclkGateID = SCLK_UART2_GATE,
+    .pclkGateID = PCLK_UART2_GATE,
+    .irqNum = UART2_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart3Dev =
+{
+    .pReg = UART3,
+    .sclkID = CLK_UART3,
+    .sclkGateID = SCLK_UART3_GATE,
+    .pclkGateID = PCLK_UART3_GATE,
+    .irqNum = UART3_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart4Dev =
+{
+    .pReg = UART4,
+    .sclkID = CLK_UART4,
+    .sclkGateID = SCLK_UART4_GATE,
+    .pclkGateID = PCLK_UART4_GATE,
+    .irqNum = UART4_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart5Dev =
+{
+    .pReg = UART5,
+    .sclkID = CLK_UART5,
+    .sclkGateID = SCLK_UART5_GATE,
+    .pclkGateID = PCLK_UART5_GATE,
+    .irqNum = UART5_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart6Dev =
+{
+    .pReg = UART6,
+    .sclkID = CLK_UART6,
+    .sclkGateID = SCLK_UART6_GATE,
+    .pclkGateID = PCLK_UART6_GATE,
+    .irqNum = UART6_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart7Dev =
+{
+    .pReg = UART7,
+    .sclkID = CLK_UART7,
+    .sclkGateID = SCLK_UART7_GATE,
+    .pclkGateID = PCLK_UART7_GATE,
+    .irqNum = UART7_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart8Dev =
+{
+    .pReg = UART8,
+    .sclkID = CLK_UART8,
+    .sclkGateID = SCLK_UART8_GATE,
+    .pclkGateID = PCLK_UART8_GATE,
+    .irqNum = UART8_IRQn,
+    .isAutoFlow = false,
+};
+
+const struct HAL_UART_DEV g_uart9Dev =
+{
+    .pReg = UART9,
+    .sclkID = CLK_UART9,
+    .sclkGateID = SCLK_UART9_GATE,
+    .pclkGateID = PCLK_UART9_GATE,
+    .irqNum = UART9_IRQn,
+    .isAutoFlow = false,
+};
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+const struct HAL_I2C_DEV g_i2c0Dev =
+{
+    .pReg = I2C0,
+    .irqNum = I2C0_IRQn,
+    .clkID = CLK_I2C,
+    .clkGateID = CLK_I2C0_GATE,
+    .pclkGateID = PCLK_I2C0_GATE,
+    .runtimeID = PM_RUNTIME_ID_I2C0,
+};
+
+const struct HAL_I2C_DEV g_i2c1Dev =
+{
+    .pReg = I2C1,
+    .irqNum = I2C1_IRQn,
+    .clkID = CLK_I2C,
+    .clkGateID = CLK_I2C1_GATE,
+    .pclkGateID = PCLK_I2C1_GATE,
+    .runtimeID = PM_RUNTIME_ID_I2C1,
+};
+
+const struct HAL_I2C_DEV g_i2c2Dev =
+{
+    .pReg = I2C2,
+    .irqNum = I2C2_IRQn,
+    .clkID = CLK_I2C,
+    .clkGateID = CLK_I2C2_GATE,
+    .pclkGateID = PCLK_I2C2_GATE,
+    .runtimeID = PM_RUNTIME_ID_I2C2,
+};
+
+const struct HAL_I2C_DEV g_i2c3Dev =
+{
+    .pReg = I2C3,
+    .irqNum = I2C3_IRQn,
+    .clkID = CLK_I2C,
+    .clkGateID = CLK_I2C3_GATE,
+    .pclkGateID = PCLK_I2C3_GATE,
+    .runtimeID = PM_RUNTIME_ID_I2C3,
+};
+
+const struct HAL_I2C_DEV g_i2c4Dev =
+{
+    .pReg = I2C4,
+    .irqNum = I2C4_IRQn,
+    .clkID = CLK_I2C,
+    .clkGateID = CLK_I2C4_GATE,
+    .pclkGateID = PCLK_I2C4_GATE,
+    .runtimeID = PM_RUNTIME_ID_I2C4,
+};
+
+const struct HAL_I2C_DEV g_i2c5Dev =
+{
+    .pReg = I2C5,
+    .irqNum = I2C5_IRQn,
+    .clkID = CLK_I2C,
+    .clkGateID = CLK_I2C5_GATE,
+    .pclkGateID = PCLK_I2C5_GATE,
+    .runtimeID = PM_RUNTIME_ID_I2C5,
+};
+#endif
+
+#ifdef HAL_FSPI_MODULE_ENABLED
+struct HAL_FSPI_HOST g_fspi0Dev =
+{
+    .instance = FSPI,
+    .sclkGate = SCLK_SFC_GATE,
+    .hclkGate = HCLK_SFC_GATE,
+    .xipClkGate = 0,
+    .sclkID = 0,
+    .irqNum = FSPI0_IRQn,
+    .xipMemCode = 0,
+    .xipMemData = 0,
+    .xmmcDev[0] =
+    {
+        .type = 0,
+    },
+};
+#endif
+
+#ifdef HAL_CANFD_MODULE_ENABLED
+const struct HAL_CANFD_DEV g_can0Dev =
+{
+    .pReg = CAN0,
+    .sclkID = CLK_CAN0,
+    .sclkGateID = CLK_CAN0_GATE,
+    .pclkGateID = PCLK_CAN0_GATE,
+    .irqNum = CAN0_IRQn,
+};
+
+const struct HAL_CANFD_DEV g_can1Dev =
+{
+    .pReg = CAN1,
+    .sclkID = CLK_CAN1,
+    .sclkGateID = CLK_CAN1_GATE,
+    .pclkGateID = PCLK_CAN1_GATE,
+    .irqNum = CAN1_IRQn,
+};
+
+const struct HAL_CANFD_DEV g_can2Dev =
+{
+    .pReg = CAN2,
+    .sclkID = CLK_CAN2,
+    .sclkGateID = CLK_CAN2_GATE,
+    .pclkGateID = PCLK_CAN2_GATE,
+    .irqNum = CAN2_IRQn,
+};
+#endif
+
+#ifdef HAL_GMAC_MODULE_ENABLED
+// const struct HAL_GMAC_DEV g_gmac0Dev =
+// {
+//     .pReg = GMAC0,
+//     .clkID = CLK_MAC0_2TOP,
+//     .clkGateID = CLK_MAC0_2TOP_GATE,
+//     .pclkID = PCLK_PHP,
+//     .pclkGateID = PCLK_GMAC0_GATE,
+//     .irqNum = GMAC0_IRQn,
+// };
+const struct HAL_GMAC_DEV g_gmac0Dev =
+{
+    .pReg = GMAC0,
+    .clkID125M = CLK_MAC0_2TOP,
+    .clkID50M = CLK_MAC0_2TOP,
+    .clkGateID125M = CLK_MAC0_2TOP_GATE,
+    .clkGateID50M = CLK_MAC0_2TOP_GATE,
+    .pclkID = PCLK_PHP,
+    .pclkGateID = PCLK_GMAC0_GATE,
+    .irqNum = GMAC0_IRQn,
+};
+
+// const struct HAL_GMAC_DEV g_gmac1Dev =
+// {
+//     .pReg = GMAC1,
+//     .clkID = CLK_MAC1_2TOP,
+//     .clkGateID = CLK_MAC1_2TOP_GATE,
+//     .pclkID = PCLK_USB,
+//     .pclkGateID = PCLK_GMAC1_GATE,
+//     .irqNum = GMAC1_IRQn,
+// };
+const struct HAL_GMAC_DEV g_gmac1Dev =
+{
+    .pReg = GMAC1,
+    .clkID125M = CLK_MAC1_2TOP,
+    .clkID50M = CLK_MAC1_2TOP,
+    .clkGateID125M = CLK_MAC1_2TOP_GATE,
+    .clkGateID50M = CLK_MAC1_2TOP_GATE,
+    .pclkID = PCLK_USB,
+    .pclkGateID = PCLK_GMAC1_GATE,
+    .irqNum = GMAC1_IRQn,
+};
+#endif
+
+#ifdef HAL_PCIE_MODULE_ENABLED
+struct HAL_PCIE_DEV g_pcieDev =
+{
+    .apbBase = PCIE3X2_APB_BASE,
+    .dbiBase = PCIE3X2_DBI_BASE,
+    .cfgBase = 0xF0000000,
+    .lanes = 2,
+    .gen = 3,
+    .firstBusNo = 0x20,
+    .legacyIrqNum = PCIE30x2_LEGACY_IRQn,
+};
+#endif
+
+#ifdef HAL_PWM_MODULE_ENABLED
+const struct HAL_PWM_DEV g_pwm0Dev =
+{
+    .pReg = PWM0,
+    .clkID = 0,
+    .clkGateID = CLK_PWM0_GATE,
+    .pclkGateID = PCLK_PWM0_GATE,
+    .irqNum = PWM_PMU_IRQn,
+};
+
+const struct HAL_PWM_DEV g_pwm1Dev =
+{
+    .pReg = PWM1,
+    .clkID = CLK_PWM1,
+    .clkGateID = CLK_PWM1_GATE,
+    .pclkGateID = PCLK_PWM1_GATE,
+    .irqNum = PWM1_IRQn,
+};
+
+const struct HAL_PWM_DEV g_pwm2Dev =
+{
+    .pReg = PWM2,
+    .clkID = CLK_PWM2,
+    .clkGateID = CLK_PWM2_GATE,
+    .pclkGateID = PCLK_PWM2_GATE,
+    .irqNum = PWM2_IRQn,
+};
+
+const struct HAL_PWM_DEV g_pwm3Dev =
+{
+    .pReg = PWM3,
+    .clkID = CLK_PWM3,
+    .clkGateID = CLK_PWM3_GATE,
+    .pclkGateID = PCLK_PWM3_GATE,
+    .irqNum = PWM3_IRQn,
+};
+#endif
+
+void BSP_Init(void)
+{
+}

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_debug.c

@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup DEBUG
+ *  @{
+ */
+
+/** @defgroup DEBUG_How_To_Use How To Use
+ *  @{
+
+ The DEBUG driver can be used as follows:
+
+ Implement DBG hook:
+
+ - printf func: define new HAL_SYSLOG in hal_conf.h or use HAL_DBG_Printf() in default;
+ - assert func: redefine AssertFailed().
+
+ Define debug level in hal_conf.h:
+
+ - HAL_DBG_ON: print master switch;
+ - HAL_DBG_INFO_ON: information printing switch;
+ - HAL_DBG_WRN_ON: information printing switch;
+ - HAL_DBG_ERR_ON: information printing switch;
+ - HAL_ASSERT_ON: Support assert.
+
+ APIS:
+
+ - printf information by calling HAL_DBG();
+ - printf warning by calling HAL_DBG_WRN();
+ - printf error by calling HAL_DBG_ERR();
+ - do assert by calling HAL_ASSERT().
+
+ @} */
+
+#include "hal_base.h"
+
+/** @defgroup DEBUG_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/** @} */
+/********************* Public Function Definition ****************************/
+
+/** @defgroup DEBUG_Exported_Functions_Group5 Other Functions
+
+ This section provides functions allowing to init and deinit module as follows:
+
+ *  @{
+ */
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the HAL_ASSERT error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: HAL_ASSERT error line source number
+  */
+__attribute__((weak)) void HAL_AssertFailed(const char *file, uint32_t line)
+{
+    HAL_DBG_ERR("assert failed at %s %lu\n", file, line);
+    while (1) {
+        ;
+    }
+}
+
+/**
+ * @brief  format hex print.
+ * @param  s: head tag for every new line.
+ * @param  buf: buffer for printing.
+ * @param  width: every single printed object width.
+ * @param  len: the number of printed objects.
+ * @return HAL_Status: HAL_OK.
+ * sum = width * len (BYTE).
+ */
+HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len)
+{
+#ifdef HAL_DBG_ON
+    uint32_t i, j;
+    unsigned char *p8 = (unsigned char *)buf;
+    unsigned short *p16 = (unsigned short *)buf;
+    uint32_t *p32 = (uint32_t *)buf;
+
+    j = 0;
+    for (i = 0; i < len; i++) {
+        if (j == 0) {
+            HAL_SYSLOG("[HAL_DBG_HEX] %s %p + 0x%lx:", s, buf, i * width);
+        }
+
+        if (width == 4) {
+            HAL_SYSLOG("0x%08lx,", p32[i]);
+        } else if (width == 2) {
+            HAL_SYSLOG("0x%04x,", p16[i]);
+        } else {
+            HAL_SYSLOG("0x%02x,", p8[i]);
+        }
+
+        if (++j >= 16) {
+            j = 0;
+            HAL_SYSLOG("\n");
+        }
+    }
+    HAL_SYSLOG("\n");
+#endif
+
+    return HAL_OK;
+}
+
+#ifdef HAL_DBG_USING_HAL_PRINTF
+static void reverse(char *start, char *end)
+{
+    while (start < end) {
+        char temp = *start;
+        *start = *end;
+        *end = temp;
+        start++;
+        end--;
+    }
+}
+
+#ifdef __GNUC__
+extern int _write(int fd, char *ptr, int len);
+#endif
+
+/**
+ * @brief  format and print data
+ * @param  format: format printf param. only support: \%d, \%s, \%ld, \%lld
+ * @return int32_t.
+ */
+__attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...)
+{
+    static char g_printf_buf[HAL_PRINTF_BUF_SIZE];
+    char *str = g_printf_buf;
+    int32_t len = 0;
+    va_list args;
+
+    va_start(args, format);
+
+    while (*format != '\0') {
+        if (*format == '%') {
+            format++;
+            if (*format == 'd') {
+                int i = va_arg(args, int);
+                char *start = str;
+                do {
+                    *str++ = '0' + (i % 10);
+                    i /= 10;
+                } while (i > 0);
+                reverse(start, str - 1);
+            } else if (*format == 's') {
+                char *s = va_arg(args, char *);
+                while (*s) {
+                    *str++ = *s++;
+                }
+            } else if (*format == 'l') {
+                format++;
+                if (*format == 'd') {
+                    long i = va_arg(args, long);
+                    char *start = str;
+                    do {
+                        *str++ = '0' + (i % 10);
+                        i /= 10;
+                    } while (i > 0);
+                    reverse(start, str - 1);
+                } else if (*format == 'l') {
+                    format++;
+                    if (*format == 'd') {
+                        long long int i = va_arg(args, long long int);
+                        char *start = str;
+                        do {
+                            *str++ = '0' + (i % 10);
+                            i /= 10;
+                        } while (i > 0);
+                        reverse(start, str - 1);
+                    }
+                }
+            }
+        } else {
+            *str++ = *format;
+        }
+        format++;
+    }
+
+    *str = '\0';
+
+    va_end(args);
+    len = str - g_printf_buf;
+
+#ifdef __GNUC__
+
+    return _write(2, g_printf_buf, len);
+#else
+    for (int i = 0; i < len; i++) {
+        fputc(g_printf_buf[i], stdout);
+    }
+
+    return len;
+#endif
+}
+#else
+/**
+ * @brief  format and print data
+ * @param  format: format printf param.
+ * @return int32_t.
+ */
+__attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...)
+{
+    return 0;
+}
+#endif /* HAL_DBG_USING_HAL_PRINTF */
+
+/** @} */
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gmac_3568.c

@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+
+#if defined(SOC_RK3568) && defined(HAL_GMAC_MODULE_ENABLED)
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup GMAC
+ *  @{
+ */
+
+/** @defgroup GMAC_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+#define HIWORD_UPDATE(val, mask, shift) \
+        ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define GRF_BIT(nr)     (1 << (nr) | 1 << (nr+16))
+#define GRF_CLR_BIT(nr) (1 << (nr+16))
+
+#define DELAY_ENABLE(soc, tx, rx)                                          \
+    (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
+     ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+
+#define RK3568_GRF_GMAC0_CON0 0X0380
+#define RK3568_GRF_GMAC0_CON1 0X0384
+#define RK3568_GRF_GMAC1_CON0 0X0388
+#define RK3568_GRF_GMAC1_CON1 0X038c
+
+/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
+#define RK3568_GMAC_GMII_MODE GRF_BIT(7)
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
+        (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3568_GMAC_PHY_INTF_SEL_RMII \
+        (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3568_GMAC_FLOW_CTRL         GRF_BIT(3)
+#define RK3568_GMAC_FLOW_CTRL_CLR     GRF_CLR_BIT(3)
+#define RK3568_GMAC_RXCLK_DLY_ENABLE  GRF_BIT(1)
+#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+#define RK3568_GMAC_TXCLK_DLY_ENABLE  GRF_BIT(0)
+#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+
+/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
+#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/** @} */
+/********************* Public Function Definition ****************************/
+
+/** @defgroup GMAC_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Set RGMII Mode.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  txDelay: RGMII tx delayline
+ * @param  rxDelay: RGMII rx delayline
+ */
+void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
+                         int32_t txDelay, int32_t rxDelay)
+{
+    uint32_t *con0, *con1;
+
+    con0 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON0) :
+                                                 &(GRF->MAC0_CON0));
+    con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
+                                                 &(GRF->MAC0_CON1));
+
+    WRITE_REG(*con1,
+              RK3568_GMAC_PHY_INTF_SEL_RGMII |
+              RK3568_GMAC_RXCLK_DLY_ENABLE |
+              RK3568_GMAC_TXCLK_DLY_ENABLE);
+
+    WRITE_REG(*con0,
+              RK3568_GMAC_CLK_RX_DL_CFG(rxDelay) |
+              RK3568_GMAC_CLK_TX_DL_CFG(txDelay));
+}
+
+/**
+ * @brief  Set RMII Mode.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ */
+void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC)
+{
+    uint32_t *con1, *cruCon, val;
+
+    con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
+                                                 &(GRF->MAC0_CON1));
+
+    WRITE_REG(*con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
+
+    cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
+                                                   &(CRU->CRU_CLKSEL_CON[31]));
+    /* RMII mode */
+    val = HIWORD_UPDATE(0x1, 0x3, 0);
+    /* clock from io if it was */
+    /* val |= HIWORD_UPDATE(0x1, 0x1, 2);  */
+    /* ref clock sel 50M */
+    val |= HIWORD_UPDATE(0x1, 0x3, 8);
+    /* clock speed 25M */
+    val |= HIWORD_UPDATE(0x1, 0x1, 3);
+    WRITE_REG(*cruCon, val);
+}
+
+/**
+ * @brief  Set external clock source select.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  extClk: 0: select clk_mac as the clock of mac
+ *                 1: select external phy clock as the clock of mac
+ */
+void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk)
+{
+    uint32_t *cruCon, val;
+    uint32_t clksel = 0;
+
+    cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
+                                                   &(CRU->CRU_CLKSEL_CON[31]));
+
+    if (extClk) {
+        clksel = 1;
+    }
+
+    val = HIWORD_UPDATE(clksel, 0x1, 2);
+    WRITE_REG(*cruCon, val);
+}
+
+/**
+ * @brief  Set RGMII speed.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  speed: RGMII speed 10/100/1000
+ */
+void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
+{
+    eCLOCK_Name clkID;
+    uint32_t rate;
+    int32_t ret;
+
+    switch (speed) {
+    case 10:
+        rate = 2500000;
+        break;
+    case 100:
+        rate = 25000000;
+        break;
+    case 1000:
+        rate = 125000000;
+        break;
+    default:
+        HAL_DBG_ERR("unknown speed value for GMAC speed=%ld", speed);
+
+        return;
+    }
+
+    if (pGMAC->phyStatus.interface == PHY_INTERFACE_MODE_RMII) {
+        clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RMII_SPEED :
+                                         SCLK_GMAC0_RMII_SPEED;
+    } else {
+        clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RGMII_SPEED :
+                                         SCLK_GMAC0_RGMII_SPEED;
+    }
+
+    ret = HAL_CRU_ClkSetFreq(clkID, rate);
+    if (ret) {
+        HAL_DBG_ERR("%s: set clk_mac_speed rate %ld failed %ld\n",
+                    __func__, rate, ret);
+    }
+}
+
+/**
+ * @brief  Set RGMII speed.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  speed: RGMII speed 10/100
+ */
+void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
+{
+    HAL_GMAC_SetRGMIISpeed(pGMAC, speed);
+}
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* SOC_RK3568 && HAL_GMAC_MODULE_ENABLED */

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_gpio.c

@@ -0,0 +1,606 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup GPIO
+ *  @{
+ */
+
+/** @defgroup GPIO_How_To_Use How To Use
+ *  @{
+
+ The GPIO driver can be used as follows:
+
+ APIs for GPIO io read write:
+
+   1. HAL_GPIO_GetPinLevel() to get EXT port level.
+   2. HAL_GPIO_SetPinLevel() to set io level.
+   3. HAL_GPIO_SetPinDirection() to set io direction.
+
+ APIs for GPIO IRQ:
+
+   1. HAL_GPIO_EnableIRQ() to enable a GPIO IRQ.
+   2. HAL_GPIO_DisableIRQ() to disable a GPIO IRQ.
+   3. HAL_GPIO_IRQHandler() to handle GPIO IRQ isr.
+   4. HAL_GPIO_IRQDispatch() to dispatch GPIO IRQ, should be implemented by User.
+
+ Please open the macro definition HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED to support
+
+ APIs for GPIO virtual model:
+
+   1. HAL_GPIO_EnableVirtualModel() to enable a GPIO virtual model.
+   2. HAL_GPIO_DisableVirtualModel() to disable a GPIO virtual model.
+   3. HAL_GPIO_SetVirtualModel() to configure GPIO pins virtual model.
+
+ @} */
+
+/** @defgroup GPIO_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+#define UNUSED(X) (void)(X)      /* To avoid gcc/g++ warnings */
+
+/********************* Private Function Definition ***************************/
+
+/**
+ * @brief  Set the GPIO IRQ end of interrupt(EOI).
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ */
+static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->PORT_EOI_H = pin | (pin >> 16);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->PORT_EOI_L = pin | (pin << 16);
+    }
+#else
+    {
+        pGPIO->PORTA_EOI = pin;
+    }
+#endif
+}
+
+/**
+ * @brief  Get GPIO all pins irq type.
+ * @param  pGPIO: the GPIO struct.
+ * @return uint32_t: type value.
+ */
+static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO)
+{
+    uint32_t type;
+
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    type = (pGPIO->INT_TYPE_L & 0xffff);
+    type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16);
+    type |= (pGPIO->INT_BOTHEDGE_L & 0xffff);
+    type |= ((pGPIO->INT_BOTHEDGE_H & 0xffff) << 16);
+#else
+    type = pGPIO->INTTYPE_LEVEL;
+    #ifdef GPIO_INT_BOTHEDGE_OFFSET
+    type |= pGPIO->INT_BOTHEDGE;
+    #endif
+#endif
+
+    return type;
+}
+
+/**
+ * @brief  Get GPIO all pins irq status.
+ * @param  pGPIO: the GPIO struct.
+ * @return uint32_t: status value.
+ */
+static uint32_t GPIO_GetIntStatus(struct GPIO_REG *pGPIO)
+{
+    return pGPIO->INT_STATUS;
+}
+
+/** @} */
+/********************* Public Function Definition ***************************/
+
+/** @defgroup GPIO_Exported_Functions_Group1 State and Errors Functions
+
+ This section provides functions allowing to get the status of the module:
+
+ *  @{
+ */
+
+/**
+ * @brief  GPIO Configure IRQ trigger type.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  mode: The value defined in @ref eGPIO_intType.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode)
+{
+    uint32_t both = 0, type = 0, plar = 0;
+
+    UNUSED(both);
+
+    switch (mode) {
+    case GPIO_INT_TYPE_EDGE_RISING:
+        type = 1;
+        plar = 1;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_EDGE_FALLING:
+        type = 1;
+        plar = 0;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_LEVEL_HIGH:
+        type = 0;
+        plar = 1;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_LEVEL_LOW:
+        type = 0;
+        plar = 0;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_EDGE_BOTH:
+        type = 0;
+        plar = 0;
+        both = 1;
+        break;
+    default:
+
+        return HAL_INVAL;
+    }
+
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin);
+        pGPIO->INT_POLARITY_H = (plar) ? (pin | (pin >> 16)) : (pin);
+        pGPIO->INT_BOTHEDGE_H = (both) ? (pin | (pin >> 16)) : (pin);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->INT_TYPE_L = (type) ? (pin | (pin << 16)) : (pin << 16);
+        pGPIO->INT_POLARITY_L = (plar) ? (pin | (pin << 16)) : (pin << 16);
+        pGPIO->INT_BOTHEDGE_L = (both) ? (pin | (pin << 16)) : (pin << 16);
+    }
+#else
+    {
+        pGPIO->INTTYPE_LEVEL = (type) ? (pin) : (pGPIO->INTTYPE_LEVEL & ~(pin));
+        pGPIO->INT_POLARITY = (plar) ? (pin) : (pGPIO->INT_POLARITY & ~(pin));
+        #ifdef GPIO_INT_BOTHEDGE_OFFSET
+        pGPIO->INT_BOTHEDGE = (both) ? (pin) : (pGPIO->INT_BOTHEDGE & ~(pin));
+        #endif
+    }
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set GPIO direction.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  direction: direction value defined in @ref eGPIO_pinDirection.
+ * @return HAL_Status: HAL_OK if success.
+ */
+HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->SWPORT_DDR_L = (direction == GPIO_OUT) ? (pin | (pin << 16)) : (pin << 16);
+    }
+#else
+    if (direction == GPIO_OUT) {
+        pGPIO->SWPORTA_DDR |= pin;
+    } else {
+        pGPIO->SWPORTA_DDR &= ~pin;
+    }
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set GPIO direction.
+ * @param  pGPIO: the GPIO struct.
+ * @param  mPins: The pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  direction: value defined in @ref eGPIO_pinDirection.
+ * @return HAL_Status: HAL_OK if success.
+ */
+HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction)
+{
+    uint8_t pin;
+    HAL_Status rc;
+
+    HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO));
+
+    for (pin = 0; pin < 32; pin++) {
+        if (mPins & (1 << pin)) {
+            rc = HAL_GPIO_SetPinDirection(pGPIO, (1 << pin), direction);
+            if (rc) {
+                return rc;
+            }
+        }
+    }
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Get GPIO Pin data direction value.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @retval eGPIO_pinDirection: data direction value.
+ */
+eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+    eGPIO_pinDirection direction;
+    uint32_t value;
+
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin);
+#else
+    value = pGPIO->SWPORTA_DDR & pin;
+#endif
+
+    if (value != (uint32_t)GPIO_IN) {
+        direction = GPIO_OUT;
+    } else {
+        direction = GPIO_IN;
+    }
+
+    return direction;
+}
+
+/**
+ * @brief  Set GPIO pin level.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  level: The level defined in @ref eGPIO_pinLevel.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->SWPORT_DR_L = (level == GPIO_HIGH) ? (pin | (pin << 16)) : (pin << 16);
+    }
+#else
+    if (level == GPIO_HIGH) {
+        pGPIO->SWPORTA_DR |= pin;
+    } else {
+        pGPIO->SWPORTA_DR &= ~pin;
+    }
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set GPIO pin level.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  mPins: The pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  level: The level defined in @ref eGPIO_pinLevel.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level)
+{
+    uint8_t pin;
+    HAL_Status rc;
+
+    HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO));
+
+    for (pin = 0; pin < 32; pin++) {
+        if (mPins & (1 << pin)) {
+            rc = HAL_GPIO_SetPinLevel(pGPIO, (1 << pin), level);
+            if (rc) {
+                return rc;
+            }
+        }
+    }
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO Functions
+
+ This section provides functions allowing to IO controlling:
+
+ *  @{
+ */
+
+/**
+ * @brief  Get GPIO Pin data value.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @retval eGPIO_pinLevel: data value.
+ */
+eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+    eGPIO_pinLevel level;
+    uint32_t value;
+
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin);
+#else
+    value = pGPIO->SWPORTA_DR & pin;
+#endif
+
+    if (value != (uint32_t)GPIO_LOW) {
+        level = GPIO_HIGH;
+    } else {
+        level = GPIO_LOW;
+    }
+
+    return level;
+}
+
+/**
+ * @brief  Get GPIO Pin ext bank level.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @retval GPIO_PinState: ext bank value.
+ */
+eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+    uint32_t value;
+
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    value = (pGPIO->EXT_PORT & pin);
+#else
+    value = (pGPIO->EXT_PORTA & pin);
+#endif
+
+    return (value == (uint32_t)GPIO_LOW) ? GPIO_LOW : GPIO_HIGH;
+}
+
+/**
+ * @brief  Get GPIO Pin ext bank level.
+ * @param  pGPIO: the GPIO struct.
+ * @retval uint32_t: ext bank value.
+ */
+uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
+{
+    uint32_t value;
+
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    value = (pGPIO->EXT_PORT);
+#else
+    value = (pGPIO->EXT_PORTA);
+#endif
+
+    return value;
+}
+/** @} */
+
+/** @defgroup GPIO_Exported_Functions_Group3 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Set GPIO irq enable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ */
+void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_H = pin;
+#endif
+        pGPIO->INT_EN_H = pin | (pin >> 16);
+    } else {
+        pin &= 0x0000FFFF;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_L = pin << 16;
+#endif
+        pGPIO->INT_EN_L = pin | (pin << 16);
+    }
+#else
+    {
+        pGPIO->INTEN |= pin;
+        pGPIO->INTMASK &= ~pin;
+    }
+#endif
+}
+
+/**
+ * @brief  Set GPIO irq disable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ */
+void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->INT_EN_H = pin;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_H = pin | (pin >> 16);
+#endif
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->INT_EN_L = pin << 16;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_L = pin | (pin << 16);
+#endif
+    }
+#else
+    {
+        pGPIO->INTEN &= ~pin;
+        pGPIO->INTMASK |= pin;
+    }
+#endif
+}
+
+/**
+ * @brief  GPIO IRQ callbacks.
+ * @param  bank: The bank id.
+ * @param  pin: The true pin index, 0~31.
+ * NOTE: This function Should not be modified, when the callback is needed,
+ *       the HAL_GPIO_IRQDispatch could be implemented in the user file.
+ */
+__attribute__((weak)) void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin)
+{
+    UNUSED(bank);
+    UNUSED(pin);
+}
+
+/**
+ * @brief  GPIO IRQ hanlder.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  bank: The bank id.
+ */
+void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank)
+{
+    uint32_t stat, type, clear;
+    uint32_t i;
+    uint32_t pin;
+
+    stat = GPIO_GetIntStatus(pGPIO);
+    type = GPIO_GetIntType(pGPIO);
+
+    /* Then process each pending GPIO interrupt */
+    for (i = 0x0U; i < PIN_NUMBER_PER_BANK && stat != 0; i++) {
+        clear = 0x1U << i;
+        pin = HAL_BIT(i);
+
+        if ((stat & clear) != 0x0U) {
+            /* If gpio is Edge-sensitive triggered, clear eoi */
+            if (type & clear) {
+                GPIO_SetEOI(pGPIO, pin);
+            }
+
+            /* Remove the pending interrupt bit from the clear */
+            stat &= ~clear;
+
+            /* And disptach the GPIO interrupt to the handler */
+            HAL_GPIO_IRQDispatch(bank, i);
+        }
+    }
+}
+
+#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED
+
+/**
+ * @brief  GPIO virtual model enable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    pGPIO->GPIO_VIRTUAL_EN = 0x10001;
+
+    return HAL_OK;
+#endif
+
+    return HAL_ERROR;
+}
+
+/**
+ * @brief  GPIO virtual model disable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    pGPIO->GPIO_VIRTUAL_EN = 0x10000;
+
+    return HAL_OK;
+#endif
+
+    return HAL_ERROR;
+}
+
+/**
+ * @brief  GPIO Configure pins for virtual model.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pins: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  vmode: The value defined in @ref eGPIO_VirtualModel.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel)
+{
+#if (GPIO_VER_ID >= 0x01000C2BU)
+    uint32_t lowPins, highPins;
+
+    lowPins = pin & 0x0000ffff;
+    highPins = (pin & 0xffff0000) >> 16;
+
+#if defined(GPIO0_EXP)
+    /* Support OS_A and OS_B */
+    if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) {
+        pGPIO->GPIO_REG_GROUP_L = lowPins << 16;
+        pGPIO->GPIO_REG_GROUP_H = highPins << 16;
+    } else {
+        pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
+    }
+
+    return HAL_OK;
+#elif defined(GPIO0_EXP3)
+    /* Support 4 OS */
+    switch (vmodel) {
+    case GPIO_VIRTUAL_MODEL_OS_A:
+        pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
+        break;
+    case GPIO_VIRTUAL_MODEL_OS_B:
+        pGPIO->GPIO_REG_GROUP1_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP1_H = highPins | (highPins << 16);
+        break;
+    case GPIO_VIRTUAL_MODEL_OS_C:
+        pGPIO->GPIO_REG_GROUP2_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP2_H = highPins | (highPins << 16);
+        break;
+    case GPIO_VIRTUAL_MODEL_OS_D:
+        pGPIO->GPIO_REG_GROUP3_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP3_H = highPins | (highPins << 16);
+        break;
+    default:
+        HAL_DBG("unknown gpio virtual model-%d\n", vmodel);
+        break;
+    }
+
+    return HAL_OK;
+#else
+#error missing GPIO EXP register definition!
+#endif
+#endif
+
+    return HAL_ERROR;
+}
+
+#endif /* HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED */
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_pinctrl_v2.c

@@ -0,0 +1,565 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+
+#if defined(HAL_PINCTRL_MODULE_ENABLED) && (defined(SOC_RV1126) || defined(SOC_SWALLOW) || defined(SOC_RK3568) || defined(RKMCU_RK2106))
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup PINCTRL
+ *  @{
+ */
+
+/** @defgroup PINCTRL_How_To_Use How To Use
+ *  @{
+
+ The pinctrl setting registers actually is bus grf registers, which include
+ iomux, drive strength, pull mode, slew rate and schmitt trigger.
+
+ The pinctrl driver provides APIs:
+   - HAL_PINCTRL_SetIOMUX() to set pin iomux
+   - HAL_PINCTRL_SetParam() to set pin iomux/drive/pull/slewrate/schmitt/ie
+
+ Example:
+
+     HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
+                          GPIO_PIN_A0 | // I2S_IN_SCLK
+                          GPIO_PIN_A1 | // I2S_IN_LRCK
+                          GPIO_PIN_A2 | // I2S_IN_SDI0
+                          GPIO_PIN_A3,  // I2S_IN_SDI1
+                          PIN_CONFIG_MUX_FUNC2);
+
+     HAL_PINCTRL_SetParam(GPIO_BANK0,
+                          GPIO_PIN_A0 | // I2S_IN_SCLK
+                          GPIO_PIN_A1 | // I2S_IN_LRCK
+                          GPIO_PIN_A2 | // I2S_IN_SDI0
+                          GPIO_PIN_A3,  // I2S_IN_SDI1
+                          PIN_CONFIG_MUX_FUNC2 |
+                          PIN_CONFIG_PUL_DOWN |
+                          PIN_CONFIG_DRV_LEVEL2 |
+                          PIN_CONFIG_SRT_FAST |
+                          PIN_CONFIG_SMT_ENABLE);
+ @} */
+
+/** @defgroup PINCTRL_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+#define _TO_MASK(w)         ((1U << (w)) - 1U)
+#define _TO_OFFSET(p, w)    ((p) * (w))
+#define RK_GEN_VAL(p, v, w) ((_TO_MASK(w) << (_TO_OFFSET(p, w) + 16)) | (((v) & _TO_MASK(w)) << _TO_OFFSET(p, w)))
+
+/*
+ * Use HAL_DBG("pinctrl: write val = 0x%lx to register %p\n", VAL, &REG);
+ * and HAL_DBG("pinctrl: readback register %p = 0x%lx\n", &REG, REG);
+ * for debug
+ */
+#define _PINCTRL_WRITE(REG, DATA) \
+{                                 \
+    REG = DATA;                   \
+}
+
+#if defined(GRF_GPIO0A_IOMUX_OFFSET)
+#define IOMUX_BIT_PER_PIN                 (2)
+#define IOMUX_PIN_PER_REG                 (16 / IOMUX_BIT_PER_PIN)
+#define IOMUX_0(__B, __P)                 (GRF->GPIO##__B##__P##_IOMUX)
+#define SET_IOMUX_0(_B, _P, p, v, w)      _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_IOMUX_0(B, P, p, v)        SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define SET_IOMUX(_GPIO, _PORT, pin, val) RK_SET_IOMUX_0(_GPIO, _PORT, pin, val)
+
+#elif defined(GRF_GPIO0A_IOMUX_H_OFFSET)
+#define IOMUX_BIT_PER_PIN            (4)
+#define IOMUX_PIN_PER_REG            (16 / IOMUX_BIT_PER_PIN)
+#define IOMUX_0(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_L)
+#define IOMUX_1(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_H)
+#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_IOMUX_0(B, P, p, v)   SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_1(B, P, p, v)   SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define SET_IOMUX(_GPIO, _PORT, pin, val)       \
+{                                               \
+    if ((pin % 8) < 4) {                        \
+        RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \
+    } else {                                    \
+        RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \
+    }                                           \
+}
+
+#elif defined(GRF_GPIO0A_IOMUX_0_OFFSET)
+#define IOMUX_BIT_PER_PIN            (8)
+#define IOMUX_PIN_PER_REG            (16 / IOMUX_BIT_PER_PIN)
+#define IOMUX_0(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_0)
+#define IOMUX_1(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_1)
+#define IOMUX_2(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_2)
+#define IOMUX_3(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_3)
+#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_2(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_2(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_3(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_3(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_IOMUX_0(B, P, p, v)   SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_1(B, P, p, v)   SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_2(B, P, p, v)   SET_IOMUX_2(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_3(B, P, p, v)   SET_IOMUX_3(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define SET_IOMUX(_GPIO, _PORT, pin, val)       \
+{                                               \
+    if ((pin % 8) < 2) {                        \
+        RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 4) {                 \
+        RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 6) {                 \
+        RK_SET_IOMUX_2(_GPIO, _PORT, pin, val); \
+    } else {                                    \
+        RK_SET_IOMUX_3(_GPIO, _PORT, pin, val); \
+    }                                           \
+}
+#endif
+
+#if defined(GRF_GPIO0A_DS_OFFSET)
+#define DS_BIT_PER_PIN                 (2)
+#define DS_PIN_PER_REG                 (16 / DS_BIT_PER_PIN)
+#define DS_0(__B, __P)                 (GRF->GPIO##__B##__P##_DS)
+#define SET_DS_0(_B, _P, p, v, w)      _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_DS_0(B, P, p, v)        SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define SET_DS(_GPIO, _PORT, pin, val) RK_SET_DS_0(_GPIO, _PORT, pin, val)
+
+#elif defined(GRF_GPIO0A_DS_H_OFFSET)
+#define DS_BIT_PER_PIN            (4)
+#define DS_PIN_PER_REG            (16 / DS_BIT_PER_PIN)
+#define DS_0(__B, __P)            (GRF->GPIO##__B##__P##_DS_L)
+#define DS_1(__B, __P)            (GRF->GPIO##__B##__P##_DS_L)
+#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_DS_0(B, P, p, v)   SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_1(B, P, p, v)   SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define SET_DS(_GPIO, _PORT, pin, val)       \
+{                                            \
+    if ((pin % 8) < 4) {                     \
+        RK_SET_DS_0(_GPIO, _PORT, pin, val); \
+    } else {                                 \
+        RK_SET_DS_1(_GPIO, _PORT, pin, val); \
+    }                                        \
+}
+
+#elif defined(GRF_GPIO0A_DS_0_OFFSET)
+#define DS_BIT_PER_PIN            (8)
+#define DS_PIN_PER_REG            (16 / DS_BIT_PER_PIN)
+#define DS_0(__B, __P)            (GRF->GPIO##__B##__P##_DS_0)
+#define DS_1(__B, __P)            (GRF->GPIO##__B##__P##_DS_1)
+#define DS_2(__B, __P)            (GRF->GPIO##__B##__P##_DS_2)
+#define DS_3(__B, __P)            (GRF->GPIO##__B##__P##_DS_3)
+#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_2(_B, _P, p, v, w) _PINCTRL_WRITE(DS_2(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_3(_B, _P, p, v, w) _PINCTRL_WRITE(DS_3(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_DS_0(B, P, p, v)   SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_1(B, P, p, v)   SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_2(B, P, p, v)   SET_DS_2(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_3(B, P, p, v)   SET_DS_3(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define SET_DS(_GPIO, _PORT, pin, val)       \
+{                                            \
+    if ((pin % 8) < 2) {                     \
+        RK_SET_DS_0(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 4) {              \
+        RK_SET_DS_1(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 6) {              \
+        RK_SET_DS_2(_GPIO, _PORT, pin, val); \
+    } else {                                 \
+        RK_SET_DS_3(_GPIO, _PORT, pin, val); \
+    }                                        \
+}
+#endif
+
+#if defined(GRF_GPIO0A_P_OFFSET)
+#define P_BIT_PER_PIN                 (2)
+#define P_PIN_PER_REG                 (16 / P_BIT_PER_PIN)
+#define P_0(__B, __P)                 (GRF->GPIO##__B##__P##_P)
+#define SET_P_0(_B, _P, p, v, w)      _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_P_0(B, P, p, v)        SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define SET_P(_GPIO, _PORT, pin, val) RK_SET_P_0(_GPIO, _PORT, pin, val)
+
+#elif defined(GRF_GPIO0A_P_H_OFFSET)
+#define P_BIT_PER_PIN            (4)
+#define P_PIN_PER_REG            (16 / P_BIT_PER_PIN)
+#define P_0(__B, __P)            (GRF->GPIO##__B##__P##_P_L)
+#define P_1(__B, __P)            (GRF->GPIO##__B##__P##_P_L)
+#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_P_0(B, P, p, v)   SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_1(B, P, p, v)   SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define SET_P(_GPIO, _PORT, pin, val)       \
+{                                           \
+    if ((pin % 8) < 4) {                    \
+        RK_SET_P_0(_GPIO, _PORT, pin, val); \
+    } else {                                \
+        RK_SET_P_3(_GPIO, _PORT, pin, val); \
+    }                                       \
+}
+
+#elif defined(GRF_GPIO0A_P_0_OFFSET)
+#define P_BIT_PER_PIN            (8)
+#define P_PIN_PER_REG            (16 / P_BIT_PER_PIN)
+#define P_0(__B, __P)            (GRF->GPIO##__B##__P##_P_0)
+#define P_1(__B, __P)            (GRF->GPIO##__B##__P##_P_1)
+#define P_2(__B, __P)            (GRF->GPIO##__B##__P##_P_2)
+#define P_3(__B, __P)            (GRF->GPIO##__B##__P##_P_3)
+#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_2(_B, _P, p, v, w) _PINCTRL_WRITE(P_2(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_3(_B, _P, p, v, w) _PINCTRL_WRITE(P_3(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_P_0(B, P, p, v)   SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_1(B, P, p, v)   SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_2(B, P, p, v)   SET_P_2(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_3(B, P, p, v)   SET_P_3(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define SET_P(_GPIO, _PORT, pin, val)       \
+{                                           \
+    if ((pin % 8) < 2) {                    \
+        RK_SET_P_0(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 4) {             \
+        RK_SET_P_1(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 6) {             \
+        RK_SET_P_2(_GPIO, _PORT, pin, val); \
+    } else {                                \
+        RK_SET_P_3(_GPIO, _PORT, pin, val); \
+    }                                       \
+}
+#endif
+
+#ifdef SET_IOMUX
+#define PINCTRL_SET_IOMUX(bank, pin, val) \
+{                                         \
+    if (pin < 8) {                        \
+        SET_IOMUX(bank, A, pin, val);     \
+    } else if (pin < 16) {                \
+        SET_IOMUX(bank, B, pin, val);     \
+    } else if (pin < 24) {                \
+        SET_IOMUX(bank, C, pin, val);     \
+    } else {                              \
+        SET_IOMUX(bank, D, pin, val);     \
+    }                                     \
+}
+#endif
+
+#ifdef SET_DS
+#define PINCTRL_SET_DS(bank, pin, val) \
+{                                      \
+    if (pin < 8) {                     \
+        SET_DS(bank, A, pin, val);     \
+    } else if (pin < 16) {             \
+        SET_DS(bank, B, pin, val);     \
+    } else if (pin < 24) {             \
+        SET_DS(bank, C, pin, val);     \
+    } else {                           \
+        SET_DS(bank, D, pin, val);     \
+    }                                  \
+}
+#endif
+
+#ifdef SET_P
+#define PINCTRL_SET_P(bank, pin, val) \
+{                                     \
+    if (pin < 8) {                    \
+        SET_P(bank, A, pin, val);     \
+    } else if (pin < 16) {            \
+        SET_P(bank, B, pin, val);     \
+    } else if (pin < 24) {            \
+        SET_P(bank, C, pin, val);     \
+    } else {                          \
+        SET_P(bank, D, pin, val);     \
+    }                                 \
+}
+#endif
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/**
+ * @brief  Private function to set iomux for one pin.
+ * @param  bank: pin bank channel.
+ * @param  pin: pin index, 0~31.
+ * @param  param: value to write.
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t data)
+{
+#ifdef PINCTRL_SET_IOMUX
+    switch (bank) {
+#ifdef GPIO0
+    case 0:
+        PINCTRL_SET_IOMUX(0, pin, data);
+        break;
+#endif
+#ifdef GPIO1
+    case 1:
+        PINCTRL_SET_IOMUX(1, pin, data);
+        break;
+#endif
+#ifdef GPIO2
+    case 2:
+        PINCTRL_SET_IOMUX(2, pin, data);
+        break;
+#endif
+#ifdef GPIO3
+    case 3:
+        PINCTRL_SET_IOMUX(3, pin, data);
+        break;
+#endif
+#ifdef GPIO4
+    case 4:
+    #ifdef SOC_RV1126
+        if (pin < 2) {
+            GRF->GPIO4A_IOMUX_L = RK_GEN_VAL(pin % IOMUX_PIN_PER_REG, data, IOMUX_BIT_PER_PIN);
+        }
+    #else
+        PINCTRL_SET_IOMUX(4, pin, data);
+    #endif
+        break;
+#endif
+    default:
+        HAL_DBG("unknown gpio%d\n", bank);
+        break;
+    }
+
+    return HAL_OK;
+#else
+
+    return HAL_ERROR;
+#endif
+}
+
+/**
+ * @brief  Private function to set drive strength for one pin.
+ * @param  bank: pin bank channel.
+ * @param  pin: pin index, 0~31.
+ * @param  param: value to write.
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetDS(eGPIO_bankId bank, uint8_t pin, uint32_t data)
+{
+#ifdef PINCTRL_SET_DS
+    switch (bank) {
+#ifdef GPIO0
+    case 0:
+        PINCTRL_SET_DS(0, pin, data);
+        break;
+#endif
+#ifdef GPIO1
+    case 1:
+        PINCTRL_SET_DS(1, pin, data);
+        break;
+#endif
+#ifdef GPIO2
+    case 2:
+        PINCTRL_SET_DS(2, pin, data);
+        break;
+#endif
+#ifdef GPIO3
+    case 3:
+        PINCTRL_SET_DS(3, pin, data);
+        break;
+#endif
+#ifdef GPIO4
+    case 4:
+    #ifdef SOC_RV1126
+        if (pin < 2) {
+            GRF->GPIO4A_DS_L = RK_GEN_VAL(pin % DS_PIN_PER_REG, data, DS_BIT_PER_PIN);
+        }
+    #else
+        PINCTRL_SET_DS(4, pin, data);
+    #endif
+        break;
+#endif
+    default:
+        HAL_DBG("unknown gpio%d\n", bank);
+        break;
+    }
+
+    return HAL_OK;
+#else
+
+    return HAL_ERROR;
+#endif
+}
+
+/**
+ * @brief  Private function to set pupd for one pin.
+ * @param  bank: pin bank channel.
+ * @param  pin: pin index, 0~31.
+ * @param  param: value to write.
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetPUPD(eGPIO_bankId bank, uint8_t pin, uint32_t data)
+{
+#ifdef PINCTRL_SET_P
+    switch (bank) {
+#ifdef GPIO0
+    case 0:
+    #ifdef SOC_RV1126
+        if (pin < 8) {
+            SET_P(0, A, pin, data);
+        } else if (pin < 16) {
+            SET_P(0, B, pin, data);
+        } else if (pin < 20) {
+            GRF->GPIO0C_P_L = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
+        } else if (pin < 24) {
+            GRF->GPIO0C_P_H = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
+        } else {
+            SET_P(0, D, pin, data);
+        }
+    #else
+        PINCTRL_SET_P(0, pin, data);
+    #endif
+        break;
+#endif
+#ifdef GPIO1
+    case 1:
+        PINCTRL_SET_P(1, pin, data);
+        break;
+#endif
+#ifdef GPIO2
+    case 2:
+        PINCTRL_SET_P(2, pin, data);
+        break;
+#endif
+#ifdef GPIO3
+    case 3:
+        PINCTRL_SET_P(3, pin, data);
+        break;
+#endif
+#ifdef GPIO4
+    case 4:
+        #ifdef SOC_RV1126
+        if (pin < 2) {
+            GRF->GPIO4A_P = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
+        }
+        #else
+        PINCTRL_SET_P(4, pin, data);
+        #endif
+        break;
+#endif
+    default:
+        HAL_DBG("unknown gpio%d\n", bank);
+        break;
+    }
+
+    return HAL_OK;
+#else
+
+    return HAL_ERROR;
+#endif
+}
+
+/**
+ * @brief  Private function to configure one pin.
+ * @param  bank: pin bank channel defined in @ref eGPIO_bankId.
+ * @param  pin: pin index, 0~31.
+ * @param  param: multi params defined in @ref ePINCTRL_configParam,
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param)
+{
+    HAL_Status rc = HAL_OK;
+
+    if (param & FLAG_MUX) {
+        rc |= PINCTRL_SetIOMUX(bank, pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX));
+    }
+
+    if (param & FLAG_PUL) {
+        rc |= PINCTRL_SetPUPD(bank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL));
+    }
+
+    if (param & FLAG_DRV) {
+        rc |= PINCTRL_SetDS(bank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV));
+    }
+
+    return rc;
+}
+/** @} */
+
+/********************* Public Function Definition ****************************/
+
+/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions
+
+ This section provides functions allowing to suspend and resume the module:
+
+ *  @{
+ */
+
+/** @} */
+
+/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions
+
+ This section provides functions allowing to init and deinit the module:
+
+ *  @{
+ */
+HAL_Status HAL_PINCTRL_Init(void)
+{
+    return HAL_OK;
+}
+
+HAL_Status HAL_PINCTRL_DeInit(void)
+{
+    return HAL_OK;
+}
+/** @} */
+
+/** @defgroup PINCTRL_Exported_Functions_Group3 IO Functions
+
+ *  @{
+ */
+
+/**
+ * @brief  Public function to configure for multi pins.
+ * @param  bank: pin bank channel defined in eGPIO_bankId.
+ * @param  mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  param: multi params defined in @ref ePINCTRL_configParam.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param)
+{
+    uint8_t pin;
+    HAL_Status rc;
+
+    HAL_ASSERT(bank < GPIO_BANK_NUM);
+
+    if (!(param & (FLAG_MUX | FLAG_PUL | FLAG_DRV | FLAG_SRT | FLAG_SMT))) {
+        return HAL_OK;
+    }
+
+    for (pin = 0; pin < 32; pin++) {
+        if (mPins & (1 << pin)) {
+            rc = PINCTRL_SetPinParam(bank, pin, param);
+            if (rc) {
+                return rc;
+            }
+        }
+    }
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Public function to set iomux for multi pins.
+ * @param  bank: pin bank channel defined in eGPIO_bankId.
+ * @param  mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  param: multi params defined in @ref ePINCTRL_configParam.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param)
+{
+    return HAL_PINCTRL_SetParam(bank, mPins, param);
+}
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* HAL_PINCTRL_MODULE_ENABLED */

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/hal_timer.c

@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup TIMER
+ *  @{
+ */
+
+/** @defgroup TIMER_How_To_Use How To Use
+ *  @{
+
+ The TIMER driver can be used as follows:
+
+ - IT mode: Resgister TIMER handler.
+ - Initialize the TIMER by calling HAL_TIMER_Init():
+ - Set TIMER count by calling HAL_TIMER_SetCount().
+ - Start the TIMER by calling HAL_TIMER_Start() or HAL_TIMER_Start_IT().
+ - Stop the TIMER by calling HAL_TIMER_Stop() or HAL_TIMER_Stop_IT().
+
+ SYS_TIMER
+
+ - SYS_TIMER is a rk timer fixed to serve the delay system. Invoke HAL_TIMER_SysTimerInit() to init.
+
+ @} */
+
+/** @defgroup TIMER_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+#define TIMER_CONTROLREG_TIMER_MODE_FREE_RUNNING (0x0U << TIMER_CONTROLREG_TIMER_MODE_SHIFT)
+
+#define TIMER_CONTROLREG_TIMER_ENABLE_ENABLED  (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT)
+#define TIMER_CONTROLREG_TIMER_ENABLE_DISABLED (0x0U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT)
+
+#define TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT)
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/** @} */
+/********************* Public Function Definition ****************************/
+
+/** @defgroup TIMER_Exported_Functions_Group4 Init and DeInit Functions
+
+ This section provides functions allowing to init and deinit module as follows:
+
+ *  @{
+ */
+
+/**
+ * @brief  Timer init.
+ * @param  pReg: Choose TIMER.
+ * @param  mode: Choose TIMER mode.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    WRITE_REG(pReg->CONTROLREG, mode << TIMER_CONTROLREG_TIMER_MODE_SHIFT);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  System Timer init.
+ * @return HAL_Status.
+ * @attention this API allow direct use in the HAL layer. SYS_TTIMER is used for delay system.
+ */
+HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+
+    if (READ_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK)) {
+        return HAL_OK;
+    }
+
+    WRITE_REG(pReg->CONTROLREG, TIMER_FREE_RUNNING);
+    pReg->LOAD_COUNT[0] = 0xFFFFFFFFU;
+    pReg->LOAD_COUNT[1] = 0xFFFFFFFFU;
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK);
+    SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Timer deinit.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    WRITE_REG(pReg->CONTROLREG, 0);
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @defgroup TIMER_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Start TIMER counter.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK);
+    SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Stop TIMER counter.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ * Just disable TIMER, and keep TIMER configuration.
+ */
+HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Start TIMER counter in interrupt mode.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_ENABLED | TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Stop TIMER counter in interrupt mode.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ * Just disable TIMER, and keep TIMER configuration.
+ */
+HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set TIMER count number.
+ * @param  pReg: Choose TIMER.
+ * @param  timerCount: TIMER counter loading number.
+ * @return HAL_Status.
+ * Set timer count number.
+ */
+HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t timerCount)
+{
+    uint64_t loadCount = 0;
+
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    loadCount = timerCount;
+    pReg->LOAD_COUNT[0] = (loadCount & 0xffffffff);
+    pReg->LOAD_COUNT[1] = ((loadCount >> 32) & 0xffffffff);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Get TIMER count number.
+ * @param  pReg: Choose TIMER.
+ * @return uint64_t: Current conut number.
+ */
+HAL_SECTION_SRAM_CODE
+uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg)
+{
+    uint32_t high, low, temp;
+
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+
+    do {
+        high = pReg->CURRENT_VALUE[1];
+        low = pReg->CURRENT_VALUE[0];
+        temp = pReg->CURRENT_VALUE[1];
+    } while (high != temp);
+
+    return ((uint64_t)high << 32) | low;
+}
+
+/**
+ * @brief  Clear TIMER interrupt status.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status: HAL_OK.
+ */
+HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg)
+{
+    uint32_t timeOut = 1000;
+
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+
+    pReg->INTSTATUS = 0x1;
+    while (pReg->INTSTATUS && timeOut) {
+        timeOut--;
+    }
+
+    if (timeOut == 0) {
+        return HAL_TIMEOUT;
+    } else {
+        return HAL_OK;
+    }
+}
+
+/**
+ * @brief  TIMER0 interrupt handler.
+ * @return HAL_Status: HAL_OK.
+ * Clear interrupt status.
+ */
+__attribute__((weak)) HAL_Status HAL_TIMER0_Handler(void)
+{
+    HAL_TIMER_ClrInt(TIMER0);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  TIMER1 interrupt handler.
+ * @return HAL_Status: HAL_OK.
+ * Clear interrupt status.
+ */
+__attribute__((weak)) HAL_Status HAL_TIMER1_Handler(void)
+{
+    HAL_TIMER_ClrInt(TIMER1);
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+#endif /* HAL_TIMER_MODULE_ENABLED */

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/system_rk3568.c

@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+#include "soc.h"
+
+/* The frequency of SYSTEM_CLOCK is determined by the previous firmware. */
+#define  SYSTEM_CLOCK  816000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+    SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+// void SystemInit (void)
+// {
+// #if defined(HAL_AP_CORE) && defined(HAL_DCACHE_MODULE_ENABLED)
+// /* do not use global variables because this function is called before
+//    reaching pre-main. RW section may be overwritten afterwards.          */
+
+//     // Invalidate entire Unified TLB
+//     __set_TLBIALL(0);
+
+//     // Invalidate entire branch predictor array
+//     __set_BPIALL(0);
+//     __DSB();
+//     __ISB();
+
+//     //  Invalidate instruction cache and flush branch target cache
+//     __set_ICIALLU(0);
+//     __DSB();
+//     __ISB();
+
+//     //  Invalidate data cache
+//     L1C_InvalidateDCacheAll();
+// #endif
+
+// #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+//     // Enable FPU
+//     __FPU_Enable();
+// #endif
+
+// #if defined(HAL_AP_CORE) && defined(HAL_DCACHE_MODULE_ENABLED)
+//     // Create Translation Table
+//     MMU_CreateTranslationTable();
+
+//     // Enable MMU
+//     MMU_Enable();
+
+//     // Enable Caches
+//     L1C_EnableCaches();
+//     L1C_EnableBTAC();
+// #endif
+
+// #if defined(HAL_MCU_CORE) && defined(HAL_INTMUX_MODULE_ENABLED)
+//     HAL_INTMUX_Init();
+// #endif
+// }
+
+// void DataInit (void)
+// {
+// #ifdef HAL_AP_CORE
+
+//     typedef struct {
+//         unsigned long* dest;
+//         unsigned long  wlen;
+//     } __zero_table_t;
+
+//     extern const __zero_table_t __zero_table_start__;
+//     extern const __zero_table_t __zero_table_end__;
+
+//     for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+//         for (unsigned long i = 0u; i < pTable->wlen; ++i) {
+//             pTable->dest[i] = 0u;
+//         }
+//     }
+// #endif /* HAL_AP_CORE */
+// }

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/hal/test_gmac.c

@@ -0,0 +1,753 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_bsp.h"
+#include "hal_base.h"
+#include "hal_gmac.h"
+#include "usyscall.h"
+#if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED))
+
+/*************************** GMAC DRIVER ****************************/
+
+/***************************** MACRO Definition ******************************/
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+
+/***************************** Structure Definition **************************/
+
+/***************************** Function Declare ******************************/
+
+/********************* Private MACRO Definition ******************************/
+#define GMAC_BUS_MAX 2
+
+#define ARCH_DMA_MINALIGN 64
+
+#define GMAC_DESCRIPTOR_SIZE 16
+#define GMAC_DESCRIPTORS_TX  8
+#define GMAC_DESCRIPTORS_RX  8
+#define GMAC_DESC_TX_SIZE    HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_TX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
+#define GMAC_DESC_RX_SIZE    HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_RX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
+
+#define GMAC_RX_BUFFER_SIZE (GMAC_DESCRIPTORS_RX * HAL_GMAC_MAX_PACKET_SIZE)
+#define GMAC_TX_BUFFER_SIZE (GMAC_DESCRIPTORS_TX * HAL_GMAC_MAX_PACKET_SIZE)
+
+/* Basic mode control register. */
+#define BMCR_RESV      0x003f      /* Unused...                   */
+#define BMCR_SPEED1000 0x0040     /* MSB of Speed (1000)         */
+#define BMCR_CTST      0x0080     /* Collision test              */
+#define BMCR_FULLDPLX  0x0100     /* Full duplex                 */
+#define BMCR_ANRESTART 0x0200     /* Auto negotiation restart    */
+#define BMCR_ISOLATE   0x0400     /* Isolate data paths from MII */
+#define BMCR_PDOWN     0x0800     /* Enable low power state      */
+#define BMCR_ANENABLE  0x1000     /* Enable auto negotiation     */
+#define BMCR_SPEED100  0x2000     /* Select 100Mbps              */
+#define BMCR_LOOPBACK  0x4000     /* TXD loopback bits           */
+#define BMCR_RESET     0x8000     /* Reset to default state      */
+#define BMCR_SPEED10   0x0000     /* Select 10Mbps               */
+
+#define GMAC_TEST_TIMES 16
+
+/********************* Private Structure Definition **************************/
+/* GMAC consumer config data. */
+struct GMAC_ETH_CONFIG {
+    struct GMAC_HANDLE instance;
+    const struct HAL_GMAC_DEV *halDev;
+    eGMAC_PHY_Interface mode;
+    uint32_t speed;
+    uint32_t maxSpeed;
+    uint16_t phyAddr;
+
+    bool extClk;
+
+    /* phy reset gpio */
+    struct GPIO_REG *resetGpioBank;
+    ePINCTRL_GPIO_PINS resetGpioNum;
+    uint32_t resetDelayMs[3];
+
+    int32_t txDelay;
+    int32_t rxDelay;
+
+    struct GMAC_Desc *txDescs;
+    struct GMAC_Desc *txDescs_dma;
+    struct GMAC_Desc *rxDescs;
+    struct GMAC_Desc *rxDescs_dma;
+
+    uint8_t *txBuff;
+    uint8_t *txBuff_dma;
+    uint8_t *rxBuff;
+    uint8_t *rxBuff_dma;
+
+    /* MAC address info, hw address */
+    uint8_t macAddr[6];
+};
+
+/********************* Private Variable Definition ***************************/
+
+
+static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff  };
+
+#if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568)
+static struct GMAC_ETH_CONFIG ethConfigTable[] =
+{
+    {
+        .halDev = &g_gmac0Dev,
+        .mode = PHY_INTERFACE_MODE_RGMII,
+        .maxSpeed = 1000,
+        .phyAddr = 1,
+
+        .extClk = false,
+
+        .resetGpioBank = GPIO3,
+        .resetGpioNum = GPIO_PIN_A4,
+        .resetDelayMs = { 0, 20, 100 },
+
+        .txDelay = 0x2f,
+        .rxDelay = 0x00,
+    },
+
+
+    // {
+    //     .halDev = &g_gmac1Dev,
+    //     .mode = PHY_INTERFACE_MODE_RGMII,
+    //     .maxSpeed = 1000,
+    //     .phyAddr = 1,
+
+    //     .extClk = false,
+
+    //     .resetGpioBank = GPIO4,
+    //     .resetGpioNum = GPIO_PIN_B6,
+    //     .resetDelayMs = { 0, 20, 100 },
+
+    //     .txDelay = 0x4f,
+    //     .rxDelay = 0x26,
+    // },
+};
+#endif
+
+
+
+
+#endif
+
+/********************* Private Function Definition ***************************/
+
+static void Dump_Hex(char *message, uint8_t *ptr, uint16_t buflen)
+{
+    unsigned char *buf = (unsigned char *)ptr;
+    int i, j;
+
+    printf("%s package at %p, len: %d: \n", message, ptr, buflen);
+    for (i = 0; i < buflen; i += 16) {
+        printf("%08X: ", i);
+
+        for (j = 0; j < 16; j++) {
+            if (i + j < buflen) {
+                printf("%02X ", buf[i + j]);
+            } else {
+                printf("   ");
+            }
+        }
+        printf(" ");
+
+        for (j = 0; j < 16; j++) {
+            if (i + j < buflen) {
+                printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+            }
+        }
+        printf("\n");
+    }
+}
+
+static void print_desc(struct GMAC_HANDLE *pGMAC)
+{
+    struct GMAC_Desc *desc;
+    int nIndex;
+
+    printf("\n");
+
+    if (pGMAC->rxDescs) {
+        desc = pGMAC->rxDescs;
+        for (nIndex = 0; nIndex < pGMAC->rxSize; nIndex++) {
+            desc = pGMAC->rxDescs + nIndex;
+            printf("rx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n",
+                   nIndex, (uint64_t)desc, desc->des0, desc->des1, desc->des2, desc->des3);
+        }
+    }
+
+    if (pGMAC->txDescs) {
+        desc = pGMAC->txDescs;
+        for (nIndex = 0; nIndex < pGMAC->txSize; nIndex++) {
+            desc = pGMAC->txDescs + nIndex;
+            printf("tx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n",
+                   nIndex, (uint64_t)desc, desc->des0, desc->des1, desc->des2, desc->des3);
+        }
+    }
+}
+
+static void Dump_Regs(struct GMAC_HANDLE *pGMAC)
+{
+    uint32_t *reg = (uint32_t *)pGMAC->pReg;
+    int i;
+
+    printf("\n");
+
+    for (i = 0; i < (0x200 / 0x4); i++) {
+        printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10,
+               *((volatile const uint32_t *)(reg + 0x4 * i)), *(volatile const uint32_t *)((reg + 0x4 * i + 1)),
+               *((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3)));
+    }
+
+    reg = reg + 0x1000 / 4;
+
+    for (i = 0; i < (0x100 / 0x4); i++) {
+        printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10 + 0x1000,
+               *((volatile const uint32_t *)(reg + 0x4 * i)), *((volatile const uint32_t *)(reg + 0x4 * i + 1)),
+               *((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3)));
+    }
+}
+
+static void PHY_Dump(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
+{
+    int data, i;
+
+    for (i = 0; i < 32; i++) {
+        data = HAL_GMAC_MDIORead(pGMAC, eth->phyAddr, i);
+        if (data < 0) {
+            printf("phy_dump: %d --> faild\n", i);
+            break;
+        }
+
+        if (i % 8 == 7) {
+            printf("%d --> %08X\n ", i, data);
+        } else {
+            printf("%d --> %08X\n\n", i, data);
+        }
+    }
+    printf("\n");
+}
+
+static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config)
+{
+    if (config->resetGpioBank) {
+        HAL_GPIO_SetPinDirection(config->resetGpioBank,
+                                 config->resetGpioNum,
+                                 GPIO_OUT);
+        HAL_GPIO_SetPinLevel(config->resetGpioBank,
+                             config->resetGpioNum,
+                             GPIO_HIGH);
+        HAL_DelayMs(config->resetDelayMs[0]);
+        HAL_GPIO_SetPinLevel(config->resetGpioBank,
+                             config->resetGpioNum,
+                             GPIO_LOW);
+        HAL_DelayMs(config->resetDelayMs[1]);
+        HAL_GPIO_SetPinLevel(config->resetGpioBank,
+                             config->resetGpioNum,
+                             GPIO_HIGH);
+        HAL_DelayMs(config->resetDelayMs[2]);
+    }
+}
+
+static inline void NET_Random_ETHAddr(uint8_t *addr)
+{
+    addr[0] = 0xe6;
+    addr[1] = 0x47;
+    addr[2] = 0xcd;
+    addr[3] = 0x20;
+    addr[4] = 0xcf;
+    addr[5] = 0xd9;
+}
+
+static inline void NET_Random_Package(uint8_t *addr, uint16_t len)
+{
+    unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff;
+    uint16_t i;
+
+    for (i = 0; i < len; i++) {
+        addr[i] = rand();
+    }
+}
+
+static void PHY_Update_Links(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC,
+                             uint8_t id)
+{
+    HAL_Status status;
+
+    status = HAL_GMAC_PHYStartup(pGMAC);
+    if (status) {
+        printf("HAL_PHY_Startup() failed: %d\n", status);
+
+        return;
+    }
+    HAL_DelayMs(10000);
+
+    status = HAL_GMAC_PHYUpdateLink(pGMAC);
+    if (status == HAL_OK) {
+        if (pGMAC->phyStatus.link) {
+            status = HAL_GMAC_PHYParseLink(pGMAC);
+            if (PHY_SPEED_1000M == pGMAC->phyStatus.speed) {
+                printf("Phy%d: 1000M link speed\n", id);
+            } else if (PHY_SPEED_100M == pGMAC->phyStatus.speed) {
+                printf("Phy%d: 100M link speed\n", id);
+            } else {
+                printf("Phy%d: 10M link speed\n", id);
+            }
+
+            if (PHY_DUPLEX_HALF == pGMAC->phyStatus.duplex) {
+                printf("Phy%d: half dumplex\n", id);
+            } else {
+                printf("Phy%d: full dumplex\n", id);
+            }
+
+            if (pGMAC->phyStatus.pause) {
+                printf("Phy%d: flow control rx/tx\n", id);
+            } else {
+                printf("Phy%d: flow control off\n", id);
+            }
+
+            status = HAL_GMAC_AdjustLink(pGMAC, eth->txDelay, eth->rxDelay);
+            if (status != HAL_OK) {
+                printf("HAL_GMAC_AdjustLink() failed: %d\n", status);
+            }
+
+            printf("Phy%d: link up.\n", id);
+        } else {
+            printf("Phy%d: link down.\n", id);
+        }
+    }
+}
+
+/* interrupt service routine polling */
+static HAL_Status GMAC_ETH_IRQ(struct GMAC_HANDLE *pGMAC)
+{
+    HAL_Status status;
+
+    /* enter interrupt */
+    /* rt_interrupt_enter(); */
+    status = HAL_GMAC_IRQHandler(pGMAC);
+
+    if (status & DMA_HANLE_RX) {
+        /* a frame has been received */
+        return 1;
+    }
+
+    return 0;
+    /* leave interrupt */
+    /* rt_interrupt_leave(); */
+}
+
+
+static void *malloc_align(size_t size, size_t align, uintptr_t va, uintptr_t *pa)
+{
+    void *align_ptr;
+    // void *ptr;
+    size_t align_size;
+
+    /* align the alignment size to 4 byte */
+    align = ((align + 0x03) & ~0x03);
+
+    /* get total aligned size */
+    align_size = ((size + 0x03) & ~0x03);
+    /* allocate memory block from heap */
+    // ptr = malloc(align_size);
+
+    if (naive_mmap(&va, pa, align_size, true) < 0){
+        HAL_DBG("Alloc failed\n");
+    }
+    // printf("%p,%p\n",(void *)va, *pa);
+    // void* ptr = (void *)va;
+    // if (ptr != 0) {
+    //     /* the allocated memory block is aligned */
+    //     if (((uint64_t)ptr & (align - 1)) == 0) {
+    //         align_ptr = (void *)((uint64_t)ptr + align);
+    //     } else {
+    //         align_ptr = (void *)(((uint64_t)ptr + (align - 1)) & ~(align - 1));
+    //     }
+
+    //     /* set the pointer before alignment pointer to the real pointer */
+    //     *((uint64_t *)((uint64_t)align_ptr - sizeof(void *))) = (uint64_t)ptr;
+
+    //     ptr = align_ptr;
+    // }
+
+    return (void *)va;
+}
+
+static void free_align(void *ptr)
+{
+    void *real_ptr;
+
+    real_ptr = (void *)*(uint64_t *)((uint64_t)ptr - sizeof(void *));
+    free(real_ptr);
+
+}
+
+/********************* Public Function Definition ****************************/
+
+static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC,
+                                 uint16_t len)
+{
+    uint8_t *ptr = NULL;
+    HAL_Status status;
+
+    if (!pGMAC->phyStatus.link) {
+        HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link);
+        return -1;
+    }
+
+    /* Check the frame length. */
+    if (len > HAL_GMAC_MAX_FRAME_SIZE) {
+        return -1;
+    }
+
+    ptr = (uint8_t *)HAL_GMAC_GetTXBuffer(pGMAC);
+    HAL_DBG("txPtr:%p\n", ptr);
+    memcpy(ptr, dstAddr, 6);
+    memcpy(ptr + 6, eth->macAddr, 6);
+    ptr[12] = 0x40;
+    ptr[13] = 0x06;
+    ptr[14] = 0x00;
+    ptr[15] = 0x01;
+    NET_Random_Package(ptr + 16, len - 16);
+
+    if (len > 60) {
+        /* index */
+        ptr[50] = pGMAC->txDescIdx;
+    }
+
+    /* dump packages */
+    Dump_Hex("Tx", ptr, len);
+
+    // HAL_DCACHE_CleanByRange((uint64_t)ptr, len);
+    uint8_t * ptr_dma = (uint8_t *)HAL_GMAC_GetTXBufferDMA(pGMAC);
+    status = HAL_GMAC_Send(pGMAC, ptr_dma, len);
+    if (status) {
+        printf("GMAC send failed: %d\n", status);
+    }
+    
+    return status;
+}
+
+static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
+{
+    uint8_t *ptr = NULL;
+    HAL_Status status;
+    int32_t size;
+
+    if (!pGMAC->phyStatus.link) {
+        HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link);
+        return -1;
+    }
+
+    status = GMAC_ETH_IRQ(pGMAC);
+    ptr = HAL_GMAC_Recv(pGMAC, &size);
+    while (status && ptr) {
+        if (size > 0 && ptr) {
+            /* dump packages */
+            Dump_Hex("Rx", ptr, size);
+            // HAL_DCACHE_InvalidateByRange((uint64_t)ptr, size);
+            HAL_GMAC_CleanRX(pGMAC);
+        } else {
+            printf("GMAC recv failed: %ld\n", size);
+
+            return -1;
+        }
+        ptr = HAL_GMAC_Recv(pGMAC, &size);
+    }
+    return 0;
+}
+
+static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
+{   
+
+    uintptr_t tx_va = 0x1000000000, tx_pa = 0;
+    if (naive_mmap(&tx_va, &tx_pa, GMAC_DESC_TX_SIZE, true) < 0){
+        HAL_DBG("TX Desc alloc failed\n");
+    }
+    eth->txDescs = (struct GMAC_Desc *)0x1000000000;
+    eth->txDescs_dma = (struct GMAC_Desc *)tx_pa;
+
+    uintptr_t rx_va = 0x1000400000, rx_pa = 0;
+    if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){
+        HAL_DBG("RX Desc alloc failed\n");
+    }
+    eth->rxDescs = (struct GMAC_Desc *)0x1000400000;
+    eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa;
+
+    if (!eth->rxDescs || !eth->txDescs_dma ||
+        !eth->txDescs || !eth->txDescs_dma){
+        return -1;
+    }
+        
+    HAL_DBG("rx:%p, %p\n",eth->rxDescs, eth->rxDescs_dma);
+    HAL_DBG("tx:%p, %p\n",eth->txDescs, eth->txDescs_dma);
+
+    
+    uintptr_t txbuf_va = 0x1000800000, txbuf_pa = 0;
+    eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN, txbuf_va, &txbuf_pa);
+    eth->txBuff = (void *)0x1000800000;
+    eth->txBuff_dma = (void *)txbuf_pa;
+
+    uintptr_t rxbuf_va = 0x1000c00000, rxbuf_pa = 0;
+    eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa);
+    eth->rxBuff = (void *)0x1000c00000;
+    eth->rxBuff_dma = (void *)rxbuf_pa;
+    
+    if (!eth->rxBuff || !eth->txBuff ||
+        !eth->rxBuff_dma || !eth->txBuff_dma){   
+        return -1;
+    }
+    HAL_DBG("rx_buff:%p,%p\n",eth->rxBuff, eth->rxBuff_dma);
+    HAL_DBG("tx_buff:%p,%p,\n",eth->txBuff, eth->txBuff_dma);
+    memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE);
+    memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE);
+    memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE);
+    // HAL_DCACHE_InvalidateByRange((uint64_t)eth->rxBuff, GMAC_RX_BUFFER_SIZE);
+    memset(eth->txBuff, 0, GMAC_TX_BUFFER_SIZE);
+    // HAL_DCACHE_CleanByRange((uint64_t)eth->txBuff, GMAC_TX_BUFFER_SIZE);
+
+    HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxDescs_dma, eth->rxBuff, eth->rxBuff_dma, GMAC_DESCRIPTORS_RX);
+    HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txDescs_dma, eth->txBuff, eth->txBuff_dma, GMAC_DESCRIPTORS_TX);
+
+    print_desc(pGMAC);
+
+    return 0;
+}
+
+static HAL_Status GMAC_Init(uint8_t id)
+{
+    struct GMAC_ETH_CONFIG *eth;
+    struct GMAC_HANDLE *pGMAC;
+    const struct HAL_GMAC_DEV *gmacDev;
+    struct GMAC_PHY_Config config;
+    eGMAC_PHY_Interface interface;
+    HAL_Status status;
+    uint32_t freq;
+
+    HAL_ASSERT(id < GMAC_BUS_MAX);
+
+    eth = &ethConfigTable[id];
+    if (!eth) {
+        return HAL_ERROR;
+    }
+
+    pGMAC = &eth->instance;
+    gmacDev = eth->halDev;
+
+    /* MAC init */
+    interface = eth->mode;
+
+    if (interface == PHY_INTERFACE_MODE_RGMII) {
+        HAL_CRU_ClkSetFreq(gmacDev->clkID125M, 125000000);
+    } else {
+        HAL_CRU_ClkSetFreq(gmacDev->clkID50M, 50000000);
+    }
+
+    freq = HAL_CRU_ClkGetFreq(gmacDev->pclkID);
+    HAL_GMAC_Init(pGMAC, gmacDev->pReg, freq, interface, eth->extClk);
+
+    /* PHY Init */
+    config.speed = eth->speed;
+    config.maxSpeed = eth->maxSpeed;
+    config.duplexMode = PHY_DUPLEX_FULL;
+    config.neg = PHY_AUTONEG_ENABLE;
+    config.interface = interface;
+    config.phyAddress = eth->phyAddr;
+    config.features = 0;
+    status = HAL_GMAC_PHYInit(pGMAC, &config);
+    if (status) {
+        printf("HAL_PHY_Init() failed: %d\n", status);
+
+        return status;
+    }
+
+    /* MAC Address */
+    NET_Random_ETHAddr(eth->macAddr);
+    HAL_GMAC_WriteHWAddr(&eth->instance, eth->macAddr);
+
+    return 0;
+}
+
+/*************************** GMAC TEST ****************************/
+
+#ifdef SOC_RK3568
+/**
+ * @brief  Config iomux for GMAC0
+ */
+static void GMAC0_Iomux_Config(void)
+{
+    /* GMAC0 iomux */
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_B6, /* gmac0_rxd0 */
+                         PIN_CONFIG_MUX_FUNC1);
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_C3 | /* gmac0_mdc */
+                         GPIO_PIN_C4 | /* gmac0_mdio */
+                         GPIO_PIN_C0 | /* gmac0_rxdvcrs */
+                         GPIO_PIN_B7 | /* gmac0_rxd1 */
+                         GPIO_PIN_A3 | /* gmac0_rxd2 */
+                         GPIO_PIN_A4 | /* gmac0_rxd3 */
+                         GPIO_PIN_A6 | /* gmac0_txd2 */
+                         GPIO_PIN_A7 | /* gmac0_txd3 */
+                         GPIO_PIN_A5,  /* gmac0_rxclk */
+                         PIN_CONFIG_MUX_FUNC2);
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_B3 | /* gmac0_txd0 */
+                         GPIO_PIN_B4 | /* gmac0_txd1 */
+                         GPIO_PIN_B5,  /* gmac0_txen */
+                         PIN_CONFIG_MUX_FUNC1 | PIN_CONFIG_DRV_LEVEL2);
+
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_A7 | /* gmac0_txd3 */
+                         GPIO_PIN_A6,  /* gmac0_txd2 */
+                         PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL2);
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,   /* gmac0_txclk */
+                         GPIO_PIN_B0,
+                         PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL1);
+
+}
+#endif
+
+
+static void GMAC_Iomux_Config(uint8_t id)
+{
+    // if (id == 1) {
+    //     GMAC1_M1_Iomux_Config();
+    // } else if (id == 0) {
+        GMAC0_Iomux_Config();
+    // }
+}
+
+
+/*************************** GMAC TEST MAIN ****************************/
+
+#include "usyscall.h"
+
+// IPC_SERVER_INTERFACE(Ipc_intr, 1);
+// IPC_SERVER_REGISTER_INTERFACES(IpIntrHandler, 1, Ipc_intr);
+
+int main() {
+    struct GMAC_ETH_CONFIG *eth;
+    struct GMAC_HANDLE *pGMAC;
+    int32_t bus, num = 0, i;
+
+    HAL_DBG("GMAC Test:\n");
+
+    num = sizeof(ethConfigTable) / sizeof(struct GMAC_ETH_CONFIG);
+    HAL_DBG("GMAC Num: %ld\n", num);
+    for (bus = 0; bus < num; bus++) {
+        eth = &ethConfigTable[bus];
+        HAL_DBG("new pGmac\n");
+        if (eth) {
+            pGMAC = &eth->instance;
+        } else {
+            return -1;
+        }
+
+        if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 0x10000, true)) {
+            printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0);
+            exit(1);
+        }
+        
+        if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 0x10000, true)) {
+            printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2);
+            exit(1);
+        }
+        
+        if (!mmap(0x2000000000ULL + GPIO3_BASE, GPIO3_BASE, 0x10000, true)) {
+            printf("eth_hal: mmap GPIO3(%8x) failed\n", GPIO3);
+            exit(1);
+        }
+
+        if (!mmap(0x2000000000ULL + GRF_BASE, GRF_BASE, 0x50000, true)) {
+            printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
+            exit(1);
+        }
+        
+        if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 0x10000, true)) {
+            printf("eth_hal: mmap CRU(%8x) failed\n", CRU);
+            exit(1);
+        }
+        if (!mmap(0x2000000000ULL + TIMER5_BASE, TIMER5_BASE, 32, true)) {
+            printf("eth_hal: mmap TIMER5(%8x) failed\n", TIMER5);
+            exit(1);
+        }
+        if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 0x10000, true)) {
+            printf("eth_hal: mmap PMUCRU(%8x) failed\n", PMUCRU);
+            exit(1);
+        }
+
+        HAL_TIMER_SysTimerInit(TIMER5);
+
+        /* ionmux */
+        GMAC_Iomux_Config(bus);
+        HAL_CRU_ClkEnable(eth->halDev->pclkGateID);
+        HAL_CRU_ClkEnable(eth->halDev->clkGateID125M);
+        HAL_CRU_ClkEnable(eth->halDev->clkGateID50M);
+        
+        /* Register irq */
+        // register_irq(eth->halDev->irqNum, );
+        /* PHY reset */
+        GMAC_PHY_Reset(eth);
+        
+        /* GMAC Init */
+        GMAC_Init(bus);
+
+        GMAC_Memory_Init(eth, pGMAC);
+        
+        /* Enable GMAC and DMA transmission and reception */
+        HAL_GMAC_Start(pGMAC, eth->macAddr);
+
+        /* Update links information */
+        PHY_Update_Links(eth, pGMAC, bus);
+    
+        /* Dump MAC Regs */
+        Dump_Regs(pGMAC);
+
+        /* Dump PHY Regs */
+        // PHY_Dump(eth, pGMAC);
+        for (i = 0; i < GMAC_TEST_TIMES; i++) {
+            HAL_DBG("TEST %d\n", i);
+
+            /* GMAC Send 64 bytes */
+            HAL_DBG("--------------GMAC_Send_Test  START!--------------\n");	
+            GMAC_Send_Test(eth, pGMAC, 64);
+	        HAL_DBG("--------------GMAC_Send_Test  END!--------------\n");	
+           
+            HAL_DelayMs(1000);
+            print_desc(pGMAC);
+            
+            /* GMAC Recv */
+            HAL_DBG("--------------GMAC_Recv_Test  START! -------------- \n");
+            GMAC_Recv_Test(pGMAC);
+            HAL_DBG("--------------GMAC_Recv_Test  END!!-------------- \n");
+
+            HAL_DelayMs(1000);
+            Dump_Regs(pGMAC);
+        }
+        HAL_CRU_ClkDisable(eth->halDev->pclkGateID);
+        HAL_CRU_ClkDisable(eth->halDev->clkGateID125M);
+        HAL_CRU_ClkDisable(eth->halDev->clkGateID50M);
+
+        // free_align(eth->txBuff);
+        // free_align(eth->rxBuff);
+        HAL_DBG("done\n");
+    }
+    exit(0);
+    return 0;
+}
+
+
+// typedef void (*isr_handler_t)(int vector, void *param);
+// typedef void (*NVIC_IRQHandler)(void);
+
+// isr_handler_t interrupt_install(int              vector,
+//         isr_handler_t handler,
+//         void            *param,
+//         const char      *name)
+// {
+
+//     HAL_NVIC_SetIRQHandler(vector, (NVIC_IRQHandler)handler);
+//     return handler;
+// }
+

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_base.h

@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup HAL_BASE
+ *  @{
+ */
+
+#ifndef _HAL_BASE_H_
+#define _HAL_BASE_H_
+
+#include "hal_conf.h"
+#include "hal_driver.h"
+#include "hal_debug.h"
+
+/***************************** MACRO Definition ******************************/
+
+/** @defgroup HAL_BASE_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+/** enter markrom usb upgrade */
+#define SYS_UPGRADE_FLAG (0xEF08A53C)
+/** enter loader usb upgrade */
+#define LDR_UPGRADE_FLAG (0x5242C301)
+
+#define IS_TICKFREQ(f) (((f) == HAL_TICK_FREQ_1KHZ)  || ((f) == HAL_TICK_FREQ_100HZ) || ((f) == HAL_TICK_FREQ_10HZ))
+
+/***************************** Structure Definition **************************/
+typedef enum {
+    HAL_TICK_FREQ_10HZ    = 100U,    /**< 10 ticks per second, so it's 100ms/tick */
+    HAL_TICK_FREQ_100HZ   = 10U,     /**< 100 ticks per second, so it's 10ms/tick */
+    HAL_TICK_FREQ_1KHZ    = 1U,      /**< 1000 ticks per second, so it's 1ms/tick */
+    HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} eHAL_tickFreq;
+
+/** @} */
+
+/***************************** Function Declare ******************************/
+/** @defgroup HAL_BASE_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+
+HAL_Status HAL_Init(void);
+HAL_Status HAL_DeInit(void);
+HAL_Status HAL_InitTick(uint32_t tickPriority);
+HAL_Status HAL_IncTick(void);
+uint32_t HAL_GetTick(void);
+HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq);
+eHAL_tickFreq HAL_GetTickFreq(void);
+
+HAL_Status HAL_DelayUs(uint32_t us);
+HAL_Status HAL_DelayMs(uint32_t ms);
+HAL_Status HAL_CPUDelayUs(uint32_t us);
+HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource);
+
+uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder);
+uint64_t HAL_GetSysTimerCount(void);
+
+void HAL_CPU_EnterIdle(void);
+#if defined(HAL_CPU_USAGE_ENABLED)
+uint32_t HAL_GetCPUUsage(void);
+#endif
+
+/** @} */
+
+/********************* Public Function Definition ***************************/
+/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  uint64_t numerator / uint32_t denominator
+ * @param  numerator
+ * @param  denominator
+ * @return uint64_t result
+ */
+static inline uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator)
+{
+    return HAL_DivU64Rem(numerator, denominator, NULL);
+}
+
+/**
+ * @brief  uint32_t numerator / uint32_t denominator rounded to nearest integer
+ * @param  numerator
+ * @param  denominator
+ * @return uint32_t result rounded to nearest integer
+ */
+static inline uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator)
+{
+    return (numerator + (denominator / 2)) / denominator;
+}
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/3568/3568/include/hal_bsp.h

@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __BSP_H__
+#define __BSP_H__
+
+#include "hal_base.h"
+
+/***************************** MACRO Definition ******************************/
+
+/***************************** Structure Definition **************************/
+#ifdef HAL_PL330_MODULE_ENABLED
+extern struct HAL_PL330_DEV g_pl330Dev0;
+extern struct HAL_PL330_DEV g_pl330Dev1;
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+extern const struct HAL_SPI_DEV g_spi0Dev;
+extern const struct HAL_SPI_DEV g_spi1Dev;
+extern const struct HAL_SPI_DEV g_spi2Dev;
+extern const struct HAL_SPI_DEV g_spi3Dev;
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+extern const struct HAL_UART_DEV g_uart0Dev;
+extern const struct HAL_UART_DEV g_uart1Dev;
+extern const struct HAL_UART_DEV g_uart2Dev;
+extern const struct HAL_UART_DEV g_uart3Dev;
+extern const struct HAL_UART_DEV g_uart4Dev;
+extern const struct HAL_UART_DEV g_uart5Dev;
+extern const struct HAL_UART_DEV g_uart6Dev;
+extern const struct HAL_UART_DEV g_uart7Dev;
+extern const struct HAL_UART_DEV g_uart8Dev;
+extern const struct HAL_UART_DEV g_uart9Dev;
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+extern const struct HAL_I2C_DEV g_i2c0Dev;
+extern const struct HAL_I2C_DEV g_i2c1Dev;
+extern const struct HAL_I2C_DEV g_i2c2Dev;
+extern const struct HAL_I2C_DEV g_i2c3Dev;
+extern const struct HAL_I2C_DEV g_i2c4Dev;
+extern const struct HAL_I2C_DEV g_i2c5Dev;
+#endif
+
+#ifdef HAL_FSPI_MODULE_ENABLED
+extern struct HAL_FSPI_HOST g_fspi0Dev;
+#endif
+#ifdef HAL_CANFD_MODULE_ENABLED
+extern const struct HAL_CANFD_DEV g_can0Dev;
+extern const struct HAL_CANFD_DEV g_can1Dev;
+extern const struct HAL_CANFD_DEV g_can2Dev;
+#endif
+
+#ifdef HAL_GMAC_MODULE_ENABLED
+extern const struct HAL_GMAC_DEV g_gmac0Dev;
+extern const struct HAL_GMAC_DEV g_gmac1Dev;
+#endif
+
+#ifdef HAL_PCIE_MODULE_ENABLED
+extern struct HAL_PCIE_DEV g_pcieDev;
+#endif
+
+#ifdef HAL_PWM_MODULE_ENABLED
+extern const struct HAL_PWM_DEV g_pwm0Dev;
+extern const struct HAL_PWM_DEV g_pwm1Dev;
+extern const struct HAL_PWM_DEV g_pwm2Dev;
+extern const struct HAL_PWM_DEV g_pwm3Dev;
+#endif
+/***************************** Function Declare ******************************/
+void BSP_Init(void);
+
+#endif