From 7b5369a1f3cd6f40276fa44165c460020ca26579 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 13 Sep 2024 15:31:22 +0800 Subject: [PATCH] Modify DWC3 reg size to aligned to 4096 --- .../services/drivers/usb/components/port/xhci/usb_hc_xhci.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h index f91b3323f..4dbd3fe10 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h @@ -60,7 +60,11 @@ extern "C" { #define USB3_0_BASE_ADDR 0xFCC00000 #define USB3_1_BASE_ADDR 0xFD000000 #define USB3_ADDR_OFFSET_UPPER_BOUND 0x08000 -#define USB3_DWC3_ADDR_GAP 0x0C00 +/* + * The size of all DWC3 registers (including OTG regs) is 0xC00. However, the XiZi AIOT requires the I/O memory size to be aligned to 4096. + * So we define USB3_DWC3_ADDR_GAP as 0x01000. + */ +#define USB3_DWC3_ADDR_GAP 0x01000 #define USB3_VIRADDR_BASE 0x0000002000000000ULL #define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE