forked from xuos/xiuos
support zynq7000-zc702
This commit is contained in:
TXuian
parent
6bdf5cc0ce
commit
5f9478251b
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@ -4,7 +4,7 @@ MAKEFLAGS += --no-print-directory
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.PHONY:COMPILE_APP COMPILE_KERNEL
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riscv_support :=
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arm_support += imx6q-sabrelite
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arm_support += imx6q-sabrelite zynq7000-zc702
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emulator_support +=
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support := $(riscv_support) $(arm_support) $(emulator_support)
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SRC_DIR :=
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@ -31,14 +31,14 @@ MAKEFILES =$(KERNEL_ROOT)/.config
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export BSP_ROOT ?= $(KERNEL_ROOT)/services/boards/$(BOARD)
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export UBIQUITOUS_ROOT ?= ..
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include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/config.mk
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include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/config.mk
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export BSP_BUILD_DIR := $(KERNEL_ROOT)
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export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools
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export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh
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export CPPPATHS
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export SRC_APP_DIR := ../../APP_Framework
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export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel testing
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export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel
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export SRC_DIR := $(SRC_KERNEL_DIR)
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export LIBCC
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@ -123,12 +123,10 @@ clean:
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@echo Clean target and build_dir
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@rm -rf build
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@rm -rf temp.txt
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@rm -rf services/boards/imx6q-sabrelite/*.o
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@rm -rf services/boards/imx6q-sabrelite/*.asm
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@rm -rf services/boards/imx6q-sabrelite/bin
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@rm -rf services/app/bin
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@rm -rf services/tools/mkfs/mkfs
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@rm -rf services/boards/imx6q-sabrelite/fs.img
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@rm -rf services/boards/imx6q-sabrelite/user.map
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@rm -rf services/app/fs.img
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@rm -rf services/app/user.map
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distclean:
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@echo Clean all configuration
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@ -1,808 +0,0 @@
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/hardkernel_init.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/hardkernel_init.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/kern_init.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer_mem_chunk.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/list.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/spinlock.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/cache/cache_common_ope.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/clock_common_op.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/trap_common.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/uart/uart_common_ope.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/assert.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/log.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/core.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/boot.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/context_switch.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/context_switch.S
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/ivt.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/ivt.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/hab_defines.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/dcd.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/dcd.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/hab_defines.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/soc_memory_map.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/iomux_register.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/registers.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/regs.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/imx6q_lowlevel_init.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/imx6q_lowlevel_init.S \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/soc_memory_map.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/cortexA9.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/cortexA9.S
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/ccm_pll.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/ccm_pll.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/soc_memory_map.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsccm.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/regs.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/mmio_access.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsccmanalog.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsgpc.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsgpt.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/regsuart.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/ccm_pll.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/clock.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/clock.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/ccm_pll.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/gpt.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/timer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/clock_common_op.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer_mem_chunk.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/list.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/spinlock.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/gpt.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/gpt.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/soc_memory_map.h \
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||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/ccm_pll.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsgpt.h \
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||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/regs.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/mmio_access.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/timer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/gpt.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/trap_common.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer_mem_chunk.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/list.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/spinlock.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/bootmmu.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/bootmmu.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/mmu.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/page_table_entry.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/mmio_access.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/mmu.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/mmu.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/mmu.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/page_table_entry.h \
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||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/cache/cache_common_ope.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer_mem_chunk.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/list.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/spinlock.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/trap_common.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/pagetable_attr.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/pagetable_attr.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/mmu.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/page_table_entry.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer_mem_chunk.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/list.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/spinlock.h
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/trap_common.o: \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trap_common.c \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv2/gicv2_common_opa.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/mmio_access.h \
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/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
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||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/trap_common.h \
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|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/trap_common.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/share_page.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/task.h
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/build/softkernel_init.o: \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/init/softkernel_init.c \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/kern_init.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/kernel_actracer/actracer_mem_chunk.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/list.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/intr/spinlock.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/assert.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/log.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/kalloc.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/pagetable.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/mmu.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/page_table_entry.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/mmu/mmu_common.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/task.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include/cortex_a9.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/object_allocator.h \
|
||||
/home/tuxian/work/microkernel/micro_kernel/XiZi_AIoT/softkernel/include/share_page.h
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
SRC_DIR := preboot_for_nxp_imx6q_sabrelite
|
||||
SRC_FILES := boot.S context_switch.S core.c
|
||||
SRC_DIR := preboot_for_$(BOARD)
|
||||
SRC_FILES := context_switch.S core.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := ivt.c dcd.c imx6q_lowlevel_init.S cortexA9.S boot.S
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -2,8 +2,8 @@ export CROSS_COMPILE ?= arm-none-eabi-
|
|||
export DEVICE = -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp
|
||||
export CFLAGS := $(DEVICE) -Wall -O0 -g -gdwarf-2
|
||||
export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
|
||||
# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/nxp_imx6q_sabrelite.lds
|
||||
export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/nxp_imx6q_sabrelite.lds
|
||||
# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
|
||||
export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
|
||||
export CXXFLAGS :=
|
||||
|
||||
ifeq ($(CONFIG_LIB_MUSLLIB), y)
|
||||
|
|
@ -14,7 +14,5 @@ endif
|
|||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DCHIP_MX6DQ
|
||||
|
||||
export USING_NEWLIB =1
|
||||
export USING_VFS = 1
|
||||
export ARCH = arm
|
||||
export ARCH_ARMV = armv7-a
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
SRC_FILES := ivt.c dcd.c imx6q_lowlevel_init.S cortexA9.S
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := boot.S cpu_init.S xil-crt0.S cortexA9.S
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,248 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file boot.S
|
||||
*
|
||||
* This file contains the initial startup code for the Cortex A9 processor
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 10/20/09 Initial version
|
||||
* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
|
||||
* register settings.
|
||||
* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
|
||||
* register settings.
|
||||
* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
|
||||
* performance. Changed the property of the ".boot"
|
||||
* section.
|
||||
* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
|
||||
* Register settings
|
||||
* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
|
||||
* value of 0x00020202. Fix for CR 697094 (SI#687034).
|
||||
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
|
||||
* 'xil_errata.h' for errata description
|
||||
* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
|
||||
* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
|
||||
* MMU is enabled
|
||||
* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
|
||||
* caches and TLB, enable MMU and caches, then enable SMP
|
||||
* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
|
||||
* is done later.
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_errata.h"
|
||||
|
||||
.globl MMUTable
|
||||
.global _boot_start
|
||||
.global stacks_start
|
||||
.global _vector_jumper
|
||||
|
||||
|
||||
|
||||
.set SYS_stack, stacks_start
|
||||
.set vector_base, _vector_jumper
|
||||
.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
|
||||
|
||||
/* this initializes the various processor modes */
|
||||
_boot_start:
|
||||
#if XPAR_CPU_ID==0
|
||||
/* only allow cpu0 through */
|
||||
mrc p15,0,r1,c0,c0,5
|
||||
and r1, r1, #0xf
|
||||
cmp r1, #0
|
||||
beq OKToRun
|
||||
EndlessLoop0:
|
||||
wfe
|
||||
b EndlessLoop0
|
||||
|
||||
#elif XPAR_CPU_ID==1
|
||||
/* only allow cpu1 through */
|
||||
mrc p15,0,r1,c0,c0,5
|
||||
and r1, r1, #0xf
|
||||
cmp r1, #1
|
||||
beq OKToRun
|
||||
EndlessLoop1:
|
||||
wfe
|
||||
b EndlessLoop1
|
||||
#endif
|
||||
|
||||
OKToRun:
|
||||
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
|
||||
and r5, r0, #0x00f00000
|
||||
and r6, r0, #0x0000000f
|
||||
orr r6, r6, r5, lsr #20-4
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_742230
|
||||
cmp r6, #0x22 /* only present up to r2p2 */
|
||||
mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
|
||||
orrle r10, r10, #1 << 4 /* set bit #4 */
|
||||
mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_743622
|
||||
teq r5, #0x00200000 /* only present in r2p* */
|
||||
mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
|
||||
orreq r10, r10, #1 << 6 /* set bit #6 */
|
||||
mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
|
||||
#endif
|
||||
|
||||
/* set VBAR to the _vector_table address in linker script */
|
||||
ldr r0, =vector_base
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
|
||||
/*invalidate scu*/
|
||||
ldr r7, =0xf8f0000c
|
||||
ldr r6, =0xffff
|
||||
str r6, [r7]
|
||||
|
||||
/* Invalidate caches and TLBs */
|
||||
mov r0,#0 /* r0 = 0 */
|
||||
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
|
||||
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
|
||||
mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
|
||||
bl invalidate_dcache /* invalidate dcache */
|
||||
|
||||
/* Disable MMU, if enabled */
|
||||
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
|
||||
bic r0, r0, #0x1 /* clear bit 0 */
|
||||
mcr p15, 0, r0, c1, c0, 0 /* write value back */
|
||||
|
||||
mrs r0, cpsr /* get the current PSR */
|
||||
mvn r1, #0x1f /* set up the system stack pointer */
|
||||
and r2, r1, r0
|
||||
orr r2, r2, #0x13 /* SVC mode */
|
||||
msr cpsr, r2
|
||||
ldr r13,=SYS_stack /* SYS stack pointer */
|
||||
|
||||
/*set scu enable bit in scu*/
|
||||
ldr r7, =0xf8f00000
|
||||
ldr r0, [r7]
|
||||
orr r0, r0, #0x1
|
||||
str r0, [r7]
|
||||
|
||||
mov r0, r0
|
||||
mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
|
||||
orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
|
||||
mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
|
||||
|
||||
/* enable vfp */
|
||||
fmrx r1, FPEXC /* read the exception register */
|
||||
orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
|
||||
fmxr FPEXC, r1 /* write back the exception register */
|
||||
|
||||
mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
|
||||
orr r0, r0, #(0x01 << 11) /* #0x8000 */
|
||||
mcr p15,0,r0,c1,c0,0
|
||||
|
||||
mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
|
||||
orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
|
||||
orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
|
||||
mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
|
||||
|
||||
mrs r0, cpsr /* get the current PSR */
|
||||
bic r0, r0, #0x100 /* enable asynchronous abort exception */
|
||||
msr cpsr_xsf, r0
|
||||
|
||||
|
||||
b _start /* jump to C startup code */
|
||||
and r0, r0, r0 /* no op */
|
||||
|
||||
.Ldone: b .Ldone /* Paranoia: we should never get here */
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* invalidate_dcache - invalidate the entire d-cache by set/way
|
||||
*
|
||||
* Note: for Cortex-A9, there is no cp instruction for invalidating
|
||||
* the whole D-cache. Need to invalidate each line.
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
invalidate_dcache:
|
||||
mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
|
||||
ands r3, r0, #0x7000000
|
||||
mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
|
||||
beq finished
|
||||
mov r10, #0 /* start with level 0 */
|
||||
loop1:
|
||||
add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
|
||||
mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
|
||||
and r1, r1, #7 /* get those 3 bits alone */
|
||||
cmp r1, #2
|
||||
blt skip /* no cache or only instruction cache at this level */
|
||||
mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
|
||||
isb /* isb to sync the change to the CacheSizeID reg */
|
||||
mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
|
||||
and r2, r1, #7 /* extract the line length field */
|
||||
add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
|
||||
ldr r4, =0x3ff
|
||||
ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
|
||||
clz r5, r4 /* r5 is the bit position of the way size increment */
|
||||
ldr r7, =0x7fff
|
||||
ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
|
||||
loop2:
|
||||
mov r9, r4 /* r9 working copy of the max way size (right aligned) */
|
||||
loop3:
|
||||
orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
|
||||
orr r11, r11, r7, lsl r2 /* factor in the index number */
|
||||
mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
|
||||
subs r9, r9, #1 /* decrement the way number */
|
||||
bge loop3
|
||||
subs r7, r7, #1 /* decrement the index */
|
||||
bge loop2
|
||||
skip:
|
||||
add r10, r10, #2 /* increment the cache number */
|
||||
cmp r3, r10
|
||||
bgt loop1
|
||||
|
||||
finished:
|
||||
mov r10, #0 /* swith back to cache level 0 */
|
||||
mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
|
||||
dsb
|
||||
isb
|
||||
|
||||
bx lr
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
export CROSS_COMPILE ?= arm-xilinx-eabi-
|
||||
export DEVICE =
|
||||
export CFLAGS := $(DEVICE) -Wall -O0 -g -std=c11
|
||||
export AFLAGS := -r
|
||||
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/$(BOARD).lds -Wl,--start-group,-lgcc,-lc,--end-group
|
||||
export CXXFLAGS :=
|
||||
|
||||
export ARCH = arm
|
||||
export ARCH_ARMV = armv7-a
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file cortexA9.s
|
||||
* @brief This file contains cortexA9 functions
|
||||
*
|
||||
*/
|
||||
/*************************************************
|
||||
File name: cortexA9.S
|
||||
Description: This file contains cortexA9 functions
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. No modifications
|
||||
*************************************************/
|
||||
|
||||
.code 32
|
||||
.section ".text","ax"
|
||||
|
||||
/*
|
||||
* bool arm_set_interrupt_state(bool enable)
|
||||
*/
|
||||
.global arm_set_interrupt_state
|
||||
.func arm_set_interrupt_state
|
||||
arm_set_interrupt_state:
|
||||
mrs r2,CPSR @ read CPSR (Current Program Status Register)
|
||||
teq r0,#0
|
||||
bicne r1,r2,#0xc0 @ disable IRQ and FIQ
|
||||
orreq r1,r2,#0xc0 @ enable IRQ and FIQ
|
||||
msr CPSR_c,r1
|
||||
tst r2,#0x80
|
||||
movne r0,#0
|
||||
moveq r0,#1
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global cpu_get_current
|
||||
@ int cpu_get_current(void)@
|
||||
@ get current CPU ID
|
||||
.func cpu_get_current
|
||||
cpu_get_current:
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #3
|
||||
BX lr
|
||||
.endfunc @cpu_get_current()@
|
||||
|
||||
.global enable_neon_fpu
|
||||
.func enable_neon_fpu
|
||||
enable_neon_fpu:
|
||||
/* set NSACR, both Secure and Non-secure access are allowed to NEON */
|
||||
MRC p15, 0, r0, c1, c1, 2
|
||||
ORR r0, r0, #(0x3<<10) @ enable fpu/neon
|
||||
MCR p15, 0, r0, c1, c1, 2
|
||||
/* Set the CPACR for access to CP10 and CP11*/
|
||||
LDR r0, =0xF00000
|
||||
MCR p15, 0, r0, c1, c0, 2
|
||||
/* Set the FPEXC EN bit to enable the FPU */
|
||||
MOV r3, #0x40000000
|
||||
@VMSR FPEXC, r3
|
||||
MCR p10, 7, r3, c8, c0, 0
|
||||
.endfunc
|
||||
|
||||
.global disable_strict_align_check
|
||||
.func disable_strict_align_check
|
||||
disable_strict_align_check:
|
||||
/*Ray's note: disable strict alignment fault checking.
|
||||
without disabling this, data abort will happen when accessing
|
||||
the BPB structure of file system since it is packed.*/
|
||||
|
||||
push {r0, lr}
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #(0x1<<1) @clear A bit of SCTLR
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
pop {r0, pc}
|
||||
.endfunc
|
||||
|
||||
.global disable_L1_cache
|
||||
.func disable_L1_cache
|
||||
disable_L1_cache:
|
||||
push {r0-r6, lr}
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #(0x1<<12)
|
||||
bic r0, r0, #(0x1<<11)
|
||||
bic r0, r0, #(0x1<<2)
|
||||
bic r0, r0, #(0x1<<0)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
pop {r0-r6, pc}
|
||||
|
||||
.endfunc
|
||||
|
||||
.global get_arm_private_peripheral_base
|
||||
@ uint32_t get_arm_private_peripheral_base(void)@
|
||||
.func get_arm_private_peripheral_base
|
||||
get_arm_private_peripheral_base:
|
||||
|
||||
@ Get base address of private perpherial space
|
||||
mrc p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
@ mov r0, #0x00A00000
|
||||
bx lr
|
||||
|
||||
.endfunc @get_arm_private_peripheral_base()@
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ TLB
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global arm_unified_tlb_invalidate
|
||||
@ void arm_unified_tlb_invalidate(void)@
|
||||
.func arm_unified_tlb_invalidate
|
||||
arm_unified_tlb_invalidate:
|
||||
mov r0, #1
|
||||
mcr p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire unified TLB
|
||||
dsb
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_unified_tlb_invalidate_is
|
||||
@ void arm_unified_tlb_invalidate_is(void)@
|
||||
.func arm_unified_tlb_invalidate_is
|
||||
arm_unified_tlb_invalidate_is:
|
||||
mov r0, #1
|
||||
mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable
|
||||
dsb
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ Branch Prediction
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global arm_branch_prediction_enable
|
||||
@ void arm_branch_prediction_enable(void)
|
||||
.func arm_branch_prediction_enable
|
||||
arm_branch_prediction_enable:
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
|
||||
orr r0, r0, #(1 << 11) @ Set the Z bit (bit 11)
|
||||
mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_branch_prediction_disable
|
||||
@ void arm_branch_prediction_disable(void)
|
||||
.func arm_branch_prediction_disable
|
||||
arm_branch_prediction_disable:
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
|
||||
bic r0, r0, #(1 << 11) @ Clear the Z bit (bit 11)
|
||||
mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_branch_target_cache_invalidate
|
||||
@ void arm_branch_target_cache_invalidate(void)
|
||||
.func arm_branch_target_cache_invalidate
|
||||
arm_branch_target_cache_invalidate:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_branch_target_cache_invalidate_is
|
||||
@ void arm_branch_target_cache_invalidate_is(void)
|
||||
.func arm_branch_target_cache_invalidate_is
|
||||
arm_branch_target_cache_invalidate_is:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c1, 6 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ SCU
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
@ SCU offset from base of private peripheral space --> 0x000
|
||||
|
||||
.global scu_enable
|
||||
@ void scu_enable(void)
|
||||
@ Enables the SCU
|
||||
.func scu_enable
|
||||
scu_enable:
|
||||
|
||||
@ mrc p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
mov r0, #0x00A00000
|
||||
|
||||
ldr r1, [r0, #0x0] @ Read the SCU Control Register
|
||||
orr r1, r1, #0x1 @ Set bit 0 (The Enable bit)
|
||||
str r1, [r0, #0x0] @ Write back modifed value
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_join_smp
|
||||
@ void scu_join_smp(void)
|
||||
@ Set this CPU as participating in SMP
|
||||
.func scu_join_smp
|
||||
scu_join_smp:
|
||||
|
||||
@ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR
|
||||
orr r0, r0, #0x040 @ Set bit 6
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_leave_smp
|
||||
@ void scu_leave_smp(void)
|
||||
@ Set this CPU as NOT participating in SMP
|
||||
.func scu_leave_smp
|
||||
scu_leave_smp:
|
||||
|
||||
@ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR
|
||||
bic r0, r0, #0x040 @ Clear bit 6
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_get_cpus_in_smp
|
||||
@ unsigned int scu_get_cpus_in_smp(void)
|
||||
@ The return value is 1 bit per core:
|
||||
@ bit 0 - CPU 0
|
||||
@ bit 1 - CPU 1
|
||||
@ etc...
|
||||
.func scu_get_cpus_in_smp
|
||||
scu_get_cpus_in_smp:
|
||||
|
||||
@ mrc p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
mov r0, #0x00A00000
|
||||
|
||||
ldr r0, [r0, #0x004] @ Read SCU Configuration register
|
||||
mov r0, r0, lsr #4 @ Bits 7:4 gives the cores in SMP mode, shift then mask
|
||||
and r0, r0, #0x0F
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_enable_maintenance_broadcast
|
||||
@ void scu_enable_maintenance_broadcast(void)
|
||||
@ Enable the broadcasting of cache & TLB maintenance operations
|
||||
@ When enabled AND in SMP, broadcast all "inner sharable"
|
||||
@ cache and TLM maintenance operations to other SMP cores
|
||||
.func scu_enable_maintenance_broadcast
|
||||
scu_enable_maintenance_broadcast:
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register
|
||||
orr r0, r0, #0x01 @ Set the FW bit (bit 0)
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_disable_maintenance_broadcast
|
||||
@ void scu_disable_maintenance_broadcast(void)
|
||||
@ Disable the broadcasting of cache & TLB maintenance operations
|
||||
.func scu_disable_maintenance_broadcast
|
||||
scu_disable_maintenance_broadcast:
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register
|
||||
bic r0, r0, #0x01 @ Clear the FW bit (bit 0)
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_secure_invalidate
|
||||
@ void scu_secure_invalidate(unsigned int cpu, unsigned int ways)
|
||||
@ cpu: 0x0=CPU 0 0x1=CPU 1 etc...
|
||||
@ This function invalidates the SCU copy of the tag rams
|
||||
@ for the specified core. typically only done at start-up.
|
||||
@ Possible flow:
|
||||
@ - Invalidate L1 caches
|
||||
@ - Invalidate SCU copy of TAG RAMs
|
||||
@ - Join SMP
|
||||
.func scu_secure_invalidate
|
||||
scu_secure_invalidate:
|
||||
and r0, r0, #0x03 @ Mask off unused bits of CPU ID
|
||||
mov r0, r0, lsl #2 @ Convert into bit offset (four bits per core)
|
||||
|
||||
and r1, r1, #0x0F @ Mask off unused bits of ways
|
||||
mov r1, r1, lsl r0 @ Shift ways into the correct CPU field
|
||||
|
||||
mrc p15, 4, r2, c15, c0, 0 @ Read periph base address
|
||||
|
||||
str r1, [r2, #0x0C] @ Write to SCU Invalidate All in Secure State
|
||||
|
||||
bx lr
|
||||
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ End of cortexA9.s
|
||||
@ ------------------------------------------------------------
|
||||
.end
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file cpu_init.s
|
||||
*
|
||||
* This file contains CPU specific initialization. Invoked from main CRT
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 10/20/09 Initial version
|
||||
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
|
||||
* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
|
||||
* register to fix CR#830580
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
.text
|
||||
.global __cpu_init
|
||||
.align 2
|
||||
__cpu_init:
|
||||
|
||||
/* Clear cp15 regs with unknown reset values */
|
||||
mov r0, #0x0
|
||||
mcr p15, 0, r0, c5, c0, 0 /* DFSR */
|
||||
mcr p15, 0, r0, c5, c0, 1 /* IFSR */
|
||||
mcr p15, 0, r0, c6, c0, 0 /* DFAR */
|
||||
mcr p15, 0, r0, c6, c0, 2 /* IFAR */
|
||||
mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
|
||||
mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
|
||||
mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
|
||||
|
||||
/* Reset and start Cycle Counter */
|
||||
mov r2, #0x80000000 /* clear overflow */
|
||||
mcr p15, 0, r2, c9, c12, 3
|
||||
mov r2, #0xd /* D, C, E */
|
||||
mcr p15, 0, r2, c9, c12, 0
|
||||
mov r2, #0x80000000 /* enable cycle counter */
|
||||
mcr p15, 0, r2, c9, c12, 1
|
||||
|
||||
bx lr
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
/*
|
||||
* Copyright (c) 2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/**
|
||||
* @file cortex_a9.h
|
||||
* @brief some cortex A9 core functions
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.08.25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: cortex_a9.h
|
||||
Description: some cortex A9 core functions
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. No modifications
|
||||
*************************************************/
|
||||
#if !defined(__CORTEX_A9_H__)
|
||||
#define __CORTEX_A9_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
//! @addtogroup cortexa9
|
||||
//! @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @name Instruction macros
|
||||
//@{
|
||||
#define NOP() __asm__ volatile("nop\n\t")
|
||||
#define WFI() __asm__ volatile("wfi\n\t")
|
||||
#define WFE() __asm__ volatile("wfe\n\t")
|
||||
#define SEV() __asm__ volatile("sev\n\t")
|
||||
#define DMB() __asm__ volatile("dmb\n\t")
|
||||
#define DSB() __asm__ volatile("dsb\n\t")
|
||||
#define ISB() __asm__ volatile("isb\n\t")
|
||||
|
||||
#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2) \
|
||||
__asm__ __volatile__("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
|
||||
|
||||
#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
|
||||
__asm__ __volatile__("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
|
||||
|
||||
#define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value))
|
||||
#define ReadReg(address) (*(volatile unsigned int*)(address))
|
||||
//@}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//! @name Misc
|
||||
//@{
|
||||
//! @brief Enable or disable the IRQ and FIQ state.
|
||||
bool arm_set_interrupt_state(bool enable);
|
||||
|
||||
//! @brief Get current CPU ID.
|
||||
int cpu_get_current(void);
|
||||
|
||||
//! @brief Enable the NEON MPE.
|
||||
void enable_neon_fpu(void);
|
||||
|
||||
//! @brief Disable aborts on unaligned accesses.
|
||||
void disable_strict_align_check(void);
|
||||
|
||||
//! @brief Get base address of private perpherial space.
|
||||
//!
|
||||
//! @return The address of the ARM CPU's private peripherals.
|
||||
// uint32_t get_arm_private_peripheral_base(void);
|
||||
//@}
|
||||
|
||||
//! @name Data cache operations
|
||||
//@{
|
||||
|
||||
//! @brief Check if dcache is enabled or disabled.
|
||||
int arm_dcache_state_query();
|
||||
|
||||
//! @brief Enables data cache at any available cache level.
|
||||
//!
|
||||
//! Works only if MMU is enabled!
|
||||
void arm_dcache_enable();
|
||||
|
||||
//! @brief Disables the data cache at any available cache level.
|
||||
void arm_dcache_disable();
|
||||
|
||||
//! @brief Invalidates the entire data cache.
|
||||
void arm_dcache_invalidate();
|
||||
|
||||
//! @brief Invalidate a line of data cache.
|
||||
void arm_dcache_invalidate_line(const void* addr);
|
||||
|
||||
//! @brief Invalidate a number of lines of data cache.
|
||||
//!
|
||||
//! Number of lines depends on length parameter and size of line.
|
||||
//! Size of line for A9 L1 cache is 32B.
|
||||
void arm_dcache_invalidate_mlines(const void* addr, size_t length);
|
||||
|
||||
//! @brief Flush (clean) all lines of cache (all sets in all ways).
|
||||
void arm_dcache_flush();
|
||||
|
||||
//! @brief Flush (clean) one line of cache.
|
||||
void arm_dcache_flush_line(const void* addr);
|
||||
|
||||
// @brief Flush (clean) multiple lines of cache.
|
||||
//!
|
||||
//! Number of lines depends on length parameter and size of line.
|
||||
void arm_dcache_flush_mlines(const void* addr, size_t length);
|
||||
//@}
|
||||
|
||||
//! @name Instrution cache operations
|
||||
//@{
|
||||
|
||||
//! @brief Check if icache is enabled or disabled.
|
||||
int arm_icache_state_query();
|
||||
|
||||
//! @brief Enables instruction cache at any available cache level.
|
||||
//!
|
||||
//! Works without enabled MMU too!
|
||||
void arm_icache_enable();
|
||||
|
||||
//! @brief Disables the instruction cache at any available cache level.
|
||||
void arm_icache_disable();
|
||||
|
||||
//! @brief Invalidates the entire instruction cache.
|
||||
void arm_icache_invalidate();
|
||||
|
||||
//! @brief Invalidates the entire instruction cache inner shareable.
|
||||
void arm_icache_invalidate_is();
|
||||
|
||||
//! @brief Invalidate a line of the instruction cache.
|
||||
void arm_icache_invalidate_line(const void* addr);
|
||||
|
||||
//! @brief Invalidate a number of lines of instruction cache.
|
||||
//!
|
||||
//! Number of lines depends on length parameter and size of line.
|
||||
void arm_icache_invalidate_mlines(const void* addr, size_t length);
|
||||
//@}
|
||||
|
||||
//! @name TLB operations
|
||||
//@{
|
||||
//! @brief Invalidate entire unified TLB.
|
||||
void arm_unified_tlb_invalidate(void);
|
||||
|
||||
//! @brief Invalidate entire unified TLB Inner Shareable.
|
||||
void arm_unified_tlb_invalidate_is(void);
|
||||
//@}
|
||||
|
||||
//! @name Branch predictor operations
|
||||
//@{
|
||||
//! @brief Enable branch prediction.
|
||||
void arm_branch_prediction_enable(void);
|
||||
|
||||
//! @brief Disable branch prediction.
|
||||
void arm_branch_prediction_disable(void);
|
||||
|
||||
//! @brief Invalidate entire branch predictor array.
|
||||
void arm_branch_target_cache_invalidate(void);
|
||||
|
||||
//! @brief Invalidate entire branch predictor array Inner Shareable
|
||||
void arm_branch_target_cache_invalidate_is(void);
|
||||
//@}
|
||||
|
||||
//! @name SCU
|
||||
//@{
|
||||
//! @brief Enables the SCU.
|
||||
void scu_enable(void);
|
||||
|
||||
//! @brief Set this CPU as participating in SMP.
|
||||
void scu_join_smp(void);
|
||||
|
||||
//! @brief Set this CPU as not participating in SMP.
|
||||
void scu_leave_smp(void);
|
||||
|
||||
//! @brief Determine which CPUs are participating in SMP.
|
||||
//!
|
||||
//! The return value is 1 bit per core:
|
||||
//! - bit 0 - CPU 0
|
||||
//! - bit 1 - CPU 1
|
||||
//! - etc...
|
||||
unsigned int scu_get_cpus_in_smp(void);
|
||||
|
||||
//! @brief Enable the broadcasting of cache & TLB maintenance operations.
|
||||
//!
|
||||
//! When enabled AND in SMP, broadcast all "inner sharable"
|
||||
//! cache and TLM maintenance operations to other SMP cores
|
||||
void scu_enable_maintenance_broadcast(void);
|
||||
|
||||
//! @brief Disable the broadcasting of cache & TLB maintenance operations.
|
||||
void scu_disable_maintenance_broadcast(void);
|
||||
|
||||
//! @brief Invalidates the SCU copy of the tag rams for the specified core.
|
||||
//!
|
||||
//! Typically only done at start-up.
|
||||
//! Possible flow:
|
||||
//! - Invalidate L1 caches
|
||||
//! - Invalidate SCU copy of TAG RAMs
|
||||
//! - Join SMP
|
||||
//!
|
||||
//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc...
|
||||
//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways.
|
||||
void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
|
||||
//@}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
//! @}
|
||||
|
||||
#endif // __CORTEX_A9_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_assert.h
|
||||
*
|
||||
* This file contains assert related functions.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a hbm 07/14/09 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
|
||||
#define XIL_ASSERT_H /* by using protection macros */
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XIL_ASSERT_NONE 0U
|
||||
#define XIL_ASSERT_OCCURRED 1U
|
||||
#define XNULL NULL
|
||||
|
||||
extern u32 Xil_AssertStatus;
|
||||
extern void Xil_Assert(const char8 *File, s32 Line);
|
||||
void XNullHandler(void *NullParameter);
|
||||
|
||||
/**
|
||||
* This data type defines a callback to be invoked when an
|
||||
* assert occurs. The callback is invoked only when asserts are enabled
|
||||
*/
|
||||
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#ifndef NDEBUG
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This assert macro is to be used for functions that do not return anything
|
||||
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
|
||||
* accomodate tests so that asserts which fail allow execution to continue.
|
||||
*
|
||||
* @param Expression is the expression to evaluate. If it evaluates to
|
||||
* false, the assert occurs.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertVoid(Expression) \
|
||||
{ \
|
||||
if (Expression) { \
|
||||
Xil_AssertStatus = XIL_ASSERT_NONE; \
|
||||
} else { \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return; \
|
||||
} \
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This assert macro is to be used for functions that do return a value. This in
|
||||
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
|
||||
* so that asserts which fail allow execution to continue.
|
||||
*
|
||||
* @param Expression is the expression to evaluate. If it evaluates to false,
|
||||
* the assert occurs.
|
||||
*
|
||||
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertNonvoid(Expression) \
|
||||
{ \
|
||||
if (Expression) { \
|
||||
Xil_AssertStatus = XIL_ASSERT_NONE; \
|
||||
} else { \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return 0; \
|
||||
} \
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Always assert. This assert macro is to be used for functions that do not
|
||||
* return anything (void). Use for instances where an assert should always
|
||||
* occur.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertVoidAlways() \
|
||||
{ \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return; \
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Always assert. This assert macro is to be used for functions that do return
|
||||
* a value. Use for instances where an assert should always occur.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertNonvoidAlways() \
|
||||
{ \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
#define Xil_AssertVoid(Expression)
|
||||
#define Xil_AssertVoidAlways()
|
||||
#define Xil_AssertNonvoid(Expression)
|
||||
#define Xil_AssertNonvoidAlways()
|
||||
|
||||
#endif
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_errata.h
|
||||
*
|
||||
* This header file contains Cortex A9 and PL310 Errata definitions.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a srt 04/18/13 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XIL_ERRATA_H
|
||||
#define XIL_ERRATA_H
|
||||
|
||||
#define ENABLE_ARM_ERRATA 1
|
||||
|
||||
#ifdef ENABLE_ARM_ERRATA
|
||||
/* Cortex A9 ARM Errata */
|
||||
|
||||
/*
|
||||
* Errata No: 742230
|
||||
* Description: DMB operation may be faulty
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_742230 1
|
||||
|
||||
/*
|
||||
* Errata No: 743622
|
||||
* Description: Faulty hazard checking in the Store Buffer may lead
|
||||
* to data corruption.
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_743622 1
|
||||
|
||||
/*
|
||||
* Errata No: 775420
|
||||
* Description: A data cache maintenance operation which aborts,
|
||||
* might lead to deadlock
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_775420 1
|
||||
|
||||
/*
|
||||
* Errata No: 794073
|
||||
* Description: Speculative instruction fetches with MMU disabled
|
||||
* might not comply with architectural requirements
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_794073 1
|
||||
|
||||
|
||||
/* PL310 L2 Cache Errata */
|
||||
|
||||
/*
|
||||
* Errata No: 588369
|
||||
* Description: Clean & Invalidate maintenance operations do not
|
||||
* invalidate clean lines
|
||||
*/
|
||||
#define CONFIG_PL310_ERRATA_588369 1
|
||||
|
||||
/*
|
||||
* Errata No: 727915
|
||||
* Description: Background Clean and Invalidate by Way operation
|
||||
* can cause data corruption
|
||||
*/
|
||||
#define CONFIG_PL310_ERRATA_727915 1
|
||||
|
||||
/*
|
||||
* Errata No: 753970
|
||||
* Description: Cache sync operation may be faulty
|
||||
*/
|
||||
#define CONFIG_PL310_ERRATA_753970 1
|
||||
|
||||
#endif /* ENABLE_ARM_ERRATA */
|
||||
|
||||
#endif /* XIL_ERRATA_H */
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_types.h
|
||||
*
|
||||
* This file contains basic types for Xilinx software IP.
|
||||
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a hbm 07/14/09 First release
|
||||
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
|
||||
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
|
||||
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
|
||||
* Define LONG and ULONG datatypes and mask values
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_TYPES_H /* prevent circular inclusions */
|
||||
#define XIL_TYPES_H /* by using protection macros */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
# define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
# define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */
|
||||
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */
|
||||
|
||||
/** @name New types
|
||||
* New simple types.
|
||||
* @{
|
||||
*/
|
||||
#ifndef __KERNEL__
|
||||
#ifndef XBASIC_TYPES_H
|
||||
/**
|
||||
* guarded against xbasic_types.h.
|
||||
*/
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
|
||||
#define __XUINT64__
|
||||
typedef struct
|
||||
{
|
||||
u32 Upper;
|
||||
u32 Lower;
|
||||
} Xuint64;
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Return the most significant half of the 64 bit data type.
|
||||
*
|
||||
* @param x is the 64 bit word.
|
||||
*
|
||||
* @return The upper 32 bits of the 64 bit word.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUINT64_MSW(x) ((x).Upper)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Return the least significant half of the 64 bit data type.
|
||||
*
|
||||
* @param x is the 64 bit word.
|
||||
*
|
||||
* @return The lower 32 bits of the 64 bit word.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUINT64_LSW(x) ((x).Lower)
|
||||
|
||||
#endif /* XBASIC_TYPES_H */
|
||||
|
||||
/**
|
||||
* xbasic_types.h does not typedef s* or u64
|
||||
*/
|
||||
|
||||
typedef char char8;
|
||||
typedef int8_t s8;
|
||||
typedef int16_t s16;
|
||||
typedef int32_t s32;
|
||||
typedef int64_t s64;
|
||||
typedef uint64_t u64;
|
||||
typedef int sint32;
|
||||
|
||||
typedef intptr_t INTPTR;
|
||||
typedef uintptr_t UINTPTR;
|
||||
typedef ptrdiff_t PTRDIFF;
|
||||
|
||||
#if !defined(LONG) || !defined(ULONG)
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
#endif
|
||||
|
||||
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
|
||||
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
|
||||
|
||||
#else
|
||||
#include <linux/types.h>
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* This data type defines an interrupt handler for a device.
|
||||
* The argument points to the instance of the component
|
||||
*/
|
||||
typedef void (*XInterruptHandler) (void *InstancePtr);
|
||||
|
||||
/**
|
||||
* This data type defines an exception handler for a processor.
|
||||
* The argument points to the instance of the component
|
||||
*/
|
||||
typedef void (*XExceptionHandler) (void *InstancePtr);
|
||||
|
||||
/**
|
||||
* UPPER_32_BITS - return bits 32-63 of a number
|
||||
* @n: the number we're accessing
|
||||
*
|
||||
* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
|
||||
* the "right shift count >= width of type" warning when that quantity is
|
||||
* 32-bits.
|
||||
*/
|
||||
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
|
||||
|
||||
/**
|
||||
* LOWER_32_BITS - return bits 0-31 of a number
|
||||
* @n: the number we're accessing
|
||||
*/
|
||||
#define LOWER_32_BITS(n) ((u32)(n))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
|
|
@ -0,0 +1,475 @@
|
|||
/* Definition for CPU ID */
|
||||
#define XPAR_CPU_ID 0
|
||||
|
||||
/* Definitions for peripheral PS7_CORTEXA9_0 */
|
||||
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
|
||||
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#include "xparameters_ps.h"
|
||||
|
||||
#define STDIN_BASEADDRESS 0xE0001000
|
||||
#define STDOUT_BASEADDRESS 0xE0001000
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver CANPS */
|
||||
#define XPAR_XCANPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_CAN_0 */
|
||||
#define XPAR_PS7_CAN_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_CAN_0_BASEADDR 0xE0008000
|
||||
#define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF
|
||||
#define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_CAN_0 */
|
||||
#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID
|
||||
#define XPAR_XCANPS_0_BASEADDR 0xE0008000
|
||||
#define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF
|
||||
#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_DDR_0 */
|
||||
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
|
||||
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver DEVCFG */
|
||||
#define XPAR_XDCFG_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_DEV_CFG_0 */
|
||||
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
|
||||
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
|
||||
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
|
||||
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
|
||||
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver DMAPS */
|
||||
#define XPAR_XDMAPS_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral PS7_DMA_NS */
|
||||
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
|
||||
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
|
||||
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_DMA_S */
|
||||
#define XPAR_PS7_DMA_S_DEVICE_ID 1
|
||||
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
|
||||
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_DMA_NS */
|
||||
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
|
||||
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
|
||||
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
|
||||
|
||||
/* Canonical definitions for peripheral PS7_DMA_S */
|
||||
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
|
||||
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
|
||||
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver EMACPS */
|
||||
#define XPAR_XEMACPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_ETHERNET_0 */
|
||||
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
|
||||
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
|
||||
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
|
||||
#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
|
||||
#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
|
||||
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_0 */
|
||||
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
|
||||
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_1 */
|
||||
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
|
||||
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_2 */
|
||||
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
|
||||
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_3 */
|
||||
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
|
||||
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_DDRC_0 */
|
||||
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
|
||||
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
|
||||
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
|
||||
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_GPV_0 */
|
||||
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
|
||||
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_INTC_DIST_0 */
|
||||
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
|
||||
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
|
||||
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
|
||||
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_L2CACHEC_0 */
|
||||
#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
|
||||
#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_OCMC_0 */
|
||||
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
|
||||
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_PL310_0 */
|
||||
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
|
||||
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_PMU_0 */
|
||||
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
|
||||
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
|
||||
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
|
||||
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
|
||||
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
|
||||
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_RAM_0 */
|
||||
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
|
||||
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_RAM_1 */
|
||||
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
|
||||
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_SCUC_0 */
|
||||
#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
|
||||
#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_SLCR_0 */
|
||||
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
|
||||
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver GPIOPS */
|
||||
#define XPAR_XGPIOPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_GPIO_0 */
|
||||
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
|
||||
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_GPIO_0 */
|
||||
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
|
||||
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
|
||||
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver IICPS */
|
||||
#define XPAR_XIICPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_I2C_0 */
|
||||
#define XPAR_PS7_I2C_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
|
||||
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
|
||||
#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_I2C_0 */
|
||||
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
|
||||
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
|
||||
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
|
||||
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver QSPIPS */
|
||||
#define XPAR_XQSPIPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_QSPI_0 */
|
||||
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
|
||||
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
|
||||
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
|
||||
#define XPAR_PS7_QSPI_0_QSPI_MODE 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_QSPI_0 */
|
||||
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
|
||||
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
|
||||
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
|
||||
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
|
||||
#define XPAR_XQSPIPS_0_QSPI_MODE 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SCUGIC */
|
||||
#define XPAR_XSCUGIC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SCUGIC_0 */
|
||||
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
|
||||
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
|
||||
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
|
||||
#define XPAR_SCUGIC_0_DEVICE_ID 0
|
||||
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
|
||||
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
|
||||
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SCUTIMER */
|
||||
#define XPAR_XSCUTIMER_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SCUTIMER_0 */
|
||||
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
|
||||
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
|
||||
#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
|
||||
#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
|
||||
#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SCUWDT */
|
||||
#define XPAR_XSCUWDT_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SCUWDT_0 */
|
||||
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
|
||||
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
|
||||
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
|
||||
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
|
||||
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SDPS */
|
||||
#define XPAR_XSDPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SD_0 */
|
||||
#define XPAR_PS7_SD_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
|
||||
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
|
||||
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_PS7_SD_0_HAS_CD 1
|
||||
#define XPAR_PS7_SD_0_HAS_WP 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SD_0 */
|
||||
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
|
||||
#define XPAR_XSDPS_0_BASEADDR 0xE0100000
|
||||
#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
|
||||
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_XSDPS_0_HAS_CD 1
|
||||
#define XPAR_XSDPS_0_HAS_WP 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver TTCPS */
|
||||
#define XPAR_XTTCPS_NUM_INSTANCES 3
|
||||
|
||||
/* Definitions for peripheral PS7_TTC_0 */
|
||||
#define XPAR_PS7_TTC_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
|
||||
#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
|
||||
#define XPAR_PS7_TTC_1_DEVICE_ID 1
|
||||
#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
|
||||
#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
|
||||
#define XPAR_PS7_TTC_2_DEVICE_ID 2
|
||||
#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
|
||||
#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_TTC_0 */
|
||||
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
|
||||
#define XPAR_XTTCPS_0_BASEADDR 0xF8001000
|
||||
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
|
||||
|
||||
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
|
||||
#define XPAR_XTTCPS_1_BASEADDR 0xF8001004
|
||||
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
|
||||
|
||||
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
|
||||
#define XPAR_XTTCPS_2_BASEADDR 0xF8001008
|
||||
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver UARTPS */
|
||||
#define XPAR_XUARTPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_UART_1 */
|
||||
#define XPAR_PS7_UART_1_DEVICE_ID 0
|
||||
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
|
||||
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
|
||||
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_PS7_UART_1_HAS_MODEM 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_UART_1 */
|
||||
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
|
||||
#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
|
||||
#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
|
||||
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_XUARTPS_0_HAS_MODEM 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver USBPS */
|
||||
#define XPAR_XUSBPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_USB_0 */
|
||||
#define XPAR_PS7_USB_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
|
||||
#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_USB_0 */
|
||||
#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
|
||||
#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
|
||||
#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver XADCPS */
|
||||
#define XPAR_XADCPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_XADC_0 */
|
||||
#define XPAR_PS7_XADC_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
|
||||
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_XADC_0 */
|
||||
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
|
||||
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
|
||||
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
|
@ -0,0 +1,333 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xparameters_ps.h
|
||||
*
|
||||
* This file contains the address definitions for the hard peripherals
|
||||
* attached to the ARM Cortex A9 core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 02/01/10 Initial version
|
||||
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
|
||||
* driver tcl
|
||||
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _XPARAMETERS_PS_H_
|
||||
#define _XPARAMETERS_PS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock
|
||||
*/
|
||||
|
||||
/* Canonical definitions for DDR MEMORY */
|
||||
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
|
||||
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
|
||||
|
||||
/* Canonical definitions for Interrupts */
|
||||
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
|
||||
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
|
||||
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
|
||||
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
|
||||
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
|
||||
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
|
||||
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
|
||||
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
|
||||
|
||||
|
||||
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
|
||||
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
|
||||
|
||||
|
||||
|
||||
/* Canonical definitions for DMAC */
|
||||
|
||||
|
||||
/* Canonical definitions for WDT */
|
||||
|
||||
/* Canonical definitions for SLCR */
|
||||
#define XPAR_XSLCR_NUM_INSTANCES 1U
|
||||
#define XPAR_XSLCR_0_DEVICE_ID 0U
|
||||
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
|
||||
|
||||
/* Canonical definitions for SCU GIC */
|
||||
#define XPAR_SCUGIC_NUM_INSTANCES 1U
|
||||
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
|
||||
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
|
||||
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
|
||||
#define XPAR_SCUGIC_ACK_BEFORE 0U
|
||||
|
||||
/* Canonical definitions for Global Timer */
|
||||
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
|
||||
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
|
||||
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
|
||||
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
|
||||
|
||||
|
||||
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
|
||||
#define XPAR_AXI_EMC
|
||||
|
||||
|
||||
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
|
||||
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock. These have been put for bacwards compatibilty
|
||||
*/
|
||||
|
||||
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
|
||||
#define XPS_UART0_BASEADDR 0xE0000000U
|
||||
#define XPS_UART1_BASEADDR 0xE0001000U
|
||||
#define XPS_USB0_BASEADDR 0xE0002000U
|
||||
#define XPS_USB1_BASEADDR 0xE0003000U
|
||||
#define XPS_I2C0_BASEADDR 0xE0004000U
|
||||
#define XPS_I2C1_BASEADDR 0xE0005000U
|
||||
#define XPS_SPI0_BASEADDR 0xE0006000U
|
||||
#define XPS_SPI1_BASEADDR 0xE0007000U
|
||||
#define XPS_CAN0_BASEADDR 0xE0008000U
|
||||
#define XPS_CAN1_BASEADDR 0xE0009000U
|
||||
#define XPS_GPIO_BASEADDR 0xE000A000U
|
||||
#define XPS_GEM0_BASEADDR 0xE000B000U
|
||||
#define XPS_GEM1_BASEADDR 0xE000C000U
|
||||
#define XPS_QSPI_BASEADDR 0xE000D000U
|
||||
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
|
||||
#define XPS_SDIO0_BASEADDR 0xE0100000U
|
||||
#define XPS_SDIO1_BASEADDR 0xE0101000U
|
||||
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
|
||||
#define XPS_NAND_BASEADDR 0xE1000000U
|
||||
#define XPS_PARPORT0_BASEADDR 0xE2000000U
|
||||
#define XPS_PARPORT1_BASEADDR 0xE4000000U
|
||||
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
|
||||
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
|
||||
#define XPS_TTC0_BASEADDR 0xF8001000U
|
||||
#define XPS_TTC1_BASEADDR 0xF8002000U
|
||||
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
|
||||
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
|
||||
#define XPS_WDT_BASEADDR 0xF8005000U
|
||||
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
|
||||
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
|
||||
#define XPS_AFI0_BASEADDR 0xF8008000U
|
||||
#define XPS_AFI1_BASEADDR 0xF8009000U
|
||||
#define XPS_AFI2_BASEADDR 0xF800A000U
|
||||
#define XPS_AFI3_BASEADDR 0xF800B000U
|
||||
#define XPS_OCM_BASEADDR 0xF800C000U
|
||||
#define XPS_EFUSE_BASEADDR 0xF800D000U
|
||||
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
|
||||
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
|
||||
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
|
||||
#define XPS_L2CC_BASEADDR 0xF8F02000U
|
||||
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
|
||||
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
|
||||
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
|
||||
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
|
||||
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
|
||||
|
||||
/* Shared Peripheral Interrupts (SPI) */
|
||||
#define XPS_CORE_PARITY0_INT_ID 32U
|
||||
#define XPS_CORE_PARITY1_INT_ID 33U
|
||||
#define XPS_L2CC_INT_ID 34U
|
||||
#define XPS_OCMINTR_INT_ID 35U
|
||||
#define XPS_ECC_INT_ID 36U
|
||||
#define XPS_PMU0_INT_ID 37U
|
||||
#define XPS_PMU1_INT_ID 38U
|
||||
#define XPS_SYSMON_INT_ID 39U
|
||||
#define XPS_DVC_INT_ID 40U
|
||||
#define XPS_WDT_INT_ID 41U
|
||||
#define XPS_TTC0_0_INT_ID 42U
|
||||
#define XPS_TTC0_1_INT_ID 43U
|
||||
#define XPS_TTC0_2_INT_ID 44U
|
||||
#define XPS_DMA0_ABORT_INT_ID 45U
|
||||
#define XPS_DMA0_INT_ID 46U
|
||||
#define XPS_DMA1_INT_ID 47U
|
||||
#define XPS_DMA2_INT_ID 48U
|
||||
#define XPS_DMA3_INT_ID 49U
|
||||
#define XPS_SMC_INT_ID 50U
|
||||
#define XPS_QSPI_INT_ID 51U
|
||||
#define XPS_GPIO_INT_ID 52U
|
||||
#define XPS_USB0_INT_ID 53U
|
||||
#define XPS_GEM0_INT_ID 54U
|
||||
#define XPS_GEM0_WAKE_INT_ID 55U
|
||||
#define XPS_SDIO0_INT_ID 56U
|
||||
#define XPS_I2C0_INT_ID 57U
|
||||
#define XPS_SPI0_INT_ID 58U
|
||||
#define XPS_UART0_INT_ID 59U
|
||||
#define XPS_CAN0_INT_ID 60U
|
||||
#define XPS_FPGA0_INT_ID 61U
|
||||
#define XPS_FPGA1_INT_ID 62U
|
||||
#define XPS_FPGA2_INT_ID 63U
|
||||
#define XPS_FPGA3_INT_ID 64U
|
||||
#define XPS_FPGA4_INT_ID 65U
|
||||
#define XPS_FPGA5_INT_ID 66U
|
||||
#define XPS_FPGA6_INT_ID 67U
|
||||
#define XPS_FPGA7_INT_ID 68U
|
||||
#define XPS_TTC1_0_INT_ID 69U
|
||||
#define XPS_TTC1_1_INT_ID 70U
|
||||
#define XPS_TTC1_2_INT_ID 71U
|
||||
#define XPS_DMA4_INT_ID 72U
|
||||
#define XPS_DMA5_INT_ID 73U
|
||||
#define XPS_DMA6_INT_ID 74U
|
||||
#define XPS_DMA7_INT_ID 75U
|
||||
#define XPS_USB1_INT_ID 76U
|
||||
#define XPS_GEM1_INT_ID 77U
|
||||
#define XPS_GEM1_WAKE_INT_ID 78U
|
||||
#define XPS_SDIO1_INT_ID 79U
|
||||
#define XPS_I2C1_INT_ID 80U
|
||||
#define XPS_SPI1_INT_ID 81U
|
||||
#define XPS_UART1_INT_ID 82U
|
||||
#define XPS_CAN1_INT_ID 83U
|
||||
#define XPS_FPGA8_INT_ID 84U
|
||||
#define XPS_FPGA9_INT_ID 85U
|
||||
#define XPS_FPGA10_INT_ID 86U
|
||||
#define XPS_FPGA11_INT_ID 87U
|
||||
#define XPS_FPGA12_INT_ID 88U
|
||||
#define XPS_FPGA13_INT_ID 89U
|
||||
#define XPS_FPGA14_INT_ID 90U
|
||||
#define XPS_FPGA15_INT_ID 91U
|
||||
|
||||
/* Private Peripheral Interrupts (PPI) */
|
||||
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
|
||||
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
|
||||
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
|
||||
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
|
||||
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
|
||||
|
||||
|
||||
/* REDEFINES for TEST APP */
|
||||
/* Definitions for UART */
|
||||
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
|
||||
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
|
||||
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
|
||||
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
|
||||
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
|
||||
|
||||
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
|
||||
|
||||
/* For backwards compatibilty */
|
||||
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
|
||||
|
||||
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#define XPAR_SCUTIMER_DEVICE_ID 0U
|
||||
#define XPAR_SCUWDT_DEVICE_ID 0U
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* protection macro */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil-crt0.S
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 1.00a ecm 10/20/09 Initial version
|
||||
* 3.05a sdm 02/02/12 Added code for profiling
|
||||
* 3.06a sgd 05/16/12 Added global constructors and cleanup code
|
||||
* Uart initialization based on compiler flag
|
||||
* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
|
||||
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
|
||||
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
|
||||
* initialization of uart smc nor and sram
|
||||
* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
|
||||
* timer when USE_AMP flag is defined
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
.file "xil-crt0.S"
|
||||
.section ".got2","aw"
|
||||
.align 2
|
||||
|
||||
.text
|
||||
.Lstack:
|
||||
.long stacks_top
|
||||
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
|
||||
|
||||
mov r0, #0
|
||||
|
||||
ldr r13, .Lstack /* stack address */
|
||||
|
||||
/* Reset and start Global Timer */
|
||||
mov r0, #0x0
|
||||
mov r1, #0x0
|
||||
|
||||
@ #if USE_AMP != 1
|
||||
@ bl XTime_SetTime
|
||||
@ #endif
|
||||
|
||||
/* make sure argc and argv are valid */
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
|
||||
/* Let her rip */
|
||||
bl bootmain
|
||||
|
||||
/* All done */
|
||||
b .
|
||||
|
||||
.Lstart:
|
||||
.size _start,.Lstart-_start
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/*******************************************************************/
|
||||
/* */
|
||||
/* This file is automatically generated by linker script generator.*/
|
||||
/* */
|
||||
/* Version: */
|
||||
/* */
|
||||
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
|
||||
/* */
|
||||
/* Description : Cortex-A9 Linker Script */
|
||||
/* */
|
||||
/*******************************************************************/
|
||||
|
||||
/* Define Memories in the system */
|
||||
BOOT_STACK_SIZE = 0x4000;
|
||||
RAM_VECTORS_SIZE = 72;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
ddr3 (rwx) : ORIGIN = 0x00100000, LENGTH = 0x3FF00000
|
||||
virt_ddr3 (WRX) : ORIGIN = 0xA0010000, LENGTH = 0x3FF00000
|
||||
}
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_boot_start)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(ddr3);
|
||||
. = ALIGN(4);
|
||||
|
||||
_start_image_addr = .;
|
||||
|
||||
.start_sec : {
|
||||
. = ALIGN(0x1000);
|
||||
|
||||
*(.vectors)
|
||||
|
||||
/* read only area. */
|
||||
boot.o(.text)
|
||||
xil-crt0.o(.text .text.*)
|
||||
cpu_init.o(.text .text.*)
|
||||
bootmmu.o(.text .text.*)
|
||||
|
||||
boot.o(.rodata .rodata.*)
|
||||
xil-crt0.o(.rodata .rodata.*)
|
||||
cpu_init.o(.rodata .rodata.*)
|
||||
bootmmu.o(.rodata .rodata.*)
|
||||
|
||||
/* already initialized to zero. */
|
||||
boot.o(.data .data.*)
|
||||
xil-crt0.o(.data .data.*)
|
||||
cpu_init.o(.data .data.*)
|
||||
bootmmu.o(.data .data.*)
|
||||
|
||||
/* initialization start checkpoint. */
|
||||
PROVIDE(boot_start_addr = .);
|
||||
|
||||
boot.o(.bss .bss.* COMMON)
|
||||
xil-crt0.o(.bss .bss.* COMMON)
|
||||
cpu_init.o(.bss .bss.* COMMON)
|
||||
bootmmu.o(.bss .bss.* COMMON)
|
||||
|
||||
/* stack for booting code. */
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(stacks_start = .);
|
||||
. += BOOT_STACK_SIZE;
|
||||
PROVIDE(stacks_end = .);
|
||||
PROVIDE(stacks_top = .);
|
||||
|
||||
/* initialization end checkpoint. */
|
||||
PROVIDE(boot_end_addr = .);
|
||||
} > ddr3
|
||||
|
||||
/* Other Kernel code is placed over 0x80000000 + 128KB. */
|
||||
.text : AT(0x00110000) {
|
||||
*(.vectors)
|
||||
. = ALIGN(0x1000);
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
} > virt_ddr3
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
/* Other Kernel code text checkpoint. */
|
||||
PROVIDE(kern_text = .);
|
||||
|
||||
.data : {
|
||||
*(.data .data.*)
|
||||
/* user app */
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(_binary_fs_img_start = .);
|
||||
*(.rawdata_fs_img*)
|
||||
PROVIDE(_binary_fs_img_end = .);
|
||||
PROVIDE(_binary_init_start = .);
|
||||
*(.rawdata_init*)
|
||||
PROVIDE(_binary_init_end = .);
|
||||
PROVIDE(_binary_default_fs_start = .);
|
||||
*(.rawdata_memfs*)
|
||||
PROVIDE(_binary_default_fs_end = .);
|
||||
} > virt_ddr3
|
||||
|
||||
PROVIDE(kernel_data_begin = .);
|
||||
|
||||
_image_size = . - 0xA0000000;
|
||||
|
||||
.bss : {
|
||||
PROVIDE(__bss_start__ = .);
|
||||
*(.bss .bss.* COMMON)
|
||||
PROVIDE(__bss_end__ = .);
|
||||
} > virt_ddr3
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(kernel_data_end = .);
|
||||
}
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_DIR:= arm/armv7-a/cortex-a9/imx6q-sabrelite
|
||||
SRC_DIR:= arm/armv7-a/cortex-a9/$(BOARD)
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -63,11 +63,17 @@ static void _clear_clock_intr()
|
|||
gpt_get_compare_event(kGPTOutputCompare1);
|
||||
}
|
||||
|
||||
static struct XiziClockDriver hardkernel_clock_driver = (struct XiziClockDriver) {
|
||||
static bool _is_timer_expired()
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct XiziClockDriver hardkernel_clock_driver = {
|
||||
.sys_clock_init = _sys_clock_init,
|
||||
.get_clock_int = _get_clock_int,
|
||||
.get_tick = _get_tick,
|
||||
.get_second = _get_second,
|
||||
.is_timer_expired = _is_timer_expired,
|
||||
.clear_clock_intr = _clear_clock_intr,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
SRC_FILES := clock.c \
|
||||
xscutimer_g.c \
|
||||
xscutimer_sinit.c \
|
||||
xscutimer.c \
|
||||
xscutimer_selftest.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
/**
|
||||
* @file clock.c
|
||||
* @brief clock interfaces of hardkernel
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.08.25
|
||||
*/
|
||||
/*************************************************
|
||||
File name: clock.c
|
||||
Description: clock interfaces of hardkernel
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. first version
|
||||
*************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xscutimer.h"
|
||||
|
||||
#include "clock_common_op.h"
|
||||
#include "log.h"
|
||||
|
||||
XScuTimer global_timer;
|
||||
#define TIMER_LOAD_VALUE 0x32CFD0 // 10ms
|
||||
|
||||
static void _sys_clock_init()
|
||||
{
|
||||
XScuTimer_Config* timer_cfg = XScuTimer_LookupConfig(XPAR_PS7_SCUTIMER_0_DEVICE_ID);
|
||||
if (XScuTimer_CfgInitialize(&global_timer, timer_cfg, timer_cfg->BaseAddr) != XST_SUCCESS || XScuTimer_SelfTest(&global_timer) != XST_SUCCESS) {
|
||||
ERROR("Error initializing timer\n");
|
||||
return;
|
||||
}
|
||||
XScuTimer_EnableInterrupt(&global_timer);
|
||||
XScuTimer_EnableAutoReload(&global_timer);
|
||||
XScuTimer_LoadTimer(&global_timer, TIMER_LOAD_VALUE);
|
||||
XScuTimer_Start(&global_timer);
|
||||
}
|
||||
|
||||
static uint32_t _get_clock_int()
|
||||
{
|
||||
return XPAR_PS7_SCUTIMER_0_INTR;
|
||||
}
|
||||
|
||||
static uint64_t _get_tick()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint64_t _get_second()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool _is_timer_expired()
|
||||
{
|
||||
return XScuTimer_IsExpired(&global_timer);
|
||||
}
|
||||
|
||||
static void _clear_clock_intr()
|
||||
{
|
||||
XScuTimer_ClearInterruptStatus(&global_timer);
|
||||
}
|
||||
|
||||
static struct XiziClockDriver hardkernel_clock_driver = {
|
||||
.sys_clock_init = _sys_clock_init,
|
||||
.get_clock_int = _get_clock_int,
|
||||
.get_tick = _get_tick,
|
||||
.get_second = _get_second,
|
||||
.is_timer_expired = _is_timer_expired,
|
||||
.clear_clock_intr = _clear_clock_intr,
|
||||
};
|
||||
|
||||
struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag)
|
||||
{
|
||||
hardkernel_clock_driver.sys_clock_init();
|
||||
return &hardkernel_clock_driver;
|
||||
}
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscutimer.h
|
||||
* @addtogroup scutimer_v2_1
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* The timer driver supports the Cortex A9 private timer.
|
||||
*
|
||||
* The timer driver supports the following features:
|
||||
* - Normal mode and Auto reload mode
|
||||
* - Interrupts (Interrupt handler is not provided in this driver. Application
|
||||
* has to register it's own handler)
|
||||
*
|
||||
* <b> Initialization and Configuration </b>
|
||||
*
|
||||
* The device driver enables higher layer software (e.g., an application) to
|
||||
* communicate with the Timer.
|
||||
*
|
||||
* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
|
||||
* user needs to first call the XScuTimer_LookupConfig() API which returns
|
||||
* the Configuration structure pointer which is passed as a parameter to
|
||||
* the XScuTimer_CfgInitialize() API.
|
||||
*
|
||||
* <b> Interrupts </b>
|
||||
*
|
||||
* The Timer hardware supports interrupts.
|
||||
*
|
||||
* This driver does not provide a Interrupt Service Routine (ISR) for the device.
|
||||
* It is the responsibility of the application to provide one if needed. Refer to
|
||||
* the interrupt example provided with this driver for details on using the
|
||||
* Timer in interrupt mode.
|
||||
*
|
||||
* <b> Virtual Memory </b>
|
||||
*
|
||||
* This driver supports Virtual Memory. The RTOS is responsible for calculating
|
||||
* the correct device base address in Virtual Memory space.
|
||||
*
|
||||
* <b> Threads </b>
|
||||
*
|
||||
* This driver is not thread safe. Any needs for threads or thread mutual
|
||||
* exclusion must be satisfied by the layer above this driver.
|
||||
*
|
||||
* <b> Asserts </b>
|
||||
*
|
||||
* Asserts are used within all Xilinx drivers to enforce constraints on argument
|
||||
* values. Asserts can be turned off on a system-wide basis by defining, at
|
||||
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
|
||||
* is recommended that users leave asserts on during development.
|
||||
*
|
||||
* <b> Building the driver </b>
|
||||
*
|
||||
* The XScuTimer driver is composed of several source files. This allows the user
|
||||
* to build and link only those parts of the driver that are necessary.
|
||||
*
|
||||
* <br><br>
|
||||
*
|
||||
* NOTE:
|
||||
* The timer is not a part of the snoop control unit as indicated by the
|
||||
* prefix "scu" in the name of the driver.
|
||||
* It is an independent module in APU.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a nm 03/10/10 First release
|
||||
* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
|
||||
* when the xstatus.h in the common driver overwrites
|
||||
* the xstatus.h of the standalone BSP during the
|
||||
* libgen.
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XSCUTIMER_H /* prevent circular inclusions */
|
||||
#define XSCUTIMER_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xscutimer_hw.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct {
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
u32 BaseAddr; /**< Base address of the device */
|
||||
} XScuTimer_Config;
|
||||
|
||||
/**
|
||||
* The XScuTimer driver instance data. The user is required to allocate a
|
||||
* variable of this type for every timer device in the system.
|
||||
* A pointer to a variable of this type is then passed to the driver API
|
||||
* functions.
|
||||
*/
|
||||
typedef struct {
|
||||
XScuTimer_Config Config; /**< Hardware Configuration */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
u32 IsStarted; /**< Device timer is running */
|
||||
} XScuTimer;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Check if the timer has expired.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if the timer has expired.
|
||||
* - FALSE if the timer has not expired.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_IsExpired(InstancePtr) \
|
||||
((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_ISR_OFFSET) & \
|
||||
XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
|
||||
XSCUTIMER_ISR_EVENT_FLAG_MASK)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Re-start the timer. This macro will read the timer load register
|
||||
* and writes the same value to load register to update the counter register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_RestartTimer(InstancePtr) \
|
||||
XScuTimer_LoadTimer((InstancePtr), \
|
||||
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_LOAD_OFFSET))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the timer load register. This will also update the
|
||||
* timer counter register with the new value. This macro can be used to
|
||||
* change the time-out value.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
* @param Value is the count to be loaded in to the load register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_LoadTimer(InstancePtr, Value) \
|
||||
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_LOAD_OFFSET, (Value))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Returns the current timer counter register value. It can be called at any
|
||||
* time.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return Contents of the timer counter register.
|
||||
*
|
||||
* @note C-style signature:
|
||||
u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_GetCounterValue(InstancePtr) \
|
||||
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_COUNTER_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enable auto-reload mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_EnableAutoReload(InstancePtr) \
|
||||
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET, \
|
||||
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET) | \
|
||||
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Disable auto-reload mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_DisableAutoReload(InstancePtr) \
|
||||
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET, \
|
||||
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET) & \
|
||||
~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enable the Timer interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_EnableInterrupt(InstancePtr) \
|
||||
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET, \
|
||||
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET) | \
|
||||
XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Disable the Timer interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_DisableInterrupt(InstancePtr) \
|
||||
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET, \
|
||||
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_CONTROL_OFFSET) & \
|
||||
~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function reads the interrupt status.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_GetInterruptStatus(InstancePtr) \
|
||||
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_ISR_OFFSET)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function clears the interrupt status.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_ClearInterruptStatus(InstancePtr) \
|
||||
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
|
||||
XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*
|
||||
* Lookup configuration in xscutimer_sinit.c
|
||||
*/
|
||||
XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
|
||||
|
||||
/*
|
||||
* Selftest function in xscutimer_selftest.c
|
||||
*/
|
||||
s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
|
||||
|
||||
/*
|
||||
* Interface functions in xscutimer.c
|
||||
*/
|
||||
s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
|
||||
XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
|
||||
void XScuTimer_Start(XScuTimer *InstancePtr);
|
||||
void XScuTimer_Stop(XScuTimer *InstancePtr);
|
||||
void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
|
||||
u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscutimer_hw.h
|
||||
* @addtogroup scutimer_v2_1
|
||||
* @{
|
||||
*
|
||||
* This file contains the hardware interface to the Timer.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a nm 03/10/10 First release
|
||||
* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
|
||||
* and interrupt registers
|
||||
* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
|
||||
* when the xstatus.h in the common driver overwrites
|
||||
* the xstatus.h of the standalone BSP during the
|
||||
* libgen.
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
|
||||
#define XSCUTIMER_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xil_types.h"
|
||||
#include "xil_io.h"
|
||||
#include "xil_assert.h"
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Register Map
|
||||
* Offsets of registers from the start of the device
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
|
||||
#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
|
||||
#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
|
||||
#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
|
||||
Status Register */
|
||||
/* @} */
|
||||
|
||||
/** @name Timer Control register
|
||||
* This register bits control the prescaler, Intr enable,
|
||||
* auto-reload and timer enable.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
|
||||
#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
|
||||
#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
|
||||
#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
|
||||
#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Status register
|
||||
* This register indicates the Timer counter register has reached zero.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
|
||||
/*@}*/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the timer load register. This will also update the
|
||||
* timer counter register with the new value. This macro can be used to
|
||||
* change the time-out value.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
* @param Value is the count to be loaded in to the load register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_SetLoadReg(BaseAddr, Value) \
|
||||
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Returns the current timer load register value.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
*
|
||||
* @return Contents of the timer load register.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_GetLoadReg(BaseAddr) \
|
||||
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the timer counter register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
* @param Value is the count to be loaded in to the counter register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_SetCounterReg(BaseAddr, Value) \
|
||||
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Returns the current timer counter register value.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
*
|
||||
* @return Contents of the timer counter register.
|
||||
*
|
||||
* @note C-style signature:
|
||||
u32 XScuTimer_GetCounterReg(u32 BaseAddr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_GetCounterReg(BaseAddr) \
|
||||
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the timer load register. This will also update the
|
||||
* timer counter register with the new value. This macro can be used to
|
||||
* change the time-out value.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
* @param Value is the count to be loaded in to the load register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_SetControlReg(BaseAddr, Value) \
|
||||
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Returns the current timer load register value.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
*
|
||||
* @return Contents of the timer load register.
|
||||
*
|
||||
* @note C-style signature:
|
||||
u32 XScuTimer_GetControlReg(u32 BaseAddr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_GetControlReg(BaseAddr) \
|
||||
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the timer counter register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
* @param Value is the count to be loaded in to the counter register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_SetIntrReg(BaseAddr, Value) \
|
||||
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Returns the current timer counter register value.
|
||||
*
|
||||
* @param BaseAddr is the base address of the scu timer.
|
||||
*
|
||||
* @return Contents of the timer counter register.
|
||||
*
|
||||
* @note C-style signature:
|
||||
u32 XScuTimer_GetIntrReg(u32 BaseAddr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XScuTimer_GetIntrReg(BaseAddr) \
|
||||
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read from the given Timer register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the device
|
||||
* @param RegOffset is the register offset to be read
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note C-style signature:
|
||||
* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
|
||||
Xil_In32((BaseAddr) + (RegOffset))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write to the given Timer register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the device
|
||||
* @param RegOffset is the register offset to be written
|
||||
* @param Data is the 32-bit value to write to the register
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddr) + (RegOffset), (Data))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xtime_l.h
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ---------------------------------------------------
|
||||
* 1.00a rp/sdm 11/03/09 Initial release.
|
||||
* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
|
||||
* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
|
||||
* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
|
||||
* </pre>
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XTIME_H /* prevent circular inclusions */
|
||||
#define XTIME_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef u64 XTime;
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
|
||||
#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
|
||||
#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
|
||||
#define GTIMER_CONTROL_OFFSET 0x08U
|
||||
|
||||
|
||||
/* Global Timer is always clocked at half of the CPU frequency */
|
||||
#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XTime_SetTime(XTime Xtime_Global);
|
||||
void XTime_GetTime(XTime *Xtime_Global);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XTIME_H */
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscutimer.c
|
||||
* @addtogroup scutimer_v2_1
|
||||
* @{
|
||||
*
|
||||
* Contains the implementation of interface functions of the SCU Timer driver.
|
||||
* See xscutimer.h for a description of the driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a nm 03/10/10 First release
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xscutimer.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Initialize a specific timer instance/driver. This function must be called
|
||||
* before other functions of the driver are called.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
* @param ConfigPtr points to the XScuTimer configuration structure.
|
||||
* @param EffectiveAddress is the base address for the device. It could be
|
||||
* a virtual address if address translation is supported in the
|
||||
* system, otherwise it is the physical address.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if initialization was successful.
|
||||
* - XST_DEVICE_IS_STARTED if the device has already been started.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
|
||||
XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
|
||||
{
|
||||
s32 Status;
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(ConfigPtr != NULL);
|
||||
|
||||
/*
|
||||
* If the device is started, disallow the initialize and return a
|
||||
* status indicating it is started. This allows the user to stop the
|
||||
* device and reinitialize, but prevents a user from inadvertently
|
||||
* initializing.
|
||||
*/
|
||||
if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
|
||||
/*
|
||||
* Copy configuration into the instance structure.
|
||||
*/
|
||||
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
|
||||
|
||||
/*
|
||||
* Save the base address pointer such that the registers of the block
|
||||
* can be accessed and indicate it has not been started yet.
|
||||
*/
|
||||
InstancePtr->Config.BaseAddr = EffectiveAddress;
|
||||
|
||||
InstancePtr->IsStarted = (u32)0;
|
||||
|
||||
/*
|
||||
* Indicate the instance is ready to use, successfully initialized.
|
||||
*/
|
||||
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
|
||||
|
||||
Status =(s32)XST_SUCCESS;
|
||||
}
|
||||
else {
|
||||
Status = (s32)XST_DEVICE_IS_STARTED;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Start the timer.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XScuTimer_Start(XScuTimer *InstancePtr)
|
||||
{
|
||||
u32 Register;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Read the contents of the Control register.
|
||||
*/
|
||||
Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET);
|
||||
|
||||
/*
|
||||
* Set the 'timer enable' bit in the register.
|
||||
*/
|
||||
Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
|
||||
|
||||
/*
|
||||
* Update the Control register with the new value.
|
||||
*/
|
||||
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET, Register);
|
||||
|
||||
/*
|
||||
* Indicate that the device is started.
|
||||
*/
|
||||
InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Stop the timer.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XScuTimer_Stop(XScuTimer *InstancePtr)
|
||||
{
|
||||
u32 Register;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Read the contents of the Control register.
|
||||
*/
|
||||
Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET);
|
||||
|
||||
/*
|
||||
* Clear the 'timer enable' bit in the register.
|
||||
*/
|
||||
Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
|
||||
|
||||
/*
|
||||
* Update the Control register with the new value.
|
||||
*/
|
||||
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET, Register);
|
||||
|
||||
/*
|
||||
* Indicate that the device is stopped.
|
||||
*/
|
||||
InstancePtr->IsStarted = (u32)0;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the prescaler bits in the timer control register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
****************************************************************************/
|
||||
void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
|
||||
{
|
||||
u32 ControlReg;
|
||||
|
||||
/*
|
||||
* Assert to validate input arguments.
|
||||
*/
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
/*
|
||||
* Read the Timer control register.
|
||||
*/
|
||||
ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET);
|
||||
|
||||
/*
|
||||
* Clear all of the prescaler control bits in the register.
|
||||
*/
|
||||
ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
|
||||
|
||||
/*
|
||||
* Set the prescaler value.
|
||||
*/
|
||||
ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
|
||||
|
||||
/*
|
||||
* Write the register with the new values.
|
||||
*/
|
||||
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET, ControlReg);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function returns the current prescaler value.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return The prescaler value.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
|
||||
{
|
||||
u32 ControlReg;
|
||||
|
||||
/*
|
||||
* Assert to validate input arguments.
|
||||
*/
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Read the Timer control register.
|
||||
*/
|
||||
ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET);
|
||||
ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
|
||||
|
||||
return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by HSI.
|
||||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
*copies of the Software, and to permit persons to whom the Software is
|
||||
*furnished to do so, subject to the following conditions:
|
||||
*
|
||||
*The above copyright notice and this permission notice shall be included in
|
||||
*all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
*(a) running on a Xilinx device, or
|
||||
*(b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
*in advertising or otherwise to promote the sale, use or other dealings in
|
||||
*this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
|
||||
*
|
||||
* Description: Driver configuration
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xscutimer.h"
|
||||
|
||||
#include "mmio_access.h"
|
||||
|
||||
/*
|
||||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XScuTimer_Config XScuTimer_ConfigTable[] = {
|
||||
{ XPAR_PS7_SCUTIMER_0_DEVICE_ID,
|
||||
MMIO_P2V_WO(XPAR_PS7_SCUTIMER_0_BASEADDR) }
|
||||
};
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscutimer_selftest.c
|
||||
* @addtogroup scutimer_v2_1
|
||||
* @{
|
||||
*
|
||||
* Contains diagnostic self-test functions for the XScuTimer driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a nm 03/10/10 First release
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xscutimer.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the timer. This test clears the timer enable bit in
|
||||
* the control register, writes to the timer load register and verifies the
|
||||
* value read back matches the value written and restores the control register
|
||||
* and the timer load register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuTimer instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if self-test was successful.
|
||||
* - XST_FAILURE if self test was not successful.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
|
||||
{
|
||||
u32 Register;
|
||||
u32 CtrlOrig;
|
||||
u32 LoadOrig;
|
||||
s32 Status;
|
||||
|
||||
/*
|
||||
* Assert to ensure the inputs are valid and the instance has been
|
||||
* initialized.
|
||||
*/
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Save the contents of the Control Register and stop the timer.
|
||||
*/
|
||||
CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET);
|
||||
Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
|
||||
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET, Register);
|
||||
|
||||
/*
|
||||
* Save the contents of the Load Register.
|
||||
* Load a new test value in the Load Register, read it back and
|
||||
* compare it with the written value.
|
||||
*/
|
||||
LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
|
||||
XSCUTIMER_LOAD_OFFSET);
|
||||
XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
|
||||
Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
|
||||
XSCUTIMER_LOAD_OFFSET);
|
||||
|
||||
/*
|
||||
* Restore the contents of the Load Register and Control Register.
|
||||
*/
|
||||
XScuTimer_LoadTimer(InstancePtr, LoadOrig);
|
||||
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
|
||||
XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
|
||||
|
||||
/*
|
||||
* Return a Failure if the contents of the Load Register do not
|
||||
* match with the value written to it.
|
||||
*/
|
||||
if (Register != XSCUTIMER_SELFTEST_VALUE) {
|
||||
Status = (s32)XST_FAILURE;
|
||||
}
|
||||
else {
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscutimer_sinit.c
|
||||
* @addtogroup scutimer_v2_1
|
||||
* @{
|
||||
*
|
||||
* This file contains method for static initialization (compile-time) of the
|
||||
* driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- ---------------------------------------------
|
||||
* 1.00a nm 03/10/10 First release
|
||||
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xscutimer.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Lookup the device configuration based on the unique device ID. The table
|
||||
* contains the configuration info for each device in the system.
|
||||
*
|
||||
* @param DeviceId is the unique device ID of the device being looked up.
|
||||
*
|
||||
* @return A pointer to the configuration table entry corresponding to the
|
||||
* given device ID, or NULL if no match is found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XScuTimer_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
|
||||
if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XScuTimer_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (XScuTimer_Config *)CfgPtr;
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xtime_l.c
|
||||
*
|
||||
* This file contains low level functions to get/set time from the Global Timer
|
||||
* register in the ARM Cortex A9 MP core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ---------------------------------------------------
|
||||
* 1.00a rp/sdm 11/03/09 Initial release.
|
||||
* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
|
||||
* </pre>
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xtime_l.h"
|
||||
#include "xil_io.h"
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Set the time in the Global Timer Counter Register.
|
||||
*
|
||||
* @param Value to be written to the Global Timer Counter Register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note In multiprocessor environment reference time will reset/lost for
|
||||
* all processors, when this function called by any one processor.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XTime_SetTime(XTime Xtime_Global)
|
||||
{
|
||||
/* Disable Global Timer */
|
||||
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
|
||||
|
||||
/* Updating Global Timer Counter Register */
|
||||
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
|
||||
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
|
||||
(u32)((u32)(Xtime_Global >> 32U)));
|
||||
|
||||
/* Enable Global Timer */
|
||||
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Get the time from the Global Timer Counter Register.
|
||||
*
|
||||
* @param Pointer to the location to be updated with the time.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XTime_GetTime(XTime* Xtime_Global)
|
||||
{
|
||||
u32 low;
|
||||
u32 high;
|
||||
|
||||
/* Reading Global Timer Counter Register */
|
||||
do {
|
||||
high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
|
||||
low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
|
||||
} while (Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
|
||||
|
||||
*Xtime_Global = (((XTime)high) << 32U) | (XTime)low;
|
||||
}
|
||||
|
|
@ -35,6 +35,7 @@ Modification:
|
|||
struct XiziClockDriver {
|
||||
void (*sys_clock_init)();
|
||||
uint32_t (*get_clock_int)();
|
||||
bool (*is_timer_expired)();
|
||||
void (*clear_clock_intr)();
|
||||
|
||||
uint64_t (*get_tick)();
|
||||
|
|
|
|||
|
|
@ -1,4 +1,16 @@
|
|||
|
||||
SRC_FILES := vector.S trampoline.S $(BOARD)/trap_common.c error_debug.c spinlock.c hard_spinlock.S
|
||||
|
||||
ifeq ($(BOARD), imx6q-sabrelite)
|
||||
SRC_DIR := gicv2
|
||||
SRC_FILES := vector.S trampoline.S trap_common.c error_debug.c spinlock.c hard_spinlock.S
|
||||
endif
|
||||
|
||||
ifeq ($(BOARD), zynq7000-zc702)
|
||||
# SRC_DIR := gicv2
|
||||
SRC_DIR := gicv3
|
||||
SRC_FILES += $(BOARD)/xil_assert.c
|
||||
# SRC_FILES := vector.S trampoline.S imx6q-sabrelite/trap_common.c error_debug.c spinlock.c hard_spinlock.S
|
||||
endif
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
SRC_FILES := xscugic_g.c \
|
||||
xscugic_hw.c \
|
||||
xscugic_intr.c \
|
||||
xscugic_sinit.c \
|
||||
xscugic.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
234
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xil_exception.h
Executable file
234
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xil_exception.h
Executable file
|
|
@ -0,0 +1,234 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_exception.h
|
||||
*
|
||||
* This header file contains ARM Cortex A9 specific exception related APIs.
|
||||
* For exception related functions that can be used across all Xilinx supported
|
||||
* processors, please use xil_exception.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 1.00a ecm/sdm 11/04/09 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
|
||||
#define XIL_EXCEPTION_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
|
||||
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
|
||||
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
|
||||
|
||||
#define XIL_EXCEPTION_ID_FIRST 0U
|
||||
#define XIL_EXCEPTION_ID_RESET 0U
|
||||
#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
|
||||
#define XIL_EXCEPTION_ID_SWI_INT 2U
|
||||
#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
|
||||
#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
|
||||
#define XIL_EXCEPTION_ID_IRQ_INT 5U
|
||||
#define XIL_EXCEPTION_ID_FIQ_INT 6U
|
||||
#define XIL_EXCEPTION_ID_LAST 6U
|
||||
|
||||
/*
|
||||
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
|
||||
*/
|
||||
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/**
|
||||
* This typedef is the exception handler function.
|
||||
*/
|
||||
typedef void (*Xil_ExceptionHandler)(void *data);
|
||||
typedef void (*Xil_InterruptHandler)(void *data);
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Enable Exceptions.
|
||||
*
|
||||
* @param Mask for exceptions to be enabled.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note If bit is 0, exception is enabled.
|
||||
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifdef __GNUC__
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
|
||||
#elif defined (__ICCARM__)
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
|
||||
#else
|
||||
#define Xil_ExceptionEnableMask(Mask) \
|
||||
{ \
|
||||
register u32 Reg __asm("cpsr"); \
|
||||
mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Enable the IRQ exception.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_ExceptionEnable() \
|
||||
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Disable Exceptions.
|
||||
*
|
||||
* @param Mask for exceptions to be enabled.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note If bit is 1, exception is disabled.
|
||||
* C-Style signature: Xil_ExceptionDisableMask(Mask)
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifdef __GNUC__
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
|
||||
#elif defined (__ICCARM__)
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
|
||||
#else
|
||||
#define Xil_ExceptionDisableMask(Mask) \
|
||||
{ \
|
||||
register u32 Reg __asm("cpsr"); \
|
||||
mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Disable the IRQ exception.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_ExceptionDisable() \
|
||||
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Enable nested interrupts by clearing the I and F bits it CPSR
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note This macro is supposed to be used from interrupt handlers. In the
|
||||
* interrupt handler the interrupts are disabled by default (I and F
|
||||
* are 1). To allow nesting of interrupts, this macro should be
|
||||
* used. It clears the I and F bits by changing the ARM mode to
|
||||
* system mode. Once these bits are cleared and provided the
|
||||
* preemption of interrupt conditions are met in the GIC, nesting of
|
||||
* interrupts will start happening.
|
||||
* Caution: This macro must be used with caution. Before calling this
|
||||
* macro, the user must ensure that the source of the current IRQ
|
||||
* is appropriately cleared. Otherwise, as soon as we clear the I and
|
||||
* F bits, there can be an infinite loop of interrupts with an
|
||||
* eventual crash (all the stack space getting consumed).
|
||||
******************************************************************************/
|
||||
#define Xil_EnableNestedInterrupts() \
|
||||
__asm__ __volatile__ ("mrs lr, spsr"); \
|
||||
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
|
||||
__asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
|
||||
__asm__ __volatile__ ("stmfd sp!, {lr}");
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Disable the nested interrupts by setting the I and F bits.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note This macro is meant to be called in the interrupt service routines.
|
||||
* This macro cannot be used independently. It can only be used when
|
||||
* nesting of interrupts have been enabled by using the macro
|
||||
* Xil_EnableNestedInterrupts(). In a typical flow, the user first
|
||||
* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
|
||||
* point. The user then must call this macro before exiting the interrupt
|
||||
* service routine. This macro puts the ARM back in IRQ/FIQ mode and
|
||||
* hence sets back the I and F bits.
|
||||
******************************************************************************/
|
||||
#define Xil_DisableNestedInterrupts() \
|
||||
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
|
||||
__asm__ __volatile__ ("msr cpsr_c, #0x92"); \
|
||||
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
|
||||
__asm__ __volatile__ ("msr spsr_cxsf, lr");
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
|
||||
Xil_ExceptionHandler Handler,
|
||||
void *Data);
|
||||
|
||||
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
|
||||
|
||||
extern void Xil_ExceptionInit(void);
|
||||
extern void Xil_DataAbortHandler(void *CallBackRef);
|
||||
extern void Xil_PrefetchAbortHandler(void *CallBackRef);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XIL_EXCEPTION_H */
|
||||
|
|
@ -0,0 +1,731 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscugic.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @{
|
||||
*
|
||||
* Contains required functions for the XScuGic driver for the Interrupt
|
||||
* Controller. See xscugic.h for a detailed description of the driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- --------------------------------------------------------
|
||||
* 1.00a drg 01/19/10 First release
|
||||
* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
|
||||
* "Config" entry is now made as pointer in the XScuGic
|
||||
* structure, necessary changes are made.
|
||||
* The HandlerTable can now be populated through the low
|
||||
* level routine XScuGic_RegisterHandler added in this
|
||||
* release. Hence necessary checks are added not to
|
||||
* overwrite the HandlerTable entriesin function
|
||||
* XScuGic_CfgInitialize.
|
||||
* 1.03a srt 02/27/13 Added APIs
|
||||
* - XScuGic_SetPriTrigTypeByDistAddr()
|
||||
* - XScuGic_GetPriTrigTypeByDistAddr()
|
||||
* Removed Offset calculation macros, defined in _hw.h
|
||||
* (CR 702687)
|
||||
* Added support to direct interrupts to the appropriate CPU. Earlier
|
||||
* interrupts were directed to CPU1 (hard coded). Now depending
|
||||
* upon the CPU selected by the user (xparameters.h), interrupts
|
||||
* will be directed to the relevant CPU. This fixes CR 699688.
|
||||
*
|
||||
* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
|
||||
* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
|
||||
* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
|
||||
* This is fix for CR#705621.
|
||||
* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
|
||||
* in function XScuGic_CfgInitialize is removed as it was
|
||||
* a bug.
|
||||
* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
|
||||
* target CPU mapping
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xil_assert.h"
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
#include "xscugic.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
static void StubHandler(void* CallBackRef);
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* DistributorInit initializes the distributor of the GIC. The
|
||||
* initialization entails:
|
||||
*
|
||||
* - Write the trigger mode, priority and target CPU
|
||||
* - All interrupt sources are disabled
|
||||
* - Enable the distributor
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param CpuID is the Cpu ID to be initialized.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void DistributorInit(XScuGic* InstancePtr, u32 CpuID)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 LocalCpuID = CpuID;
|
||||
|
||||
#if USE_AMP == 1
|
||||
#warning "Building GIC for AMP"
|
||||
|
||||
/*
|
||||
* The distrubutor should not be initialized by FreeRTOS in the case of
|
||||
* AMP -- it is assumed that Linux is the master of this device in that
|
||||
* case.
|
||||
*/
|
||||
return;
|
||||
#endif
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
|
||||
|
||||
/*
|
||||
* Set the security domains in the int_security registers for
|
||||
* non-secure interrupts
|
||||
* All are secure, so leave at the default. Set to 1 for non-secure
|
||||
* interrupts.
|
||||
*/
|
||||
|
||||
/*
|
||||
* For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
|
||||
*/
|
||||
|
||||
/*
|
||||
* 1. The trigger mode in the int_config register
|
||||
* Only write to the SPI interrupts, so start at 32
|
||||
*/
|
||||
for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 16U) {
|
||||
/*
|
||||
* Each INT_ID uses two bits, or 16 INT_ID per register
|
||||
* Set them all to be level sensitive, active HIGH.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
|
||||
0U);
|
||||
}
|
||||
|
||||
#define DEFAULT_PRIORITY 0xa0a0a0a0U
|
||||
for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
|
||||
/*
|
||||
* 2. The priority using int the priority_level register
|
||||
* The priority_level and spi_target registers use one byte per
|
||||
* INT_ID.
|
||||
* Write a default value that can be changed elsewhere.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
|
||||
DEFAULT_PRIORITY);
|
||||
}
|
||||
|
||||
for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
|
||||
/*
|
||||
* 3. The CPU interface in the spi_target register
|
||||
* Only write to the SPI interrupts, so start at 32
|
||||
*/
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
LocalCpuID);
|
||||
}
|
||||
|
||||
for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 32U) {
|
||||
/*
|
||||
* 4. Enable the SPI using the enable_set register. Leave all
|
||||
* disabled for now.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
|
||||
0xFFFFFFFFU);
|
||||
}
|
||||
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
|
||||
XSCUGIC_EN_INT_MASK);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
|
||||
*
|
||||
* - Set the priority of the CPU
|
||||
* - Enable the CPU interface
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void CPUInitialize(XScuGic* InstancePtr)
|
||||
{
|
||||
/*
|
||||
* Program the priority mask of the CPU using the Priority mask register
|
||||
*/
|
||||
XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
|
||||
|
||||
/*
|
||||
* If the CPU operates in both security domains, set parameters in the
|
||||
* control_s register.
|
||||
* 1. Set FIQen=1 to use FIQ for secure interrupts,
|
||||
* 2. Program the AckCtl bit
|
||||
* 3. Program the SBPR bit to select the binary pointer behavior
|
||||
* 4. Set EnableS = 1 to enable secure interrupts
|
||||
* 5. Set EnbleNS = 1 to enable non secure interrupts
|
||||
*/
|
||||
|
||||
/*
|
||||
* If the CPU operates only in the secure domain, setup the
|
||||
* control_s register.
|
||||
* 1. Set FIQen=1,
|
||||
* 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
|
||||
* Only enable the IRQ output unless secure interrupts are needed.
|
||||
*/
|
||||
XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* CfgInitialize a specific interrupt controller instance/driver. The
|
||||
* initialization entails:
|
||||
*
|
||||
* - Initialize fields of the XScuGic structure
|
||||
* - Initial vector table with stub function calls
|
||||
* - All interrupt sources are disabled
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param ConfigPtr is a pointer to a config table for the particular
|
||||
* device this driver is associated with.
|
||||
* @param EffectiveAddr is the device base address in the virtual memory
|
||||
* address space. The caller is responsible for keeping the address
|
||||
* mapping from EffectiveAddr to the device physical base address
|
||||
* unchanged once this function is invoked. Unexpected errors may
|
||||
* occur if the address mapping changes after this function is
|
||||
* called. If address translation is not used, use
|
||||
* Config->BaseAddress for this parameters, passing the physical
|
||||
* address instead.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if initialization was successful
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XScuGic_CfgInitialize(XScuGic* InstancePtr,
|
||||
XScuGic_Config* ConfigPtr,
|
||||
u32 EffectiveAddr)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
|
||||
(void)EffectiveAddr;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(ConfigPtr != NULL);
|
||||
|
||||
if (InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
|
||||
|
||||
InstancePtr->IsReady = 0;
|
||||
InstancePtr->Config = ConfigPtr;
|
||||
|
||||
for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id++) {
|
||||
/*
|
||||
* Initalize the handler to point to a stub to handle an
|
||||
* interrupt which has not been connected to a handler. Only
|
||||
* initialize it if the handler is 0 which means it was not
|
||||
* initialized statically by the tools/user. Set the callback
|
||||
* reference to this instance so that unhandled interrupts
|
||||
* can be tracked.
|
||||
*/
|
||||
if ((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
|
||||
InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
|
||||
}
|
||||
InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
|
||||
}
|
||||
|
||||
DistributorInit(InstancePtr, Cpu_Id);
|
||||
CPUInitialize(InstancePtr);
|
||||
|
||||
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Makes the connection between the Int_Id of the interrupt source and the
|
||||
* associated handler that is to run when the interrupt is recognized. The
|
||||
* argument provided in this call as the Callbackref is used as the argument
|
||||
* for the handler when it is called.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param Int_Id contains the ID of the interrupt source and should be
|
||||
* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
|
||||
* @param Handler to the handler for that interrupt.
|
||||
* @param CallBackRef is the callback reference, usually the instance
|
||||
* pointer of the connecting driver.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if the handler was connected correctly.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* WARNING: The handler provided as an argument will overwrite any handler
|
||||
* that was previously connected.
|
||||
*
|
||||
****************************************************************************/
|
||||
s32 XScuGic_Connect(XScuGic* InstancePtr, u32 Int_Id,
|
||||
Xil_InterruptHandler Handler, void* CallBackRef)
|
||||
{
|
||||
/*
|
||||
* Assert the arguments
|
||||
*/
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertNonvoid(Handler != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* The Int_Id is used as an index into the table to select the proper
|
||||
* handler
|
||||
*/
|
||||
InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
|
||||
InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Updates the interrupt table with the Null Handler and NULL arguments at the
|
||||
* location pointed at by the Int_Id. This effectively disconnects that interrupt
|
||||
* source from any handler. The interrupt is disabled also.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
|
||||
* @param Int_Id contains the ID of the interrupt source and should
|
||||
* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XScuGic_Disconnect(XScuGic* InstancePtr, u32 Int_Id)
|
||||
{
|
||||
u32 Mask;
|
||||
|
||||
/*
|
||||
* Assert the arguments
|
||||
*/
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* The Int_Id is used to create the appropriate mask for the
|
||||
* desired bit position. Int_Id currently limited to 0 - 31
|
||||
*/
|
||||
Mask = 0x00000001U << (Int_Id % 32U);
|
||||
|
||||
/*
|
||||
* Disable the interrupt such that it won't occur while disconnecting
|
||||
* the handler, only disable the specified interrupt id without modifying
|
||||
* the other interrupt ids
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32U) * 4U), Mask);
|
||||
|
||||
/*
|
||||
* Disconnect the handler and connect a stub, the callback reference
|
||||
* must be set to this instance to allow unhandled interrupts to be
|
||||
* tracked
|
||||
*/
|
||||
InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
|
||||
InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enables the interrupt source provided as the argument Int_Id. Any pending
|
||||
* interrupt condition for the specified Int_Id will occur after this function is
|
||||
* called.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param Int_Id contains the ID of the interrupt source and should be
|
||||
* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XScuGic_Enable(XScuGic* InstancePtr, u32 Int_Id)
|
||||
{
|
||||
u32 Mask;
|
||||
|
||||
/*
|
||||
* Assert the arguments
|
||||
*/
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* The Int_Id is used to create the appropriate mask for the
|
||||
* desired bit position. Int_Id currently limited to 0 - 31
|
||||
*/
|
||||
Mask = 0x00000001U << (Int_Id % 32U);
|
||||
|
||||
/*
|
||||
* Enable the selected interrupt source by setting the
|
||||
* corresponding bit in the Enable Set register.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32U) * 4U), Mask);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Disables the interrupt source provided as the argument Int_Id such that the
|
||||
* interrupt controller will not cause interrupts for the specified Int_Id. The
|
||||
* interrupt controller will continue to hold an interrupt condition for the
|
||||
* Int_Id, but will not cause an interrupt.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param Int_Id contains the ID of the interrupt source and should be
|
||||
* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
void XScuGic_Disable(XScuGic* InstancePtr, u32 Int_Id)
|
||||
{
|
||||
u32 Mask;
|
||||
|
||||
/*
|
||||
* Assert the arguments
|
||||
*/
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* The Int_Id is used to create the appropriate mask for the
|
||||
* desired bit position. Int_Id currently limited to 0 - 31
|
||||
*/
|
||||
Mask = 0x00000001U << (Int_Id % 32U);
|
||||
|
||||
/*
|
||||
* Disable the selected interrupt source by setting the
|
||||
* corresponding bit in the IDR.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32U) * 4U), Mask);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Allows software to simulate an interrupt in the interrupt controller. This
|
||||
* function will only be successful when the interrupt controller has been
|
||||
* started in simulation mode. A simulated interrupt allows the interrupt
|
||||
* controller to be tested without any device to drive an interrupt input
|
||||
* signal into it.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param Int_Id is the software interrupt ID to simulate an interrupt.
|
||||
* @param Cpu_Id is the list of CPUs to send the interrupt.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
|
||||
* simulated
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XScuGic_SoftwareIntr(XScuGic* InstancePtr, u32 Int_Id, u32 Cpu_Id)
|
||||
{
|
||||
u32 Mask;
|
||||
|
||||
/*
|
||||
* Assert the arguments
|
||||
*/
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid(Int_Id <= 15U);
|
||||
Xil_AssertNonvoid(Cpu_Id <= 255U);
|
||||
|
||||
/*
|
||||
* The Int_Id is used to create the appropriate mask for the
|
||||
* desired interrupt. Int_Id currently limited to 0 - 15
|
||||
* Use the target list for the Cpu ID.
|
||||
*/
|
||||
Mask = ((Cpu_Id << 16U) | Int_Id) & (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
|
||||
|
||||
/*
|
||||
* Write to the Software interrupt trigger register. Use the appropriate
|
||||
* CPU Int_Id.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
|
||||
|
||||
/* Indicate the interrupt was successfully simulated */
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* A stub for the asynchronous callback. The stub is here in case the upper
|
||||
* layers forget to set the handler.
|
||||
*
|
||||
* @param CallBackRef is a pointer to the upper layer callback reference
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void StubHandler(void* CallBackRef)
|
||||
{
|
||||
/*
|
||||
* verify that the inputs are valid
|
||||
*/
|
||||
Xil_AssertVoid(CallBackRef != NULL);
|
||||
|
||||
/*
|
||||
* Indicate another unhandled interrupt for stats
|
||||
*/
|
||||
((XScuGic*)((void*)CallBackRef))->UnhandledInterrupts++;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Sets the interrupt priority and trigger type for the specificd IRQ source.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
* @param Priority is the new priority for the IRQ source. 0 is highest
|
||||
* priority, 0xF8 (248) is lowest. There are 32 priority levels
|
||||
* supported with a step of 8. Hence the supported priorities are
|
||||
* 0, 8, 16, 32, 40 ..., 248.
|
||||
* @param Trigger is the new trigger type for the IRQ source.
|
||||
* Each bit pair describes the configuration for an INT_ID.
|
||||
* SFI Read Only b10 always
|
||||
* PPI Read Only depending on how the PPIs are configured.
|
||||
* b01 Active HIGH level sensitive
|
||||
* b11 Rising edge sensitive
|
||||
* SPI LSB is read only.
|
||||
* b01 Active HIGH level sensitive
|
||||
* b11 Rising edge sensitive/
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_SetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
|
||||
u8 Priority, u8 Trigger)
|
||||
{
|
||||
u32 RegValue;
|
||||
u8 LocalPriority;
|
||||
LocalPriority = Priority;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
|
||||
Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
|
||||
|
||||
/*
|
||||
* Determine the register to write to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* The priority bits are Bits 7 to 3 in GIC Priority Register. This
|
||||
* means the number of priority levels supported are 32 and they are
|
||||
* in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
|
||||
* The lower order 3 bits are masked before putting it in the register.
|
||||
*/
|
||||
LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id % 4U) * 8U));
|
||||
RegValue |= (u32)LocalPriority << ((Int_Id % 4U) * 8U);
|
||||
|
||||
/*
|
||||
* Write the value back to the register.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
|
||||
/*
|
||||
* Determine the register to write to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id % 16U) * 2U));
|
||||
RegValue |= (u32)Trigger << ((Int_Id % 16U) * 2U);
|
||||
|
||||
/*
|
||||
* Write the value back to the register.
|
||||
*/
|
||||
XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Gets the interrupt priority and trigger type for the specificd IRQ source.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
* @param Priority is a pointer to the value of the priority of the IRQ
|
||||
* source. This is a return value.
|
||||
* @param Trigger is pointer to the value of the trigger of the IRQ
|
||||
* source. This is a return value.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_GetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
|
||||
u8* Priority, u8* Trigger)
|
||||
{
|
||||
u32 RegValue;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(Priority != NULL);
|
||||
Xil_AssertVoid(Trigger != NULL);
|
||||
|
||||
/*
|
||||
* Determine the register to read to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue = RegValue >> ((Int_Id % 4U) * 8U);
|
||||
*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
|
||||
|
||||
/*
|
||||
* Determine the register to read to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue = RegValue >> ((Int_Id % 16U) * 2U);
|
||||
|
||||
*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
|
||||
}
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Sets the target CPU for the interrupt of a peripheral
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Cpu_Id is a CPU number for which the interrupt has to be targeted
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_InterruptMaptoCpu(XScuGic* InstancePtr, u8 Cpu_Id, u32 Int_Id)
|
||||
{
|
||||
u32 RegValue, Offset;
|
||||
RegValue = XScuGic_DistReadReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
|
||||
|
||||
Offset = (Int_Id & 0x3);
|
||||
|
||||
RegValue = (RegValue | (~(0xFF << (Offset * 8))));
|
||||
RegValue |= ((Cpu_Id) << (Offset * 8));
|
||||
|
||||
XScuGic_DistWriteReg(InstancePtr,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscugic.h
|
||||
* @addtogroup scugic_v3_1
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* The generic interrupt controller driver component.
|
||||
*
|
||||
* The interrupt controller driver uses the idea of priority for the various
|
||||
* handlers. Priority is an integer within the range of 1 and 31 inclusive with
|
||||
* default of 1 being the highest priority interrupt source. The priorities
|
||||
* of the various sources can be dynamically altered as needed through
|
||||
* hardware configuration.
|
||||
*
|
||||
* The generic interrupt controller supports the following
|
||||
* features:
|
||||
*
|
||||
* - specific individual interrupt enabling/disabling
|
||||
* - specific individual interrupt acknowledging
|
||||
* - attaching specific callback function to handle interrupt source
|
||||
* - assigning desired priority to interrupt source if default is not
|
||||
* acceptable.
|
||||
*
|
||||
* Details about connecting the interrupt handler of the driver are contained
|
||||
* in the source file specific to interrupt processing, xscugic_intr.c.
|
||||
*
|
||||
* This driver is intended to be RTOS and processor independent. It works with
|
||||
* physical addresses only. Any needs for dynamic memory management, threads
|
||||
* or thread mutual exclusion, virtual memory, or cache control must be
|
||||
* satisfied by the layer above this driver.
|
||||
*
|
||||
* <b>Interrupt Vector Tables</b>
|
||||
*
|
||||
* The device ID of the interrupt controller device is used by the driver as a
|
||||
* direct index into the configuration data table. The user should populate the
|
||||
* vector table with handlers and callbacks at run-time using the
|
||||
* XScuGic_Connect() and XScuGic_Disconnect() functions.
|
||||
*
|
||||
* Each vector table entry corresponds to a device that can generate an
|
||||
* interrupt. Each entry contains an interrupt handler function and an
|
||||
* argument to be passed to the handler when an interrupt occurs. The
|
||||
* user must use XScuGic_Connect() when the interrupt handler takes an
|
||||
* argument other than the base address.
|
||||
*
|
||||
* <b>Nested Interrupts Processing</b>
|
||||
*
|
||||
* Nested interrupts are not supported by this driver.
|
||||
*
|
||||
* NOTE:
|
||||
* The generic interrupt controller is not a part of the snoop control unit
|
||||
* as indicated by the prefix "scu" in the name of the driver.
|
||||
* It is an independent module in APU.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------------
|
||||
* 1.00a drg 01/19/00 First release
|
||||
* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
|
||||
* The HandlerTable (of type XScuGic_VectorTableEntry) is
|
||||
* moved to XScuGic_Config structure from XScuGic structure.
|
||||
*
|
||||
* The "Config" entry in XScuGic structure is made as
|
||||
* pointer for better efficiency.
|
||||
*
|
||||
* A new file named as xscugic_hw.c is now added. It is
|
||||
* to implement low level driver routines without using
|
||||
* any xscugic instance pointer. They are useful when the
|
||||
* user wants to use xscugic through device id or
|
||||
* base address. The driver routines provided are explained
|
||||
* below.
|
||||
* XScuGic_DeviceInitialize that takes device id as
|
||||
* argument and initializes the device (without calling
|
||||
* XScuGic_CfgInitialize).
|
||||
* XScuGic_DeviceInterruptHandler that takes device id
|
||||
* as argument and calls appropriate handlers from the
|
||||
* HandlerTable.
|
||||
* XScuGic_RegisterHandler that registers a new handler
|
||||
* by taking xscugic hardware base address as argument.
|
||||
* LookupConfigByBaseAddress is used to return the
|
||||
* corresponding config structure from XScuGic_ConfigTable
|
||||
* based on the scugic base address passed.
|
||||
* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
|
||||
* structure.
|
||||
* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
|
||||
* *_hw.h
|
||||
* Added APIs
|
||||
* - XScuGic_SetPriTrigTypeByDistAddr()
|
||||
* - XScuGic_GetPriTrigTypeByDistAddr()
|
||||
* (CR 702687)
|
||||
* Added support to direct interrupts to the appropriate CPU. Earlier
|
||||
* interrupts were directed to CPU1 (hard coded). Now depending
|
||||
* upon the CPU selected by the user (xparameters.h), interrupts
|
||||
* will be directed to the relevant CPU. This fixes CR 699688.
|
||||
* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
|
||||
* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
|
||||
* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
|
||||
* This is fix for CR#705621.
|
||||
* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
|
||||
* xparameters.h. Fix for CR's 690505, 708928 & 719359.
|
||||
* 2.0 adk 12/10/13 Updated as per the New Tcl API's
|
||||
* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XSCUGIC_H /* prevent circular inclusions */
|
||||
#define XSCUGIC_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_exception.h"
|
||||
#include "xil_io.h"
|
||||
#include "xscugic_hw.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/* The following data type defines each entry in an interrupt vector table.
|
||||
* The callback reference is the base address of the interrupting device
|
||||
* for the low level driver and an instance pointer for the high level driver.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
Xil_InterruptHandler Handler;
|
||||
void* CallBackRef;
|
||||
} XScuGic_VectorTableEntry;
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
u32 CpuBaseAddress; /**< CPU Interface Register base address */
|
||||
u32 DistBaseAddress; /**< Distributor Register base address */
|
||||
XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS]; /**<
|
||||
Vector table of interrupt handlers */
|
||||
} XScuGic_Config;
|
||||
|
||||
/**
|
||||
* The XScuGic driver instance data. The user is required to allocate a
|
||||
* variable of this type for every intc device in the system. A pointer
|
||||
* to a variable of this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
XScuGic_Config* Config; /**< Configuration table entry */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
u32 UnhandledInterrupts; /**< Intc Statistics */
|
||||
} XScuGic;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write the given CPU Interface register
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param RegOffset is the register offset to be written
|
||||
* @param Data is the 32-bit value to write to the register
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
|
||||
(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
|
||||
((u32)(Data))))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the given CPU Interface register
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param RegOffset is the register offset to be read
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
|
||||
(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write the given Distributor Interface register
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param RegOffset is the register offset to be written
|
||||
* @param Data is the 32-bit value to write to the register
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
|
||||
(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
|
||||
((u32)(Data))))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the given Distributor Interface register
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param RegOffset is the register offset to be read
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
|
||||
(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*
|
||||
* Required functions in xscugic.c
|
||||
*/
|
||||
|
||||
s32 XScuGic_Connect(XScuGic* InstancePtr, u32 Int_Id,
|
||||
Xil_InterruptHandler Handler, void* CallBackRef);
|
||||
void XScuGic_Disconnect(XScuGic* InstancePtr, u32 Int_Id);
|
||||
|
||||
void XScuGic_Enable(XScuGic* InstancePtr, u32 Int_Id);
|
||||
void XScuGic_Disable(XScuGic* InstancePtr, u32 Int_Id);
|
||||
|
||||
s32 XScuGic_CfgInitialize(XScuGic* InstancePtr, XScuGic_Config* ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
|
||||
s32 XScuGic_SoftwareIntr(XScuGic* InstancePtr, u32 Int_Id, u32 Cpu_Id);
|
||||
|
||||
void XScuGic_GetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
|
||||
u8* Priority, u8* Trigger);
|
||||
void XScuGic_SetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
|
||||
u8 Priority, u8 Trigger);
|
||||
void XScuGic_InterruptMaptoCpu(XScuGic* InstancePtr, u8 Cpu_Id, u32 Int_Id);
|
||||
/*
|
||||
* Initialization functions in xscugic_sinit.c
|
||||
*/
|
||||
XScuGic_Config* XScuGic_LookupConfig(u16 DeviceId);
|
||||
|
||||
/*
|
||||
* Interrupt functions in xscugic_intr.c
|
||||
*/
|
||||
void XScuGic_InterruptHandler(XScuGic* InstancePtr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by HSI.
|
||||
* Version:
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.*
|
||||
*Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
*of this software and associated documentation files (the Software), to deal
|
||||
*in the Software without restriction, including without limitation the rights
|
||||
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
*copies of the Software, and to permit persons to whom the Software is
|
||||
*furnished to do so, subject to the following conditions:
|
||||
*
|
||||
*The above copyright notice and this permission notice shall be included in
|
||||
*all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
*(a) running on a Xilinx device, or
|
||||
*(b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
*in advertising or otherwise to promote the sale, use or other dealings in
|
||||
*this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
|
||||
*
|
||||
* Description: Driver configuration
|
||||
*
|
||||
*******************************************************************/
|
||||
#include "xparameters.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
#include "mmio_access.h"
|
||||
|
||||
/*
|
||||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XScuGic_Config XScuGic_ConfigTable[] = {
|
||||
{ XPAR_PS7_SCUGIC_0_DEVICE_ID,
|
||||
MMIO_P2V_WO(XPAR_PS7_SCUGIC_0_BASEADDR),
|
||||
MMIO_P2V_WO(XPAR_PS7_SCUGIC_0_DIST_BASEADDR) }
|
||||
};
|
||||
|
|
@ -0,0 +1,563 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscugic_hw.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @{
|
||||
*
|
||||
* This file contains low-level driver functions that can be used to access the
|
||||
* device. The user should refer to the hardware device specification for more
|
||||
* details of the device operation.
|
||||
* These routines are used when the user does not want to create an instance of
|
||||
* XScuGic structure but still wants to use the ScuGic device. Hence the
|
||||
* routines provided here take device id or scugic base address as arguments.
|
||||
* Separate static versions of DistInit and CPUInit are provided to implement
|
||||
* the low level driver routines.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.01a sdm 07/18/11 First release
|
||||
* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
|
||||
* 702687).
|
||||
* Added support to direct interrupts to the appropriate CPU.
|
||||
* Earlier interrupts were directed to CPU1 (hard coded). Now
|
||||
* depending upon the CPU selected by the user (xparameters.h),
|
||||
* interrupts will be directed to the relevant CPU.
|
||||
* This fixes CR 699688.
|
||||
* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
|
||||
* XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_assert.h"
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
static void DistInit(XScuGic_Config* Config, u32 CpuID);
|
||||
static void CPUInit(XScuGic_Config* Config);
|
||||
static XScuGic_Config* LookupConfigByBaseAddress(u32 CpuBaseAddress);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* DistInit initializes the distributor of the GIC. The
|
||||
* initialization entails:
|
||||
*
|
||||
* - Write the trigger mode, priority and target CPU
|
||||
* - All interrupt sources are disabled
|
||||
* - Enable the distributor
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
* @param CpuID is the Cpu ID to be initialized.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void DistInit(XScuGic_Config* Config, u32 CpuID)
|
||||
{
|
||||
u32 Int_Id;
|
||||
u32 LocalCpuID = CpuID;
|
||||
|
||||
#if USE_AMP == 1
|
||||
#warning "Building GIC for AMP"
|
||||
|
||||
/*
|
||||
* The distrubutor should not be initialized by FreeRTOS in the case of
|
||||
* AMP -- it is assumed that Linux is the master of this device in that
|
||||
* case.
|
||||
*/
|
||||
return;
|
||||
#endif
|
||||
|
||||
XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
|
||||
|
||||
/*
|
||||
* Set the security domains in the int_security registers for non-secure
|
||||
* interrupts. All are secure, so leave at the default. Set to 1 for
|
||||
* non-secure interrupts.
|
||||
*/
|
||||
|
||||
/*
|
||||
* For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
|
||||
*/
|
||||
|
||||
/*
|
||||
* 1. The trigger mode in the int_config register
|
||||
* Only write to the SPI interrupts, so start at 32
|
||||
*/
|
||||
for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 16U) {
|
||||
/*
|
||||
* Each INT_ID uses two bits, or 16 INT_ID per register
|
||||
* Set them all to be level sensitive, active HIGH.
|
||||
*/
|
||||
XScuGic_WriteReg(Config->DistBaseAddress,
|
||||
XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
|
||||
}
|
||||
|
||||
#define DEFAULT_PRIORITY 0xa0a0a0a0U
|
||||
for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
|
||||
/*
|
||||
* 2. The priority using int the priority_level register
|
||||
* The priority_level and spi_target registers use one byte per
|
||||
* INT_ID.
|
||||
* Write a default value that can be changed elsewhere.
|
||||
*/
|
||||
XScuGic_WriteReg(Config->DistBaseAddress,
|
||||
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
|
||||
DEFAULT_PRIORITY);
|
||||
}
|
||||
|
||||
for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
|
||||
/*
|
||||
* 3. The CPU interface in the spi_target register
|
||||
* Only write to the SPI interrupts, so start at 32
|
||||
*/
|
||||
LocalCpuID |= LocalCpuID << 8U;
|
||||
LocalCpuID |= LocalCpuID << 16U;
|
||||
|
||||
XScuGic_WriteReg(Config->DistBaseAddress,
|
||||
XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
|
||||
}
|
||||
|
||||
for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 32U) {
|
||||
/*
|
||||
* 4. Enable the SPI using the enable_set register. Leave all disabled
|
||||
* for now.
|
||||
*/
|
||||
XScuGic_WriteReg(Config->DistBaseAddress,
|
||||
XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
|
||||
Int_Id),
|
||||
0xFFFFFFFFU);
|
||||
}
|
||||
|
||||
XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
|
||||
XSCUGIC_EN_INT_MASK);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
|
||||
*
|
||||
* - Set the priority of the CPU.
|
||||
* - Enable the CPU interface
|
||||
*
|
||||
* @param ConfigPtr is a pointer to a config table for the particular
|
||||
* device this driver is associated with.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void CPUInit(XScuGic_Config* Config)
|
||||
{
|
||||
/*
|
||||
* Program the priority mask of the CPU using the Priority mask
|
||||
* register
|
||||
*/
|
||||
XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
|
||||
0xF0U);
|
||||
|
||||
/*
|
||||
* If the CPU operates in both security domains, set parameters in the
|
||||
* control_s register.
|
||||
* 1. Set FIQen=1 to use FIQ for secure interrupts,
|
||||
* 2. Program the AckCtl bit
|
||||
* 3. Program the SBPR bit to select the binary pointer behavior
|
||||
* 4. Set EnableS = 1 to enable secure interrupts
|
||||
* 5. Set EnbleNS = 1 to enable non secure interrupts
|
||||
*/
|
||||
|
||||
/*
|
||||
* If the CPU operates only in the secure domain, setup the
|
||||
* control_s register.
|
||||
* 1. Set FIQen=1,
|
||||
* 2. Set EnableS=1, to enable the CPU interface to signal secure .
|
||||
* interrupts Only enable the IRQ output unless secure interrupts
|
||||
* are needed.
|
||||
*/
|
||||
XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* CfgInitialize a specific interrupt controller instance/driver. The
|
||||
* initialization entails:
|
||||
*
|
||||
* - Initialize fields of the XScuGic structure
|
||||
* - Initial vector table with stub function calls
|
||||
* - All interrupt sources are disabled
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
|
||||
* @param ConfigPtr is a pointer to a config table for the particular device
|
||||
* this driver is associated with.
|
||||
* @param EffectiveAddr is the device base address in the virtual memory address
|
||||
* space. The caller is responsible for keeping the address mapping
|
||||
* from EffectiveAddr to the device physical base address unchanged
|
||||
* once this function is invoked. Unexpected errors may occur if the
|
||||
* address mapping changes after this function is called. If address
|
||||
* translation is not used, use Config->BaseAddress for this parameters,
|
||||
* passing the physical address instead.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if initialization was successful
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XScuGic_DeviceInitialize(u32 DeviceId)
|
||||
{
|
||||
XScuGic_Config* Config;
|
||||
u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
|
||||
|
||||
Config = &XScuGic_ConfigTable[(u32)DeviceId];
|
||||
|
||||
DistInit(Config, Cpu_Id);
|
||||
|
||||
CPUInit(Config);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function is the primary interrupt handler for the driver. It must be
|
||||
* connected to the interrupt source such that it is called when an interrupt of
|
||||
* the interrupt controller is active. It will resolve which interrupts are
|
||||
* active and enabled and call the appropriate interrupt handler. It uses
|
||||
* the Interrupt Type information to determine when to acknowledge the
|
||||
* interrupt.Highest priority interrupts are serviced first.
|
||||
*
|
||||
* This function assumes that an interrupt vector table has been previously
|
||||
* initialized. It does not verify that entries in the table are valid before
|
||||
* calling an interrupt handler.
|
||||
*
|
||||
* @param DeviceId is the unique identifier for the ScuGic device.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XScuGic_DeviceInterruptHandler(void* DeviceId)
|
||||
{
|
||||
|
||||
u32 InterruptID;
|
||||
u32 IntIDFull;
|
||||
XScuGic_VectorTableEntry* TablePtr;
|
||||
XScuGic_Config* CfgPtr;
|
||||
|
||||
CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId];
|
||||
|
||||
/*
|
||||
* Read the int_ack register to identify the highest priority
|
||||
* interrupt ID and make sure it is valid. Reading Int_Ack will
|
||||
* clear the interrupt in the GIC.
|
||||
*/
|
||||
IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
|
||||
InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
|
||||
if (XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID) {
|
||||
goto IntrExit;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interrupt is shared, do some locking here if there are
|
||||
* multiple processors.
|
||||
*/
|
||||
/*
|
||||
* If pre-eption is required:
|
||||
* Re-enable pre-emption by setting the CPSR I bit for non-secure ,
|
||||
* interrupts or the F bit for secure interrupts
|
||||
*/
|
||||
|
||||
/*
|
||||
* If we need to change security domains, issue a SMC instruction here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Execute the ISR. Jump into the Interrupt service routine based on
|
||||
* the IRQSource. A software trigger is cleared by the ACK.
|
||||
*/
|
||||
TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
|
||||
if (TablePtr != NULL) {
|
||||
TablePtr->Handler(TablePtr->CallBackRef);
|
||||
}
|
||||
|
||||
IntrExit:
|
||||
/*
|
||||
* Write to the EOI register, we are all done here.
|
||||
* Let this function return, the boot code will restore the stack.
|
||||
*/
|
||||
XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
|
||||
|
||||
/*
|
||||
* Return from the interrupt. Change security domains could happen
|
||||
* here.
|
||||
*/
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Register a handler function for a specific interrupt ID. The vector table
|
||||
* of the interrupt controller is updated, overwriting any previous handler.
|
||||
* The handler function will be called when an interrupt occurs for the given
|
||||
* interrupt ID.
|
||||
*
|
||||
* @param BaseAddress is the CPU Interface Register base address of the
|
||||
* interrupt controller whose vector table will be modified.
|
||||
* @param InterruptId is the interrupt ID to be associated with the input
|
||||
* handler.
|
||||
* @param Handler is the function pointer that will be added to
|
||||
* the vector table for the given interrupt ID.
|
||||
* @param CallBackRef is the argument that will be passed to the new
|
||||
* handler function when it is called. This is user-specific.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* Note that this function has no effect if the input base address is invalid.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
|
||||
Xil_InterruptHandler IntrHandler, void* CallBackRef)
|
||||
{
|
||||
XScuGic_Config* CfgPtr;
|
||||
CfgPtr = LookupConfigByBaseAddress(BaseAddress);
|
||||
|
||||
if (CfgPtr != NULL) {
|
||||
if (IntrHandler != NULL) {
|
||||
CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
|
||||
}
|
||||
if (CallBackRef != NULL) {
|
||||
CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Looks up the device configuration based on the CPU interface base address of
|
||||
* the device. A table contains the configuration info for each device in the
|
||||
* system.
|
||||
*
|
||||
* @param CpuBaseAddress is the CPU Interface Register base address.
|
||||
*
|
||||
* @return A pointer to the configuration structure for the specified
|
||||
* device, or NULL if the device was not found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static XScuGic_Config* LookupConfigByBaseAddress(u32 CpuBaseAddress)
|
||||
{
|
||||
XScuGic_Config* CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
|
||||
if (XScuGic_ConfigTable[Index].CpuBaseAddress == CpuBaseAddress) {
|
||||
CfgPtr = &XScuGic_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (XScuGic_Config*)CfgPtr;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Sets the interrupt priority and trigger type for the specificd IRQ source.
|
||||
*
|
||||
* @param BaseAddr is the device base address
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
* @param Priority is the new priority for the IRQ source. 0 is highest
|
||||
* priority, 0xF8 (248) is lowest. There are 32 priority levels
|
||||
* supported with a step of 8. Hence the supported priorities are
|
||||
* 0, 8, 16, 32, 40 ..., 248.
|
||||
* @param Trigger is the new trigger type for the IRQ source.
|
||||
* Each bit pair describes the configuration for an INT_ID.
|
||||
* SFI Read Only b10 always
|
||||
* PPI Read Only depending on how the PPIs are configured.
|
||||
* b01 Active HIGH level sensitive
|
||||
* b11 Rising edge sensitive
|
||||
* SPI LSB is read only.
|
||||
* b01 Active HIGH level sensitive
|
||||
* b11 Rising edge sensitive/
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note This API has the similar functionality of XScuGic_SetPriority
|
||||
* TriggerType() and should be used when there is no InstancePtr.
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
||||
u8 Priority, u8 Trigger)
|
||||
{
|
||||
u32 RegValue;
|
||||
u8 LocalPriority = Priority;
|
||||
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
|
||||
Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
|
||||
|
||||
/*
|
||||
* Determine the register to write to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_ReadReg(DistBaseAddress,
|
||||
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* The priority bits are Bits 7 to 3 in GIC Priority Register. This
|
||||
* means the number of priority levels supported are 32 and they are
|
||||
* in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
|
||||
* The lower order 3 bits are masked before putting it in the register.
|
||||
*/
|
||||
LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id % 4U) * 8U));
|
||||
RegValue |= (u32)LocalPriority << ((Int_Id % 4U) * 8U);
|
||||
|
||||
/*
|
||||
* Write the value back to the register.
|
||||
*/
|
||||
XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
/*
|
||||
* Determine the register to write to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_ReadReg(DistBaseAddress,
|
||||
XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id % 16U) * 2U));
|
||||
RegValue |= (u32)Trigger << ((Int_Id % 16U) * 2U);
|
||||
|
||||
/*
|
||||
* Write the value back to the register.
|
||||
*/
|
||||
XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
|
||||
RegValue);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Gets the interrupt priority and trigger type for the specificd IRQ source.
|
||||
*
|
||||
* @param BaseAddr is the device base address
|
||||
* @param Int_Id is the IRQ source number to modify
|
||||
* @param Priority is a pointer to the value of the priority of the IRQ
|
||||
* source. This is a return value.
|
||||
* @param Trigger is pointer to the value of the trigger of the IRQ
|
||||
* source. This is a return value.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note This API has the similar functionality of XScuGic_GetPriority
|
||||
* TriggerType() and should be used when there is no InstancePtr.
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
||||
u8* Priority, u8* Trigger)
|
||||
{
|
||||
u32 RegValue;
|
||||
|
||||
Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
|
||||
Xil_AssertVoid(Priority != NULL);
|
||||
Xil_AssertVoid(Trigger != NULL);
|
||||
|
||||
/*
|
||||
* Determine the register to read to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_ReadReg(DistBaseAddress,
|
||||
XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue = RegValue >> ((Int_Id % 4U) * 8U);
|
||||
*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
|
||||
|
||||
/*
|
||||
* Determine the register to read to using the Int_Id.
|
||||
*/
|
||||
RegValue = XScuGic_ReadReg(DistBaseAddress,
|
||||
XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
|
||||
|
||||
/*
|
||||
* Shift and Mask the correct bits for the priority and trigger in the
|
||||
* register
|
||||
*/
|
||||
RegValue = RegValue >> ((Int_Id % 16U) * 2U);
|
||||
|
||||
*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,635 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscugic_hw.h
|
||||
* @addtogroup scugic_v3_1
|
||||
* @{
|
||||
*
|
||||
* This header file contains identifiers and HW access functions (or
|
||||
* macros) that can be used to access the device. The user should refer to the
|
||||
* hardware device specification for more details of the device operation.
|
||||
* The driver functions/APIs are defined in xscugic.h.
|
||||
*
|
||||
* This GIC device has two parts, a distributor and CPU interface(s). Each part
|
||||
* has separate register definition sections.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------------
|
||||
* 1.00a drg 01/19/10 First release
|
||||
* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
|
||||
* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
|
||||
* added to enable or disable interrupts based on
|
||||
* Distributor Register base address. Normally users use
|
||||
* XScuGic instance and call XScuGic_Enable or
|
||||
* XScuGic_Disable to enable/disable interrupts. These
|
||||
* new macros are provided when user does not want to
|
||||
* use an instance pointer but still wants to enable or
|
||||
* disable interrupts.
|
||||
* Function prototypes for functions (present in newly
|
||||
* added file xscugic_hw.c) are added.
|
||||
* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
|
||||
* 702687).
|
||||
* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
|
||||
* XScuGic_SetPriTrigTypeByDistAddr and
|
||||
* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
|
||||
* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
|
||||
* Zynq Ultrascale Mp
|
||||
* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
|
||||
#define XSCUGIC_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_exception.h"
|
||||
#include "xil_io.h"
|
||||
#include "xil_types.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*
|
||||
* The maximum number of interrupts supported by the hardware.
|
||||
*/
|
||||
#ifdef __ARM_NEON__
|
||||
#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
|
||||
#else
|
||||
#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The maximum priority value that can be used in the GIC.
|
||||
*/
|
||||
#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
|
||||
#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
|
||||
|
||||
/** @name Distributor Interface Register Map
|
||||
*
|
||||
* Define the offsets from the base address for all Distributor registers of
|
||||
* the interrupt controller, some registers may be reserved in the hardware
|
||||
* device.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable \
|
||||
Register */
|
||||
#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller \
|
||||
Type Register */
|
||||
#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID \
|
||||
Register */
|
||||
#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security \
|
||||
Register */
|
||||
#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set \
|
||||
Register */
|
||||
#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
|
||||
#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set \
|
||||
Register */
|
||||
#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear \
|
||||
Register */
|
||||
#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
|
||||
#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
|
||||
#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target \
|
||||
Register 0x800-0x8FB */
|
||||
#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration \
|
||||
Register 0xC00-0xCFC */
|
||||
#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
|
||||
#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register \
|
||||
0xd04-0xd7C */
|
||||
#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration \
|
||||
Register */
|
||||
#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered \
|
||||
Interrupt Register */
|
||||
#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
|
||||
#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
|
||||
/* @} */
|
||||
|
||||
/** @name Distributor Enable Register
|
||||
* Controls if the distributor response to external interrupt inputs.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Controller Type Register
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable \
|
||||
Shared Peripheral \
|
||||
Interrupts*/
|
||||
#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
|
||||
#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
|
||||
#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
|
||||
/* @} */
|
||||
|
||||
/** @name Implementor ID Register
|
||||
* Implementor and revision information.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
|
||||
#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Security Registers
|
||||
* Each bit controls the security level of an interrupt, either secure or non
|
||||
* secure. These registers can only be accessed using secure read and write.
|
||||
* There are registers for each of the CPU interfaces at offset 0x080. A
|
||||
* register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 32 of these registers staring at location 0x084.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an \
|
||||
INT_ID */
|
||||
/* @} */
|
||||
|
||||
/** @name Enable Set Register
|
||||
* Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
|
||||
* enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
|
||||
* bit to 0.
|
||||
* There are registers for each of the CPU interfaces at offset 0x100. With up
|
||||
* to 8 registers aliased to the same address. A register set for the SPI
|
||||
* interrupts is available to all CPU interfaces.
|
||||
* There are up to 32 of these registers staring at location 0x104.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an \
|
||||
INT_ID */
|
||||
/* @} */
|
||||
|
||||
/** @name Enable Clear Register
|
||||
* Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
|
||||
* enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
|
||||
* sets the corresponding bit to 0.
|
||||
* There are registers for each of the CPU interfaces at offset 0x180. With up
|
||||
* to 8 registers aliased to the same address.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 32 of these registers staring at location 0x184.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an \
|
||||
INT_ID */
|
||||
/* @} */
|
||||
|
||||
/** @name Pending Set Register
|
||||
* Each bit controls the Pending or Active and Pending state of an interrupt, a
|
||||
* 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
|
||||
* an interrupt to the pending state.
|
||||
* There are registers for each of the CPU interfaces at offset 0x200. With up
|
||||
* to 8 registers aliased to the same address.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 32 of these registers staring at location 0x204.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an \
|
||||
INT_ID */
|
||||
/* @} */
|
||||
|
||||
/** @name Pending Clear Register
|
||||
* Each bit can clear the Pending or Active and Pending state of an interrupt, a
|
||||
* 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
|
||||
* clears the pending state of an interrupt.
|
||||
* There are registers for each of the CPU interfaces at offset 0x280. With up
|
||||
* to 8 registers aliased to the same address.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 32 of these registers staring at location 0x284.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an \
|
||||
INT_ID */
|
||||
/* @} */
|
||||
|
||||
/** @name Active Status Register
|
||||
* Each bit provides the Active status of an interrupt, a
|
||||
* 0 is not Active, a 1 is Active. This is a read only register.
|
||||
* There are registers for each of the CPU interfaces at offset 0x300. With up
|
||||
* to 8 registers aliased to each address.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 32 of these registers staring at location 0x380.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an \
|
||||
INT_ID */
|
||||
/* @} */
|
||||
|
||||
/** @name Priority Level Register
|
||||
* Each byte in a Priority Level Register sets the priority level of an
|
||||
* interrupt. Reading the register provides the priority level of an interrupt.
|
||||
* There are registers for each of the CPU interfaces at offset 0x400 through
|
||||
* 0x41C. With up to 8 registers aliased to each address.
|
||||
* 0 is highest priority, 0xFF is lowest.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 255 of these registers staring at location 0x420.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an \
|
||||
INT_ID */
|
||||
#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority \
|
||||
actually the lowest priority*/
|
||||
/* @} */
|
||||
|
||||
/** @name SPI Target Register 0x800-0x8FB
|
||||
* Each byte references a separate SPI and programs which of the up to 8 CPU
|
||||
* interfaces are sent a Pending interrupt.
|
||||
* There are registers for each of the CPU interfaces at offset 0x800 through
|
||||
* 0x81C. With up to 8 registers aliased to each address.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 255 of these registers staring at location 0x820.
|
||||
*
|
||||
* This driver does not support multiple CPU interfaces. These are included
|
||||
* for complete documentation.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
|
||||
#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
|
||||
#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
|
||||
#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
|
||||
#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
|
||||
#define XSCUGIC_SPI_CPU2_MASK 0x00000003U /**< CPU 2 Mask*/
|
||||
#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
|
||||
#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Configuration Register 0xC00-0xCFC
|
||||
* The interrupt configuration registers program an SFI to be active HIGH level
|
||||
* sensitive or rising edge sensitive.
|
||||
* Each bit pair describes the configuration for an INT_ID.
|
||||
* SFI Read Only b10 always
|
||||
* PPI Read Only depending on how the PPIs are configured.
|
||||
* b01 Active HIGH level sensitive
|
||||
* b11 Rising edge sensitive
|
||||
* SPI LSB is read only.
|
||||
* b01 Active HIGH level sensitive
|
||||
* b11 Rising edge sensitive/
|
||||
* There are registers for each of the CPU interfaces at offset 0xC00 through
|
||||
* 0xC04. With up to 8 registers aliased to each address.
|
||||
* A register set for the SPI interrupts is available to all CPU interfaces.
|
||||
* There are up to 255 of these registers staring at location 0xC08.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
|
||||
/* @} */
|
||||
|
||||
/** @name PPI Status Register
|
||||
* Enables an external AMBA master to access the status of the PPI inputs.
|
||||
* A CPU can only read the status of its local PPI signals and cannot read the
|
||||
* status for other CPUs.
|
||||
* This register is aliased for each CPU interface.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
|
||||
#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
|
||||
/* @} */
|
||||
|
||||
/** @name SPI Status Register 0xd04-0xd7C
|
||||
* Enables an external AMBA master to access the status of the SPI inputs.
|
||||
* There are up to 63 registers if the maximum number of SPI inputs are
|
||||
* configured.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI \
|
||||
input */
|
||||
/* @} */
|
||||
|
||||
/** @name AHB Configuration Register
|
||||
* Provides the status of the CFGBIGEND input signal and allows the endianess
|
||||
* of the GIC to be set.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, \
|
||||
1-GIC uses Big Endian */
|
||||
#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, \
|
||||
1-use the AHB_END bit */
|
||||
#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
|
||||
|
||||
/* @} */
|
||||
|
||||
/** @name Software Triggered Interrupt Register
|
||||
* Controls issueing of software interrupts.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
|
||||
#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter \
|
||||
b00-Use the target List \
|
||||
b01-All CPUs except requester \
|
||||
b10-To Requester \
|
||||
b11-reserved */
|
||||
#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
|
||||
#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
|
||||
#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID \
|
||||
signaled to the CPU*/
|
||||
/* @} */
|
||||
|
||||
/** @name CPU Interface Register Map
|
||||
*
|
||||
* Define the offsets from the base address for all CPU registers of the
|
||||
* interrupt controller, some registers may be reserved in the hardware device.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control \
|
||||
Register */
|
||||
#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
|
||||
#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
|
||||
#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
|
||||
#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
|
||||
#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
|
||||
#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt \
|
||||
Register */
|
||||
#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure \
|
||||
Binary Point Register */
|
||||
|
||||
/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
|
||||
* to. */
|
||||
/* @} */
|
||||
|
||||
/** @name Control Register
|
||||
* CPU Interface Control register definitions
|
||||
* All bits are defined here although some are not available in the non-secure
|
||||
* mode.
|
||||
* @{
|
||||
*/
|
||||
#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, \
|
||||
0=separate registers, \
|
||||
1=both use bin_pt_s */
|
||||
#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure \
|
||||
interrupts, \
|
||||
0= use IRQ for both, \
|
||||
1=Use FIQ for secure, IRQ for non*/
|
||||
#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
|
||||
#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
|
||||
#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
|
||||
/* @} */
|
||||
|
||||
/** @name Priority Mask Register
|
||||
* Priority Mask register definitions
|
||||
* The CPU interface does not send interrupt if the level of the interrupt is
|
||||
* lower than the level of the register.
|
||||
* @{
|
||||
*/
|
||||
/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
|
||||
/* @} */
|
||||
|
||||
/** @name Binary Point Register
|
||||
* Binary Point register definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value \
|
||||
Value Secure Non-secure \
|
||||
b000 0xFE 0xFF \
|
||||
b001 0xFC 0xFE \
|
||||
b010 0xF8 0xFC \
|
||||
b011 0xF0 0xF8 \
|
||||
b100 0xE0 0xF0 \
|
||||
b101 0xC0 0xE0 \
|
||||
b110 0x80 0xC0 \
|
||||
b111 0x00 0x80 \
|
||||
*/
|
||||
/*@}*/
|
||||
|
||||
/** @name Interrupt Acknowledge Register
|
||||
* Interrupt Acknowledge register definitions
|
||||
* Identifies the current Pending interrupt, and the CPU ID for software
|
||||
* interrupts.
|
||||
*/
|
||||
#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
|
||||
#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
|
||||
/* @} */
|
||||
|
||||
/** @name End of Interrupt Register
|
||||
* End of Interrupt register definitions
|
||||
* Allows the CPU to signal the GIC when it completes an interrupt service
|
||||
* routine.
|
||||
*/
|
||||
#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
|
||||
|
||||
/* @} */
|
||||
|
||||
/** @name Running Priority Register
|
||||
* Running Priority register definitions
|
||||
* Identifies the interrupt priority level of the highest priority active
|
||||
* interrupt.
|
||||
*/
|
||||
#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
|
||||
/* @} */
|
||||
|
||||
/*
|
||||
* Highest Pending Interrupt register definitions
|
||||
* Identifies the interrupt priority of the highest priority pending interupt
|
||||
*/
|
||||
#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
|
||||
/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
|
||||
/* @} */
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the Interrupt Configuration Register offset for an interrupt id.
|
||||
*
|
||||
* @param InterruptID is the interrupt number.
|
||||
*
|
||||
* @return The 32-bit value of the offset
|
||||
*
|
||||
* @note
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
|
||||
((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID) / 16U) * 4U))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the Interrupt Priority Register offset for an interrupt id.
|
||||
*
|
||||
* @param InterruptID is the interrupt number.
|
||||
*
|
||||
* @return The 32-bit value of the offset
|
||||
*
|
||||
* @note
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
|
||||
((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID) / 4U) * 4U))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the SPI Target Register offset for an interrupt id.
|
||||
*
|
||||
* @param InterruptID is the interrupt number.
|
||||
*
|
||||
* @return The 32-bit value of the offset
|
||||
*
|
||||
* @note
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
|
||||
((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID) / 4U) * 4U))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the Interrupt Clear-Enable Register offset for an interrupt ID
|
||||
*
|
||||
* @param Register is the register offset for the clear/enable bank.
|
||||
* @param InterruptID is the interrupt number.
|
||||
*
|
||||
* @return The 32-bit value of the offset
|
||||
*
|
||||
* @note
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
|
||||
((Register) + (((InterruptID) / 32U) * 4U))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Read the given Intc register.
|
||||
*
|
||||
* @param BaseAddress is the base address of the device.
|
||||
* @param RegOffset is the register offset to be read
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_ReadReg(BaseAddress, RegOffset) \
|
||||
(Xil_In32((BaseAddress) + (RegOffset)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Write the given Intc register.
|
||||
*
|
||||
* @param BaseAddress is the base address of the device.
|
||||
* @param RegOffset is the register offset to be written
|
||||
* @param Data is the 32-bit value to write to the register
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
|
||||
(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enable specific interrupt(s) in the interrupt controller.
|
||||
*
|
||||
* @param DistBaseAddress is the Distributor Register base address of the
|
||||
* device
|
||||
* @param Int_Id is the ID of the interrupt source and should be in the
|
||||
* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
|
||||
XScuGic_WriteReg((DistBaseAddress), \
|
||||
XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
|
||||
(0x00000001U << ((Int_Id) % 32U)))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Disable specific interrupt(s) in the interrupt controller.
|
||||
*
|
||||
* @param DistBaseAddress is the Distributor Register base address of the
|
||||
* device
|
||||
* @param Int_Id is the ID of the interrupt source and should be in the
|
||||
* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
|
||||
*
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-style signature:
|
||||
* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
|
||||
XScuGic_WriteReg((DistBaseAddress), \
|
||||
XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
|
||||
(0x00000001U << ((Int_Id) % 32U)))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XScuGic_DeviceInterruptHandler(void* DeviceId);
|
||||
s32 XScuGic_DeviceInitialize(u32 DeviceId);
|
||||
void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
|
||||
Xil_InterruptHandler Handler, void* CallBackRef);
|
||||
void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
||||
u8 Priority, u8 Trigger);
|
||||
void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
|
||||
u8* Priority, u8* Trigger);
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscugic_intr.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @{
|
||||
*
|
||||
* This file contains the interrupt processing for the driver for the Xilinx
|
||||
* Interrupt Controller. The interrupt processing is partitioned separately such
|
||||
* that users are not required to use the provided interrupt processing. This
|
||||
* file requires other files of the driver to be linked in also.
|
||||
*
|
||||
* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
|
||||
* is an instance pointer to an interrupt controller driver such that multiple
|
||||
* interrupt controllers can be supported. This handler requires the calling
|
||||
* function to pass it the appropriate argument, so another level of indirection
|
||||
* may be required.
|
||||
*
|
||||
* The interrupt processing may be used by connecting the interrupt handler to
|
||||
* the interrupt system. The handler does not save and restore the processor
|
||||
* context but only handles the processing of the Interrupt Controller. The user
|
||||
* is encouraged to supply their own interrupt handler when performance tuning is
|
||||
* deemed necessary.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------------
|
||||
* 1.00a drg 01/19/10 First release
|
||||
* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
|
||||
* since the HandlerTable has now moved to XScuGic_Config.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* @internal
|
||||
*
|
||||
* This driver assumes that the context of the processor has been saved prior to
|
||||
* the calling of the Interrupt Controller interrupt handler and then restored
|
||||
* after the handler returns. This requires either the running RTOS to save the
|
||||
* state of the machine or that a wrapper be used as the destination of the
|
||||
* interrupt vector to save the state of the processor and restore the state
|
||||
* after the interrupt handler returns.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_assert.h"
|
||||
#include "xil_types.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function is the primary interrupt handler for the driver. It must be
|
||||
* connected to the interrupt source such that it is called when an interrupt of
|
||||
* the interrupt controller is active. It will resolve which interrupts are
|
||||
* active and enabled and call the appropriate interrupt handler. It uses
|
||||
* the Interrupt Type information to determine when to acknowledge the interrupt.
|
||||
* Highest priority interrupts are serviced first.
|
||||
*
|
||||
* This function assumes that an interrupt vector table has been previously
|
||||
* initialized. It does not verify that entries in the table are valid before
|
||||
* calling an interrupt handler.
|
||||
*
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XScuGic instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XScuGic_InterruptHandler(XScuGic* InstancePtr)
|
||||
{
|
||||
|
||||
u32 InterruptID;
|
||||
u32 IntIDFull;
|
||||
XScuGic_VectorTableEntry* TablePtr;
|
||||
|
||||
/* Assert that the pointer to the instance is valid
|
||||
*/
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
/*
|
||||
* Read the int_ack register to identify the highest priority interrupt ID
|
||||
* and make sure it is valid. Reading Int_Ack will clear the interrupt
|
||||
* in the GIC.
|
||||
*/
|
||||
IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
|
||||
InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
|
||||
|
||||
if (XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID) {
|
||||
goto IntrExit;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interrupt is shared, do some locking here if there are multiple
|
||||
* processors.
|
||||
*/
|
||||
/*
|
||||
* If pre-eption is required:
|
||||
* Re-enable pre-emption by setting the CPSR I bit for non-secure ,
|
||||
* interrupts or the F bit for secure interrupts
|
||||
*/
|
||||
|
||||
/*
|
||||
* If we need to change security domains, issue a SMC instruction here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Execute the ISR. Jump into the Interrupt service routine based on the
|
||||
* IRQSource. A software trigger is cleared by the ACK.
|
||||
*/
|
||||
TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
|
||||
if (TablePtr != NULL) {
|
||||
TablePtr->Handler(TablePtr->CallBackRef);
|
||||
}
|
||||
|
||||
IntrExit:
|
||||
/*
|
||||
* Write to the EOI register, we are all done here.
|
||||
* Let this function return, the boot code will restore the stack.
|
||||
*/
|
||||
XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
|
||||
|
||||
/*
|
||||
* Return from the interrupt. Change security domains could happen here.
|
||||
*/
|
||||
}
|
||||
/** @} */
|
||||
103
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_sinit.c
Executable file
103
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_sinit.c
Executable file
|
|
@ -0,0 +1,103 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xscugic_sinit.c
|
||||
* @addtogroup scugic_v3_1
|
||||
* @{
|
||||
*
|
||||
* Contains static init functions for the XScuGic driver for the Interrupt
|
||||
* Controller. See xscugic.h for a detailed description of the driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- --------------------------------------------------------
|
||||
* 1.00a drg 01/19/10 First release
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xparameters.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Looks up the device configuration based on the unique device ID. A table
|
||||
* contains the configuration info for each device in the system.
|
||||
*
|
||||
* @param DeviceId is the unique identifier for a device.
|
||||
*
|
||||
* @return A pointer to the XScuGic configuration structure for the
|
||||
* specified device, or NULL if the device was not found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XScuGic_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
|
||||
if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XScuGic_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (XScuGic_Config *)CfgPtr;
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,430 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xstatus.h
|
||||
*
|
||||
* This file contains Xilinx software status codes. Status codes have their
|
||||
* own data type called int. These codes are used throughout the Xilinx
|
||||
* device drivers.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XSTATUS_H /* prevent circular inclusions */
|
||||
#define XSTATUS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*********************** Common statuses 0 - 500 *****************************/
|
||||
// clang-format off
|
||||
#define XST_SUCCESS 0L
|
||||
#define XST_FAILURE 1L
|
||||
#define XST_DEVICE_NOT_FOUND 2L
|
||||
#define XST_DEVICE_BLOCK_NOT_FOUND 3L
|
||||
#define XST_INVALID_VERSION 4L
|
||||
#define XST_DEVICE_IS_STARTED 5L
|
||||
#define XST_DEVICE_IS_STOPPED 6L
|
||||
#define XST_FIFO_ERROR 7L /* an error occurred during an
|
||||
operation with a FIFO such as
|
||||
an underrun or overrun, this
|
||||
error requires the device to
|
||||
be reset */
|
||||
#define XST_RESET_ERROR 8L /* an error occurred which requires
|
||||
the device to be reset */
|
||||
#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
|
||||
typically requires the device
|
||||
using the DMA to be reset */
|
||||
#define XST_NOT_POLLED 10L /* the device is not configured for
|
||||
polled mode operation */
|
||||
#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
|
||||
the specified data into */
|
||||
#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
|
||||
to hold the expected data */
|
||||
#define XST_NO_DATA 13L /* there was no data available */
|
||||
#define XST_REGISTER_ERROR 14L /* a register did not contain the
|
||||
expected value */
|
||||
#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
|
||||
into the function */
|
||||
#define XST_NOT_SGDMA 16L /* the device is not configured for
|
||||
scatter-gather DMA operation */
|
||||
#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
|
||||
#define XST_NO_CALLBACK 18L /* a callback has not yet been
|
||||
registered */
|
||||
#define XST_NO_FEATURE 19L /* device is not configured with
|
||||
the requested feature */
|
||||
#define XST_NOT_INTERRUPT 20L /* device is not configured for
|
||||
interrupt mode operation */
|
||||
#define XST_DEVICE_BUSY 21L /* device is busy */
|
||||
#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
|
||||
have maxed out */
|
||||
#define XST_IS_STARTED 23L /* used when part of device is
|
||||
already started i.e.
|
||||
sub channel */
|
||||
#define XST_IS_STOPPED 24L /* used when part of device is
|
||||
already stopped i.e.
|
||||
sub channel */
|
||||
#define XST_DATA_LOST 26L /* driver defined error */
|
||||
#define XST_RECV_ERROR 27L /* generic receive error */
|
||||
#define XST_SEND_ERROR 28L /* generic transmit error */
|
||||
#define XST_NOT_ENABLED 29L /* a requested service is not
|
||||
available because it has not
|
||||
been enabled */
|
||||
|
||||
/***************** Utility Component statuses 401 - 500 *********************/
|
||||
|
||||
#define XST_MEMTEST_FAILED 401L /* memory test failed */
|
||||
|
||||
|
||||
/***************** Common Components statuses 501 - 1000 *********************/
|
||||
|
||||
/********************* Packet Fifo statuses 501 - 510 ************************/
|
||||
|
||||
#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
|
||||
#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
|
||||
#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
|
||||
was invalid after reset */
|
||||
#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
|
||||
#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
|
||||
* empty and full simultaneously
|
||||
*/
|
||||
|
||||
/************************** DMA statuses 511 - 530 ***************************/
|
||||
|
||||
#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
|
||||
failed */
|
||||
#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
|
||||
was invalid after reset */
|
||||
#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
|
||||
no buffer descriptors ready
|
||||
to be processed */
|
||||
#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
|
||||
#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
|
||||
#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
|
||||
the scatter gather list are
|
||||
being used */
|
||||
#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
|
||||
descriptor which is to be
|
||||
copied over in the scatter
|
||||
list is locked */
|
||||
#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
|
||||
put into the scatter gather
|
||||
list to be commited */
|
||||
#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
|
||||
specified was larger than the
|
||||
total # of buffer descriptors
|
||||
in the scatter gather list */
|
||||
#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
|
||||
already been created */
|
||||
#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
|
||||
been created */
|
||||
#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
|
||||
being started was not committed
|
||||
to the list */
|
||||
#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
|
||||
has already been used by the
|
||||
hardware so it can't be reused
|
||||
*/
|
||||
#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
|
||||
error */
|
||||
#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
|
||||
error */
|
||||
|
||||
/************************** IPIF statuses 531 - 550 ***************************/
|
||||
|
||||
#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
|
||||
was passed into the function */
|
||||
#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
|
||||
reset was not valid */
|
||||
#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
|
||||
status register did not read
|
||||
back correctly */
|
||||
#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
|
||||
register did not reset when
|
||||
acked */
|
||||
#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
|
||||
register was not updated when
|
||||
other registers changed */
|
||||
#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
|
||||
status register did not read
|
||||
back correctly */
|
||||
#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
|
||||
did not reset when acked */
|
||||
#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
|
||||
not updated correctly when other
|
||||
registers changed */
|
||||
#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
|
||||
register did not indicate the
|
||||
expected value */
|
||||
#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
|
||||
did not indicate the expected
|
||||
value */
|
||||
#define XST_IPIF_ERROR 541L /* generic ipif error */
|
||||
|
||||
/****************** Device specific statuses 1001 - 4095 *********************/
|
||||
|
||||
/********************* Ethernet statuses 1001 - 1050 *************************/
|
||||
|
||||
#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
|
||||
* to hold the minimum number of
|
||||
* buffers or descriptors */
|
||||
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
|
||||
#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
|
||||
#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
|
||||
#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
|
||||
#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
|
||||
#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
|
||||
* collision on polled send */
|
||||
|
||||
/*********************** UART statuses 1051 - 1075 ***************************/
|
||||
#define XST_UART
|
||||
|
||||
#define XST_UART_INIT_ERROR 1051L
|
||||
#define XST_UART_START_ERROR 1052L
|
||||
#define XST_UART_CONFIG_ERROR 1053L
|
||||
#define XST_UART_TEST_FAIL 1054L
|
||||
#define XST_UART_BAUD_ERROR 1055L
|
||||
#define XST_UART_BAUD_RANGE 1056L
|
||||
|
||||
|
||||
/************************ IIC statuses 1076 - 1100 ***************************/
|
||||
|
||||
#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
|
||||
#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
|
||||
#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
|
||||
/* general call address */
|
||||
#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
|
||||
/* value after reset not valid */
|
||||
#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
|
||||
/* didn't return value written */
|
||||
#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
|
||||
/* didn't return written value */
|
||||
#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
|
||||
|
||||
/*********************** ATMC statuses 1101 - 1125 ***************************/
|
||||
|
||||
#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
|
||||
controller hit the max value
|
||||
which requires the statistics
|
||||
to be cleared */
|
||||
|
||||
/*********************** Flash statuses 1126 - 1150 **************************/
|
||||
|
||||
#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
|
||||
*/
|
||||
#define XST_FLASH_READY 1127L /* Flash is ready for commands */
|
||||
#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
|
||||
error. Use XFlash_DeviceControl
|
||||
to retrieve device specific codes
|
||||
*/
|
||||
#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
|
||||
*/
|
||||
#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
|
||||
*/
|
||||
#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
|
||||
driver */
|
||||
#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
|
||||
#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
|
||||
#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
|
||||
aborted due to a timeout */
|
||||
#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
|
||||
addressible range */
|
||||
#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
|
||||
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
|
||||
write/erase function with
|
||||
XFL_NON_BLOCKING_WRITE/ERASE
|
||||
option cleared */
|
||||
#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
|
||||
|
||||
/*********************** SPI statuses 1151 - 1175 ****************************/
|
||||
|
||||
#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
|
||||
#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
|
||||
#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
|
||||
#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
|
||||
#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
|
||||
#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
|
||||
* selected */
|
||||
#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
|
||||
#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
|
||||
*/
|
||||
#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
|
||||
#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
|
||||
#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
|
||||
|
||||
#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
|
||||
|
||||
/********************** OPB Arbiter statuses 1176 - 1200 *********************/
|
||||
|
||||
#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
|
||||
* one master assigned to two or more
|
||||
* priorities, or one master not
|
||||
* assigned to any priority
|
||||
*/
|
||||
#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
|
||||
* priority levels without first
|
||||
* suspending the use of priority
|
||||
* levels
|
||||
*/
|
||||
#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
|
||||
* bus parking was not enabled
|
||||
*/
|
||||
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
|
||||
* priority mode to allow the
|
||||
* priorities to be changed
|
||||
*/
|
||||
|
||||
/************************ Intc statuses 1201 - 1225 **************************/
|
||||
|
||||
#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
|
||||
#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
|
||||
|
||||
/********************** TmrCtr statuses 1226 - 1250 **************************/
|
||||
|
||||
#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
|
||||
|
||||
/********************** WdtTb statuses 1251 - 1275 ***************************/
|
||||
|
||||
#define XST_WDTTB_TIMER_FAILED 1251L
|
||||
|
||||
/********************** PlbArb statuses 1276 - 1300 **************************/
|
||||
|
||||
#define XST_PLBARB_FAIL_SELFTEST 1276L
|
||||
|
||||
/********************** Plb2Opb statuses 1301 - 1325 *************************/
|
||||
|
||||
#define XST_PLB2OPB_FAIL_SELFTEST 1301L
|
||||
|
||||
/********************** Opb2Plb statuses 1326 - 1350 *************************/
|
||||
|
||||
#define XST_OPB2PLB_FAIL_SELFTEST 1326L
|
||||
|
||||
/********************** SysAce statuses 1351 - 1360 **************************/
|
||||
|
||||
#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
|
||||
|
||||
/********************** PCI Bridge statuses 1361 - 1375 **********************/
|
||||
|
||||
#define XST_PCI_INVALID_ADDRESS 1361L
|
||||
|
||||
/********************** FlexRay constants 1400 - 1409 *************************/
|
||||
|
||||
#define XST_FR_TX_ERROR 1400
|
||||
#define XST_FR_TX_BUSY 1401
|
||||
#define XST_FR_BUF_LOCKED 1402
|
||||
#define XST_FR_NO_BUF 1403
|
||||
|
||||
/****************** USB constants 1410 - 1420 *******************************/
|
||||
|
||||
#define XST_USB_ALREADY_CONFIGURED 1410
|
||||
#define XST_USB_BUF_ALIGN_ERROR 1411
|
||||
#define XST_USB_NO_DESC_AVAILABLE 1412
|
||||
#define XST_USB_BUF_TOO_BIG 1413
|
||||
#define XST_USB_NO_BUF 1414
|
||||
|
||||
/****************** HWICAP constants 1421 - 1429 *****************************/
|
||||
|
||||
#define XST_HWICAP_WRITE_DONE 1421
|
||||
|
||||
|
||||
/****************** AXI VDMA constants 1430 - 1440 *****************************/
|
||||
|
||||
#define XST_VDMA_MISMATCH_ERROR 1430
|
||||
|
||||
/*********************** NAND Flash statuses 1441 - 1459 *********************/
|
||||
|
||||
#define XST_NAND_BUSY 1441L /* Flash is erasing or
|
||||
* programming
|
||||
*/
|
||||
#define XST_NAND_READY 1442L /* Flash is ready for commands
|
||||
*/
|
||||
#define XST_NAND_ERROR 1443L /* Flash had detected an
|
||||
* internal error.
|
||||
*/
|
||||
#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
|
||||
* driver
|
||||
*/
|
||||
#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
|
||||
*/
|
||||
#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
|
||||
* operation aborted due to a
|
||||
* timeout
|
||||
*/
|
||||
#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
|
||||
* addressible range
|
||||
*/
|
||||
#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
|
||||
*/
|
||||
#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
|
||||
* page of the device
|
||||
*/
|
||||
#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
|
||||
*/
|
||||
|
||||
#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
|
||||
*/
|
||||
|
||||
// clang-format on
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef s32 XStatus;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
|
|
@ -213,7 +213,7 @@ static int _is_interruptable(void)
|
|||
return !(val & DIS_INT);
|
||||
}
|
||||
|
||||
static struct XiziTrapDriver xizi_trap_driver = (struct XiziTrapDriver) {
|
||||
static struct XiziTrapDriver xizi_trap_driver = {
|
||||
.sys_irq_init = _sys_irq_init,
|
||||
|
||||
.cpu_irq_enable = _cpu_irq_enable,
|
||||
|
|
@ -235,6 +235,6 @@ static struct XiziTrapDriver xizi_trap_driver = (struct XiziTrapDriver) {
|
|||
struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag)
|
||||
{
|
||||
xizi_trap_driver.sys_irq_init();
|
||||
xizi_trap_driver.cpu_irq_enable();
|
||||
xizi_trap_driver.cpu_irq_disable();
|
||||
return &xizi_trap_driver;
|
||||
}
|
||||
|
|
@ -246,9 +246,9 @@ init_stack:
|
|||
bic r2, r2, #ARM_CPSR_MODE_MASK
|
||||
orr r2, r2, r0
|
||||
msr cpsr_cxsf, r2
|
||||
|
||||
# switch back to the SVC mode
|
||||
mov sp, r1
|
||||
|
||||
@ # switch back to the SVC mode
|
||||
bic r2, r2, #ARM_CPSR_MODE_MASK
|
||||
orr r2, r2, #ARM_MODE_SVC
|
||||
msr cpsr_cxsf, r2
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
/**
|
||||
* @file irq_numbers.c
|
||||
* @brief irq numbers
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2024.03.04
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: irq_numbers.c
|
||||
Description: irq numbers
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2024-03-04
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. Add HW_NR_IRQS
|
||||
*************************************************/
|
||||
#pragma once
|
||||
|
||||
#include "xparameters_ps.h"
|
||||
#include "xscugic_hw.h"
|
||||
|
||||
#define HW_NR_IRQS XSCUGIC_MAX_NUM_INTR_INPUTS
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
/**
|
||||
* @file trap_common.c
|
||||
* @brief trap interface of hardkernel
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.08.25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: trap_common.c
|
||||
Description: trap interface of hardkernel
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. first version
|
||||
*************************************************/
|
||||
#include <string.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "trap_common.h"
|
||||
#include "xparameters.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
#include "log.h"
|
||||
|
||||
extern void init_stack(uint32_t, uint32_t);
|
||||
extern void user_trap_swi_enter(void);
|
||||
extern void trap_iabort(void);
|
||||
extern void trap_dabort(void);
|
||||
extern void trap_irq_enter(void);
|
||||
extern void trap_undefined_instruction(void);
|
||||
|
||||
static struct XiziTrapDriver xizi_trap_driver;
|
||||
|
||||
void panic(char* s)
|
||||
{
|
||||
xizi_trap_driver.cpu_irq_disable();
|
||||
KPrintf("panic: %s\n", s);
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
/* stack for different mode*/
|
||||
static char mode_stack_pages[NR_CPU][NR_MODE_STACKS][MODE_STACK_SIZE];
|
||||
|
||||
extern uint32_t _vector_jumper;
|
||||
extern uint32_t _vector_start;
|
||||
extern uint32_t _vector_end;
|
||||
|
||||
static XScuGic IntcInstance; /* Instance of the Interrupt Controller */
|
||||
|
||||
void init_cpu_mode_stacks(int cpu_id)
|
||||
{
|
||||
uint32_t modes[] = { ARM_MODE_FIQ, ARM_MODE_IRQ, ARM_MODE_ABT, ARM_MODE_UND };
|
||||
// initialize the stacks for different mode
|
||||
for (int i = 0; i < sizeof(modes) / sizeof(uint32_t); i++) {
|
||||
memset(mode_stack_pages[cpu_id][i], 0, MODE_STACK_SIZE);
|
||||
init_stack(modes[i], (uint32_t)mode_stack_pages[cpu_id][i]);
|
||||
}
|
||||
}
|
||||
|
||||
void handle_reserved(void)
|
||||
{
|
||||
// unimplemented trap handler
|
||||
LOG("Unimplemented Reserved\n");
|
||||
panic("");
|
||||
}
|
||||
|
||||
void handle_fiq(void)
|
||||
{
|
||||
LOG("Unimplemented FIQ\n");
|
||||
panic("");
|
||||
}
|
||||
|
||||
static void _sys_irq_init()
|
||||
{
|
||||
/* load exception vectors */
|
||||
volatile uint32_t* vector_base = &_vector_start;
|
||||
|
||||
// Set Interrupt handler start address
|
||||
vector_base[1] = (uint32_t)trap_undefined_instruction; // Undefined Instruction
|
||||
vector_base[2] = (uint32_t)user_trap_swi_enter; // Software Interrupt
|
||||
vector_base[3] = (uint32_t)trap_iabort; // Prefetch Abort
|
||||
vector_base[4] = (uint32_t)trap_dabort; // Data Abort
|
||||
vector_base[5] = (uint32_t)handle_reserved; // Reserved
|
||||
vector_base[6] = (uint32_t)trap_irq_enter; // IRQ
|
||||
vector_base[7] = (uint32_t)handle_fiq; // FIQ
|
||||
|
||||
init_cpu_mode_stacks(0);
|
||||
|
||||
/* active hardware irq responser */
|
||||
XScuGic_Config* gic_config = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID);
|
||||
if (NULL == gic_config) {
|
||||
ERROR("Error while looking up gic config\n");
|
||||
return;
|
||||
}
|
||||
int gic_init_status = XScuGic_CfgInitialize(&IntcInstance, gic_config, gic_config->CpuBaseAddress);
|
||||
if (gic_init_status != XST_SUCCESS) {
|
||||
ERROR("Error initializing gic\n");
|
||||
return;
|
||||
}
|
||||
|
||||
xizi_trap_driver.switch_hw_irqtbl((uint32_t*)&_vector_jumper);
|
||||
}
|
||||
|
||||
static void _cpu_irq_enable(void)
|
||||
{
|
||||
// Xil_ExceptionEnable();
|
||||
arm_set_interrupt_state(true);
|
||||
}
|
||||
|
||||
static void _cpu_irq_disable(void)
|
||||
{
|
||||
// Xil_ExceptionDisable();
|
||||
arm_set_interrupt_state(false);
|
||||
}
|
||||
|
||||
static void _single_irq_enable(int irq, int cpu, int prio)
|
||||
{
|
||||
XScuGic_Enable(&IntcInstance, irq);
|
||||
}
|
||||
|
||||
static void _single_irq_disable(int irq, int cpu)
|
||||
{
|
||||
XScuGic_Disable(&IntcInstance, irq);
|
||||
}
|
||||
|
||||
#define VBAR
|
||||
static inline uint32_t* _switch_hw_irqtbl(uint32_t* new_tbl_base)
|
||||
{
|
||||
// get old irq table base addr
|
||||
uint32_t old_tbl_base = 0;
|
||||
_ARM_MRC(15, 0, old_tbl_base, 12, 0, 0);
|
||||
|
||||
// set new irq table base addr
|
||||
_ARM_MCR(15, 0, new_tbl_base, 12, 0, 0);
|
||||
|
||||
// set sctlr to use VBAR
|
||||
uint32_t sctlr = 0;
|
||||
_ARM_MRC(15, 0, sctlr, 1, 0, 0);
|
||||
sctlr &= ~(1 << 13);
|
||||
_ARM_MCR(15, 0, sctlr, 1, 0, 0);
|
||||
|
||||
return (uint32_t*)old_tbl_base;
|
||||
}
|
||||
|
||||
static void _bind_irq_handler(int irq, irq_handler_t handler)
|
||||
{
|
||||
xizi_trap_driver.sw_irqtbl[irq].handler = handler;
|
||||
}
|
||||
|
||||
static bool _send_sgi(uint32_t irq, uint32_t bitmask, enum SgiFilterType type)
|
||||
{
|
||||
if (bitmask > (1 << NR_CPU) - 1) {
|
||||
return false;
|
||||
}
|
||||
|
||||
int cpu_id = 0;
|
||||
while (bitmask != 0) {
|
||||
if ((bitmask & 0x1) != 0) {
|
||||
XScuGic_SoftwareIntr(&IntcInstance, irq, cpu_id);
|
||||
}
|
||||
cpu_id++;
|
||||
bitmask >>= 1;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static uint32_t _hw_before_irq()
|
||||
{
|
||||
|
||||
uint32_t IntIDFull = XScuGic_CPUReadReg(&IntcInstance, XSCUGIC_INT_ACK_OFFSET);
|
||||
return IntIDFull;
|
||||
}
|
||||
|
||||
static uint32_t _hw_cur_int_num(uint32_t int_info)
|
||||
{
|
||||
return int_info & XSCUGIC_ACK_INTID_MASK;
|
||||
}
|
||||
|
||||
static uint32_t _hw_cur_int_cpu(uint32_t int_info)
|
||||
{
|
||||
return (int_info >> 5) & 0x3;
|
||||
}
|
||||
|
||||
static void _hw_after_irq(uint32_t int_info)
|
||||
{
|
||||
XScuGic_CPUWriteReg(&IntcInstance, XSCUGIC_EOI_OFFSET, int_info);
|
||||
}
|
||||
|
||||
static int _is_interruptable(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"mrs %0, cpsr"
|
||||
: "=r"(val)
|
||||
:
|
||||
:);
|
||||
|
||||
return !(val & DIS_INT);
|
||||
}
|
||||
|
||||
static struct XiziTrapDriver xizi_trap_driver = {
|
||||
.sys_irq_init = _sys_irq_init,
|
||||
|
||||
.cpu_irq_enable = _cpu_irq_enable,
|
||||
.cpu_irq_disable = _cpu_irq_disable,
|
||||
.single_irq_enable = _single_irq_enable,
|
||||
.single_irq_disable = _single_irq_disable,
|
||||
.switch_hw_irqtbl = _switch_hw_irqtbl,
|
||||
|
||||
.bind_irq_handler = _bind_irq_handler,
|
||||
.send_sgi = _send_sgi,
|
||||
|
||||
.is_interruptable = _is_interruptable,
|
||||
.hw_before_irq = _hw_before_irq,
|
||||
.hw_cur_int_num = _hw_cur_int_num,
|
||||
.hw_cur_int_cpu = _hw_cur_int_cpu,
|
||||
.hw_after_irq = _hw_after_irq,
|
||||
};
|
||||
|
||||
struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag)
|
||||
{
|
||||
xizi_trap_driver.sys_irq_init();
|
||||
xizi_trap_driver.cpu_irq_enable();
|
||||
return &xizi_trap_driver;
|
||||
}
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_assert.c
|
||||
*
|
||||
* This file contains basic assert related functions for Xilinx software IP.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a hbm 07/14/09 Initial release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_assert.h"
|
||||
#include "xil_types.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/**
|
||||
* This variable allows testing to be done easier with asserts. An assert
|
||||
* sets this variable such that a driver can evaluate this variable
|
||||
* to determine if an assert occurred.
|
||||
*/
|
||||
u32 Xil_AssertStatus;
|
||||
|
||||
/**
|
||||
* This variable allows the assert functionality to be changed for testing
|
||||
* such that it does not wait infinitely. Use the debugger to disable the
|
||||
* waiting during testing of asserts.
|
||||
*/
|
||||
/*s32 Xil_AssertWait = 1*/
|
||||
|
||||
/* The callback function to be invoked when an assert is taken */
|
||||
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Implement assert. Currently, it calls a user-defined callback function
|
||||
* if one has been set. Then, it potentially enters an infinite loop depending
|
||||
* on the value of the Xil_AssertWait variable.
|
||||
*
|
||||
* @param file is the name of the filename of the source
|
||||
* @param line is the linenumber within File
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Assert(const char8* File, s32 Line)
|
||||
{
|
||||
s32 Xil_AssertWait = 1;
|
||||
/* if the callback has been set then invoke it */
|
||||
if (Xil_AssertCallbackRoutine != 0) {
|
||||
(*Xil_AssertCallbackRoutine)(File, Line);
|
||||
}
|
||||
|
||||
/* if specified, wait indefinitely such that the assert will show up
|
||||
* in testing
|
||||
*/
|
||||
while (Xil_AssertWait != 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set up a callback function to be invoked when an assert occurs. If there
|
||||
* was already a callback installed, then it is replaced.
|
||||
*
|
||||
* @param routine is the callback to be invoked when an assert is taken
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note This function has no effect if NDEBUG is set
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_AssertSetCallback(Xil_AssertCallback Routine)
|
||||
{
|
||||
Xil_AssertCallbackRoutine = Routine;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Null handler function. This follows the XInterruptHandler signature for
|
||||
* interrupt handlers. It can be used to assign a null handler (a stub) to an
|
||||
* interrupt controller vector table.
|
||||
*
|
||||
* @param NullParameter is an arbitrary void pointer and not used.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XNullHandler(void* NullParameter)
|
||||
{
|
||||
}
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
SRC_DIR := src
|
||||
SRC_FILES := bootmmu.c mmu.c pagetable_attr.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +0,0 @@
|
|||
SRC_FILES := bootmmu.c mmu.c pagetable_attr.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file memlayout.h
|
||||
* @brief virtual memory and physical memory layout
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2024-01-25
|
||||
*/
|
||||
/*************************************************
|
||||
File name: memlayout.h
|
||||
Description: virtual memory and physical memory layout
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. first version
|
||||
*************************************************/
|
||||
#pragma once
|
||||
|
||||
// Memory layout
|
||||
// clang-format off
|
||||
|
||||
#define ARCH_BIT 32
|
||||
|
||||
/* A9 physical memory layout */
|
||||
#define PHY_MEM_BASE (0x00100000)
|
||||
#define PHY_USER_FREEMEM_BASE (0x20000000)
|
||||
#define PHY_USER_FREEMEM_TOP (0x3FF00000)
|
||||
#define PHY_MEM_STOP (0x3FF00000)
|
||||
|
||||
/* PTE-PAGE_SIZE */
|
||||
#define LEVEL4_PTE_SHIFT 12
|
||||
#define LEVEL4_PTE_SIZE (1 << LEVEL4_PTE_SHIFT)
|
||||
|
||||
/* PDE-SECTION_SIZE */
|
||||
#define LEVEL3_PDE_SHIFT 20
|
||||
#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT)
|
||||
|
||||
#define NUM_LEVEL3_PDE (1 << (ARCH_BIT - LEVEL3_PDE_SHIFT)) // how many PTE in a PT
|
||||
#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT
|
||||
#define NUM_TOPLEVEL_PDE NUM_LEVEL3_PDE
|
||||
|
||||
#define PAGE_SIZE LEVEL4_PTE_SIZE
|
||||
#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
|
||||
|
||||
/* User memory layout */
|
||||
#define USER_STACK_SIZE PAGE_SIZE
|
||||
#define USER_MEM_BASE (0x00000000)
|
||||
#define USER_MEM_TOP DEV_VRTMEM_BASE
|
||||
#define USER_IPC_SPACE_BASE (0x70000000)
|
||||
#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
|
||||
|
||||
/* Deivce memory layout */
|
||||
#define DEV_PHYMEM_BASE (0xE0000000)
|
||||
#define DEV_VRTMEM_BASE (0x80000000)
|
||||
#define DEV_MEM_SZ (0x1FFFFFFF)
|
||||
|
||||
/* Kernel memory layout */
|
||||
#define KERN_MEM_BASE (0xA0000000) // First kernel virtual address
|
||||
#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
|
||||
|
||||
// clang-format on
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
SRC_DIR := uart_io_for_imx6q_sabrelite
|
||||
SRC_DIR := uart_io_for_$(BOARD)
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -59,17 +59,17 @@ Modification:
|
|||
|
||||
static void UartInitGpio(void)
|
||||
{
|
||||
/* UART1 TXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
|
||||
/* UART1 TXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
|
||||
|
||||
/* UART1 RXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
|
||||
/* UART1 RXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
|
||||
|
||||
/* UART2 TXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
|
||||
/* UART2 TXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
|
||||
|
||||
/* UART2 RXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
|
||||
/* UART2 RXD */
|
||||
mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
|
||||
}
|
||||
|
||||
static uint32_t GetUartClk(void)
|
||||
|
|
@ -131,13 +131,13 @@ __attribute__((__always_inline__)) static inline uint8_t UartGetCharInstance(uin
|
|||
if (!(HW_UART_USR2(instance).B.RDR))
|
||||
return 0xFF;
|
||||
|
||||
read_data = HW_UART_URXD_RD(instance);
|
||||
read_data = HW_UART_URXD_RD(instance);
|
||||
|
||||
/* If error are detected */
|
||||
if (read_data & 0x7C00)
|
||||
return 0xFF;
|
||||
|
||||
return (uint8_t) read_data;
|
||||
return (uint8_t)read_data;
|
||||
}
|
||||
|
||||
__attribute__((__always_inline__)) static inline uint32_t UartGetIrqnumInstance(uint32_t instance)
|
||||
|
|
@ -177,7 +177,7 @@ static uint32_t UartGetIrqnum()
|
|||
}
|
||||
|
||||
/// @todo make this static
|
||||
static struct XiziSerialDriver hardkernel_serial_driver = (struct XiziSerialDriver) {
|
||||
static struct XiziSerialDriver hardkernel_serial_driver = {
|
||||
.sys_serial_init = UartInit,
|
||||
.get_serial_irqnum = UartGetIrqnum,
|
||||
.putc = UartPutChar,
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := xil_uart.c xil_io.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_io.h
|
||||
*
|
||||
* This file contains the interface for the general IO component, which
|
||||
* encapsulates the Input/Output functions for processors that do not
|
||||
* require any special I/O handling.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 1.00a ecm/sdm 10/24/09 First release
|
||||
* 1.00a sdm 07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
|
||||
* 3.07a asa 08/31/12 Added xil_printf.h include
|
||||
* 3.08a sgd 11/05/12 Reverted SYNC macros definitions
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_IO_H /* prevent circular inclusions */
|
||||
#define XIL_IO_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#if defined __GNUC__
|
||||
#define SYNCHRONIZE_IO dmb()
|
||||
#define INST_SYNC isb()
|
||||
#define DATA_SYNC dsb()
|
||||
#else
|
||||
#define SYNCHRONIZE_IO
|
||||
#define INST_SYNC
|
||||
#define DATA_SYNC
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform an big-endian input operation for a 16-bit memory location
|
||||
* by reading from the specified address and returning the Value read from
|
||||
* that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation at.
|
||||
*
|
||||
* @return The Value read from the specified input address with the
|
||||
* proper endianness. The return Value has the same endianness
|
||||
* as that of the processor, i.e. if the processor is
|
||||
* little-engian, the return Value is the byte-swapped Value read
|
||||
* from the address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_In16LE(Addr) Xil_In16((Addr))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a big-endian input operation for a 32-bit memory location
|
||||
* by reading from the specified address and returning the Value read from
|
||||
* that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation at.
|
||||
*
|
||||
* @return The Value read from the specified input address with the
|
||||
* proper endianness. The return Value has the same endianness
|
||||
* as that of the processor, i.e. if the processor is
|
||||
* little-engian, the return Value is the byte-swapped Value read
|
||||
* from the address.
|
||||
*
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_In32LE(Addr) Xil_In32((Addr))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a big-endian output operation for a 16-bit memory location
|
||||
* by writing the specified Value to the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
* The Value has the same endianness as that of the processor.
|
||||
* If the processor is little-endian, the byte-swapped Value is
|
||||
* written to the address.
|
||||
*
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a big-endian output operation for a 32-bit memory location
|
||||
* by writing the specified Value to the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
* The Value has the same endianness as that of the processor.
|
||||
* If the processor is little-endian, the byte-swapped Value is
|
||||
* written to the address.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 32-bit number from host byte order to network byte order.
|
||||
*
|
||||
* @param Data the 32-bit number to be converted.
|
||||
*
|
||||
* @return The converted 32-bit number in network byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 16-bit number from host byte order to network byte order.
|
||||
*
|
||||
* @param Data the 16-bit number to be converted.
|
||||
*
|
||||
* @return The converted 16-bit number in network byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Htons(Data) Xil_EndianSwap16((Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 32-bit number from network byte order to host byte order.
|
||||
*
|
||||
* @param Data the 32-bit number to be converted.
|
||||
*
|
||||
* @return The converted 32-bit number in host byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Convert a 16-bit number from network byte order to host byte order.
|
||||
*
|
||||
* @param Data the 16-bit number to be converted.
|
||||
*
|
||||
* @return The converted 16-bit number in host byte order.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/* The following functions allow the software to be transportable across
|
||||
* processors which may use memory mapped I/O or I/O which is mapped into a
|
||||
* seperate address space.
|
||||
*/
|
||||
u8 Xil_In8(INTPTR Addr);
|
||||
u16 Xil_In16(INTPTR Addr);
|
||||
u32 Xil_In32(INTPTR Addr);
|
||||
|
||||
void Xil_Out8(INTPTR Addr, u8 Value);
|
||||
void Xil_Out16(INTPTR Addr, u16 Value);
|
||||
void Xil_Out32(INTPTR Addr, u32 Value);
|
||||
|
||||
u16 Xil_In16BE(INTPTR Addr);
|
||||
u32 Xil_In32BE(INTPTR Addr);
|
||||
void Xil_Out16BE(INTPTR Addr, u16 Value);
|
||||
void Xil_Out32BE(INTPTR Addr, u32 Value);
|
||||
|
||||
u16 Xil_EndianSwap16(u16 Data);
|
||||
u32 Xil_EndianSwap32(u32 Data);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xpseudo_asm.h
|
||||
*
|
||||
* This header file contains macros for using inline assembler code.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a ecm 10/18/09 First release
|
||||
* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XPSEUDO_ASM_H
|
||||
#define XPSEUDO_ASM_H
|
||||
|
||||
#include "xreg_cortexa9.h"
|
||||
#ifdef __GNUC__
|
||||
#include "xpseudo_asm_gcc.h"
|
||||
#elif defined (__ICCARM__)
|
||||
#include "xpseudo_asm_iccarm.h"
|
||||
#else
|
||||
#include "xpseudo_asm_rvct.h"
|
||||
#endif
|
||||
|
||||
#endif /* XPSEUDO_ASM_H */
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xpseudo_asm_gcc.h
|
||||
*
|
||||
* This header file contains macros for using inline assembler code. It is
|
||||
* written specifically for the GNU compiler.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 1.00a ecm/sdm 10/28/09 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
|
||||
#define XPSEUDO_ASM_GCC_H /* by using protection macros */
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/* necessary for pre-processor */
|
||||
#define stringify(s) tostring(s)
|
||||
#define tostring(s) #s
|
||||
|
||||
/* pseudo assembler instructions */
|
||||
#define mfcpsr() ({u32 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"mrs %0, cpsr\n"\
|
||||
: "=r" (rval)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define mtcpsr(v) __asm__ __volatile__(\
|
||||
"msr cpsr,%0\n"\
|
||||
: : "r" (v)\
|
||||
)
|
||||
|
||||
#define cpsiei() __asm__ __volatile__("cpsie i\n")
|
||||
#define cpsidi() __asm__ __volatile__("cpsid i\n")
|
||||
|
||||
#define cpsief() __asm__ __volatile__("cpsie f\n")
|
||||
#define cpsidf() __asm__ __volatile__("cpsid f\n")
|
||||
|
||||
|
||||
|
||||
#define mtgpr(rn, v) __asm__ __volatile__(\
|
||||
"mov r" stringify(rn) ", %0 \n"\
|
||||
: : "r" (v)\
|
||||
)
|
||||
|
||||
#define mfgpr(rn) ({u32 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"mov %0,r" stringify(rn) "\n"\
|
||||
: "=r" (rval)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
/* memory synchronization operations */
|
||||
|
||||
/* Instruction Synchronization Barrier */
|
||||
#define isb() __asm__ __volatile__ ("isb" : : : "memory")
|
||||
|
||||
/* Data Synchronization Barrier */
|
||||
#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
|
||||
|
||||
/* Data Memory Barrier */
|
||||
#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
|
||||
|
||||
|
||||
/* Memory Operations */
|
||||
#define ldr(adr) ({u32 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"ldr %0,[%1]"\
|
||||
: "=r" (rval) : "r" (adr)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define ldrb(adr) ({u8 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"ldrb %0,[%1]"\
|
||||
: "=r" (rval) : "r" (adr)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
#define str(adr, val) __asm__ __volatile__(\
|
||||
"str %0,[%1]\n"\
|
||||
: : "r" (val), "r" (adr)\
|
||||
)
|
||||
|
||||
#define strb(adr, val) __asm__ __volatile__(\
|
||||
"strb %0,[%1]\n"\
|
||||
: : "r" (val), "r" (adr)\
|
||||
)
|
||||
|
||||
/* Count leading zeroes (clz) */
|
||||
#define clz(arg) ({u8 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"clz %0,%1"\
|
||||
: "=r" (rval) : "r" (arg)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
/* CP15 operations */
|
||||
#define mtcp(rn, v) __asm__ __volatile__(\
|
||||
"mcr " rn "\n"\
|
||||
: : "r" (v)\
|
||||
);
|
||||
|
||||
#define mfcp(rn) ({u32 rval; \
|
||||
__asm__ __volatile__(\
|
||||
"mrc " rn "\n"\
|
||||
: "=r" (rval)\
|
||||
);\
|
||||
rval;\
|
||||
})
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XPSEUDO_ASM_GCC_H */
|
||||
|
|
@ -0,0 +1,591 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xreg_cortexa9.h
|
||||
*
|
||||
* This header file contains definitions for using inline assembler code. It is
|
||||
* written specifically for the GNU, ARMCC compiler.
|
||||
*
|
||||
* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
|
||||
* with the positions of the bits within the registers.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 1.00a ecm/sdm 10/20/09 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XREG_CORTEXA9_H
|
||||
#define XREG_CORTEXA9_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* GPRs */
|
||||
#define XREG_GPR0 r0
|
||||
#define XREG_GPR1 r1
|
||||
#define XREG_GPR2 r2
|
||||
#define XREG_GPR3 r3
|
||||
#define XREG_GPR4 r4
|
||||
#define XREG_GPR5 r5
|
||||
#define XREG_GPR6 r6
|
||||
#define XREG_GPR7 r7
|
||||
#define XREG_GPR8 r8
|
||||
#define XREG_GPR9 r9
|
||||
#define XREG_GPR10 r10
|
||||
#define XREG_GPR11 r11
|
||||
#define XREG_GPR12 r12
|
||||
#define XREG_GPR13 r13
|
||||
#define XREG_GPR14 r14
|
||||
#define XREG_GPR15 r15
|
||||
#define XREG_CPSR cpsr
|
||||
|
||||
/* Coprocessor number defines */
|
||||
#define XREG_CP0 0
|
||||
#define XREG_CP1 1
|
||||
#define XREG_CP2 2
|
||||
#define XREG_CP3 3
|
||||
#define XREG_CP4 4
|
||||
#define XREG_CP5 5
|
||||
#define XREG_CP6 6
|
||||
#define XREG_CP7 7
|
||||
#define XREG_CP8 8
|
||||
#define XREG_CP9 9
|
||||
#define XREG_CP10 10
|
||||
#define XREG_CP11 11
|
||||
#define XREG_CP12 12
|
||||
#define XREG_CP13 13
|
||||
#define XREG_CP14 14
|
||||
#define XREG_CP15 15
|
||||
|
||||
/* Coprocessor control register defines */
|
||||
#define XREG_CR0 cr0
|
||||
#define XREG_CR1 cr1
|
||||
#define XREG_CR2 cr2
|
||||
#define XREG_CR3 cr3
|
||||
#define XREG_CR4 cr4
|
||||
#define XREG_CR5 cr5
|
||||
#define XREG_CR6 cr6
|
||||
#define XREG_CR7 cr7
|
||||
#define XREG_CR8 cr8
|
||||
#define XREG_CR9 cr9
|
||||
#define XREG_CR10 cr10
|
||||
#define XREG_CR11 cr11
|
||||
#define XREG_CR12 cr12
|
||||
#define XREG_CR13 cr13
|
||||
#define XREG_CR14 cr14
|
||||
#define XREG_CR15 cr15
|
||||
|
||||
/* Current Processor Status Register (CPSR) Bits */
|
||||
#define XREG_CPSR_THUMB_MODE 0x20
|
||||
#define XREG_CPSR_MODE_BITS 0x1F
|
||||
#define XREG_CPSR_SYSTEM_MODE 0x1F
|
||||
#define XREG_CPSR_UNDEFINED_MODE 0x1B
|
||||
#define XREG_CPSR_DATA_ABORT_MODE 0x17
|
||||
#define XREG_CPSR_SVC_MODE 0x13
|
||||
#define XREG_CPSR_IRQ_MODE 0x12
|
||||
#define XREG_CPSR_FIQ_MODE 0x11
|
||||
#define XREG_CPSR_USER_MODE 0x10
|
||||
|
||||
#define XREG_CPSR_IRQ_ENABLE 0x80
|
||||
#define XREG_CPSR_FIQ_ENABLE 0x40
|
||||
|
||||
#define XREG_CPSR_N_BIT 0x80000000
|
||||
#define XREG_CPSR_Z_BIT 0x40000000
|
||||
#define XREG_CPSR_C_BIT 0x20000000
|
||||
#define XREG_CPSR_V_BIT 0x10000000
|
||||
|
||||
|
||||
/* CP15 defines */
|
||||
#if defined (__GNUC__) || defined (__ICCARM__)
|
||||
/* C0 Register defines */
|
||||
#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
|
||||
#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
|
||||
#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
|
||||
#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
|
||||
#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
|
||||
|
||||
#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
|
||||
#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
|
||||
#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
|
||||
#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
|
||||
#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
|
||||
#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
|
||||
#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
|
||||
|
||||
#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
|
||||
#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
|
||||
#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
|
||||
#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
|
||||
#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
|
||||
|
||||
#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
|
||||
#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
|
||||
#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
|
||||
|
||||
#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
|
||||
|
||||
/* C1 Register Defines */
|
||||
#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
|
||||
#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
|
||||
#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
|
||||
|
||||
#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
|
||||
#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
|
||||
#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
|
||||
#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
|
||||
|
||||
#else /* RVCT */
|
||||
/* C0 Register defines */
|
||||
#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
|
||||
#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
|
||||
#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
|
||||
#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
|
||||
#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
|
||||
|
||||
#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
|
||||
#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
|
||||
#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
|
||||
#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
|
||||
#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
|
||||
#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
|
||||
#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
|
||||
|
||||
#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
|
||||
#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
|
||||
#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
|
||||
#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
|
||||
#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
|
||||
|
||||
#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
|
||||
#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
|
||||
#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
|
||||
|
||||
#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
|
||||
|
||||
/* C1 Register Defines */
|
||||
#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
|
||||
#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
|
||||
#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
|
||||
|
||||
#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
|
||||
#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
|
||||
#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
|
||||
#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
|
||||
#endif
|
||||
|
||||
/* XREG_CP15_CONTROL bit defines */
|
||||
#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
|
||||
#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
|
||||
#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
|
||||
#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
|
||||
#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
|
||||
#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
|
||||
#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
|
||||
#define XREG_CP15_CONTROL_V_BIT 0x00002000U
|
||||
#define XREG_CP15_CONTROL_I_BIT 0x00001000U
|
||||
#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
|
||||
#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
|
||||
#define XREG_CP15_CONTROL_B_BIT 0x00000080U
|
||||
#define XREG_CP15_CONTROL_C_BIT 0x00000004U
|
||||
#define XREG_CP15_CONTROL_A_BIT 0x00000002U
|
||||
#define XREG_CP15_CONTROL_M_BIT 0x00000001U
|
||||
|
||||
#if defined (__GNUC__) || defined (__ICCARM__)
|
||||
/* C2 Register Defines */
|
||||
#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
|
||||
#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
|
||||
#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
|
||||
|
||||
/* C3 Register Defines */
|
||||
#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
|
||||
|
||||
/* C4 Register Defines */
|
||||
/* Not Used */
|
||||
|
||||
/* C5 Register Defines */
|
||||
#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
|
||||
#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
|
||||
|
||||
#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
|
||||
#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
|
||||
|
||||
/* C6 Register Defines */
|
||||
#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
|
||||
#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
|
||||
|
||||
/* C7 Register Defines */
|
||||
#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
|
||||
|
||||
#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
|
||||
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
|
||||
|
||||
#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
|
||||
|
||||
#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
|
||||
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
|
||||
|
||||
/* The CP15 register access below has been deprecated in favor of the new
|
||||
* isb instruction in Cortex A9.
|
||||
*/
|
||||
#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
|
||||
#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
|
||||
|
||||
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
|
||||
#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
|
||||
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
|
||||
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
|
||||
|
||||
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
|
||||
#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
|
||||
|
||||
/* The next two CP15 register accesses below have been deprecated in favor
|
||||
* of the new dsb and dmb instructions in Cortex A9.
|
||||
*/
|
||||
#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
|
||||
#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
|
||||
|
||||
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
|
||||
|
||||
#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
|
||||
|
||||
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
|
||||
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
|
||||
|
||||
/* C8 Register Defines */
|
||||
#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
|
||||
#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
|
||||
#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
|
||||
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
|
||||
|
||||
#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
|
||||
#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
|
||||
#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
|
||||
|
||||
#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
|
||||
#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
|
||||
#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
|
||||
|
||||
#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
|
||||
#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
|
||||
#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
|
||||
#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
|
||||
|
||||
/* C9 Register Defines */
|
||||
#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
|
||||
#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
|
||||
#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
|
||||
#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
|
||||
#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
|
||||
#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
|
||||
|
||||
#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
|
||||
#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
|
||||
#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
|
||||
|
||||
#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
|
||||
#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
|
||||
#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
|
||||
|
||||
/* C10 Register Defines */
|
||||
#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
|
||||
|
||||
#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
|
||||
#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
|
||||
|
||||
/* C11 Register Defines */
|
||||
/* Not used */
|
||||
|
||||
/* C12 Register Defines */
|
||||
#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
|
||||
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
|
||||
|
||||
#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
|
||||
#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
|
||||
|
||||
/* C13 Register Defines */
|
||||
#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
|
||||
#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
|
||||
#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
|
||||
#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
|
||||
|
||||
/* C14 Register Defines */
|
||||
/* not used */
|
||||
|
||||
/* C15 Register Defines */
|
||||
#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
|
||||
#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
|
||||
|
||||
#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
|
||||
#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
|
||||
|
||||
#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
|
||||
|
||||
#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
|
||||
|
||||
#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
|
||||
|
||||
#else
|
||||
/* C2 Register Defines */
|
||||
#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
|
||||
#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
|
||||
#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
|
||||
|
||||
/* C3 Register Defines */
|
||||
#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
|
||||
|
||||
/* C4 Register Defines */
|
||||
/* Not Used */
|
||||
|
||||
/* C5 Register Defines */
|
||||
#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
|
||||
#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
|
||||
|
||||
#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
|
||||
#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
|
||||
|
||||
/* C6 Register Defines */
|
||||
#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
|
||||
#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
|
||||
|
||||
/* C7 Register Defines */
|
||||
#define XREG_CP15_NOP "cp15:0:c7:c0:4"
|
||||
|
||||
#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
|
||||
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
|
||||
|
||||
#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
|
||||
|
||||
#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
|
||||
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
|
||||
|
||||
/* The CP15 register access below has been deprecated in favor of the new
|
||||
* isb instruction in Cortex A9.
|
||||
*/
|
||||
#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
|
||||
#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
|
||||
|
||||
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
|
||||
#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
|
||||
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
|
||||
#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
|
||||
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
|
||||
#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
|
||||
|
||||
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
|
||||
#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
|
||||
|
||||
/* The next two CP15 register accesses below have been deprecated in favor
|
||||
* of the new dsb and dmb instructions in Cortex A9.
|
||||
*/
|
||||
#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
|
||||
#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
|
||||
|
||||
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
|
||||
|
||||
#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
|
||||
|
||||
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
|
||||
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
|
||||
|
||||
/* C8 Register Defines */
|
||||
#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
|
||||
#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
|
||||
#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
|
||||
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
|
||||
|
||||
#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
|
||||
#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
|
||||
#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
|
||||
|
||||
#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
|
||||
#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
|
||||
#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
|
||||
|
||||
#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
|
||||
#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
|
||||
#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
|
||||
#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
|
||||
|
||||
/* C9 Register Defines */
|
||||
#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
|
||||
#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
|
||||
#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
|
||||
#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
|
||||
#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
|
||||
#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
|
||||
|
||||
#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
|
||||
#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
|
||||
#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
|
||||
|
||||
#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
|
||||
#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
|
||||
#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
|
||||
|
||||
/* C10 Register Defines */
|
||||
#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
|
||||
|
||||
#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
|
||||
#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
|
||||
|
||||
/* C11 Register Defines */
|
||||
/* Not used */
|
||||
|
||||
/* C12 Register Defines */
|
||||
#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
|
||||
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
|
||||
|
||||
#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
|
||||
#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
|
||||
|
||||
/* C13 Register Defines */
|
||||
#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
|
||||
#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
|
||||
#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
|
||||
#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
|
||||
|
||||
/* C14 Register Defines */
|
||||
/* not used */
|
||||
|
||||
/* C15 Register Defines */
|
||||
#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
|
||||
#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
|
||||
|
||||
#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
|
||||
#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
|
||||
|
||||
#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
|
||||
|
||||
#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
|
||||
|
||||
#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
|
||||
#endif
|
||||
|
||||
|
||||
/* MPE register definitions */
|
||||
#define XREG_FPSID c0
|
||||
#define XREG_FPSCR c1
|
||||
#define XREG_MVFR1 c6
|
||||
#define XREG_MVFR0 c7
|
||||
#define XREG_FPEXC c8
|
||||
#define XREG_FPINST c9
|
||||
#define XREG_FPINST2 c10
|
||||
|
||||
/* FPSID bits */
|
||||
#define XREG_FPSID_IMPLEMENTER_BIT (24)
|
||||
#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
|
||||
#define XREG_FPSID_SOFTWARE (1<<23)
|
||||
#define XREG_FPSID_ARCH_BIT (16)
|
||||
#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
|
||||
#define XREG_FPSID_PART_BIT (8)
|
||||
#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
|
||||
#define XREG_FPSID_VARIANT_BIT (4)
|
||||
#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
|
||||
#define XREG_FPSID_REV_BIT (0)
|
||||
#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
|
||||
|
||||
/* FPSCR bits */
|
||||
#define XREG_FPSCR_N_BIT (1 << 31)
|
||||
#define XREG_FPSCR_Z_BIT (1 << 30)
|
||||
#define XREG_FPSCR_C_BIT (1 << 29)
|
||||
#define XREG_FPSCR_V_BIT (1 << 28)
|
||||
#define XREG_FPSCR_QC (1 << 27)
|
||||
#define XREG_FPSCR_AHP (1 << 26)
|
||||
#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
|
||||
#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
|
||||
#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
|
||||
#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
|
||||
#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
|
||||
#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
|
||||
#define XREG_FPSCR_RMODE_BIT (22)
|
||||
#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
|
||||
#define XREG_FPSCR_STRIDE_BIT (20)
|
||||
#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
|
||||
#define XREG_FPSCR_LENGTH_BIT (16)
|
||||
#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
|
||||
#define XREG_FPSCR_IDC (1 << 7)
|
||||
#define XREG_FPSCR_IXC (1 << 4)
|
||||
#define XREG_FPSCR_UFC (1 << 3)
|
||||
#define XREG_FPSCR_OFC (1 << 2)
|
||||
#define XREG_FPSCR_DZC (1 << 1)
|
||||
#define XREG_FPSCR_IOC (1 << 0)
|
||||
|
||||
/* MVFR0 bits */
|
||||
#define XREG_MVFR0_RMODE_BIT (28)
|
||||
#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
|
||||
#define XREG_MVFR0_SHORT_VEC_BIT (24)
|
||||
#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
|
||||
#define XREG_MVFR0_SQRT_BIT (20)
|
||||
#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
|
||||
#define XREG_MVFR0_DIVIDE_BIT (16)
|
||||
#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
|
||||
#define XREG_MVFR0_EXEC_TRAP_BIT (12)
|
||||
#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
|
||||
#define XREG_MVFR0_DP_BIT (8)
|
||||
#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
|
||||
#define XREG_MVFR0_SP_BIT (4)
|
||||
#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
|
||||
#define XREG_MVFR0_A_SIMD_BIT (0)
|
||||
#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
|
||||
|
||||
/* FPEXC bits */
|
||||
#define XREG_FPEXC_EX (1 << 31)
|
||||
#define XREG_FPEXC_EN (1 << 30)
|
||||
#define XREG_FPEXC_DEX (1 << 29)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XREG_CORTEXA9_H */
|
||||
|
|
@ -0,0 +1,439 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xuartps_hw.h
|
||||
* @addtogroup uartps_v3_1
|
||||
* @{
|
||||
*
|
||||
* This header file contains the hardware interface of an XUartPs device.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ----------------------------------------------
|
||||
* 1.00 drg/jz 01/12/10 First Release
|
||||
* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
|
||||
* and XUARTPS_IXR_TTRIG.
|
||||
* Modified the names of these defines
|
||||
* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
|
||||
* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
|
||||
* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
|
||||
* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
|
||||
* 1.05a hk 08/22/13 Added prototype for uart reset and related
|
||||
* constant definitions.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XUARTPS_HW_H /* prevent circular inclusions */
|
||||
#define XUARTPS_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Register Map
|
||||
*
|
||||
* Register offsets for the UART.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
|
||||
#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
|
||||
#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
|
||||
#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
|
||||
#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
|
||||
#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
|
||||
#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
|
||||
#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
|
||||
#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
|
||||
#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
|
||||
#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
|
||||
#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
|
||||
#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
|
||||
#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
|
||||
#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
|
||||
#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
|
||||
#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
|
||||
/* @} */
|
||||
|
||||
/** @name Control Register
|
||||
*
|
||||
* The Control register (CR) controls the major functions of the device.
|
||||
*
|
||||
* Control Register Bit Definition
|
||||
*/
|
||||
|
||||
#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
|
||||
#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
|
||||
#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
|
||||
#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
|
||||
#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
|
||||
#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
|
||||
#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
|
||||
#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
|
||||
#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
|
||||
#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
|
||||
/* @}*/
|
||||
|
||||
/** @name Mode Register
|
||||
*
|
||||
* The mode register (MR) defines the mode of transfer as well as the data
|
||||
* format. If this register is modified during transmission or reception,
|
||||
* data validity cannot be guaranteed.
|
||||
*
|
||||
* Mode Register Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
|
||||
#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
|
||||
#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
|
||||
#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
|
||||
#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
|
||||
#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
|
||||
#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
|
||||
#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
|
||||
#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
|
||||
#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
|
||||
#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
|
||||
#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
|
||||
#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
|
||||
#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
|
||||
#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
|
||||
#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
|
||||
#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
|
||||
#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
|
||||
#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
|
||||
#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
|
||||
#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
|
||||
#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
|
||||
#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
|
||||
#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
|
||||
#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Registers
|
||||
*
|
||||
* Interrupt control logic uses the interrupt enable register (IER) and the
|
||||
* interrupt disable register (IDR) to set the value of the bits in the
|
||||
* interrupt mask register (IMR). The IMR determines whether to pass an
|
||||
* interrupt to the interrupt status register (ISR).
|
||||
* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
|
||||
* interrupt. IMR and ISR are read only, and IER and IDR are write only.
|
||||
* Reading either IER or IDR returns 0x00.
|
||||
*
|
||||
* All four registers have the same bit definitions.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
|
||||
#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
|
||||
#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
|
||||
#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
|
||||
#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
|
||||
#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
|
||||
#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
|
||||
#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
|
||||
#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
|
||||
#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
|
||||
#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
|
||||
#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
|
||||
#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
|
||||
#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
|
||||
#define XUARTPS_IXR_MASK 0x00001FFFU /**< Valid bit mask */
|
||||
/* @} */
|
||||
|
||||
/** @name Baud Rate Generator Register
|
||||
*
|
||||
* The baud rate generator control register (BRGR) is a 16 bit register that
|
||||
* controls the receiver bit sample clock and baud rate.
|
||||
* Valid values are 1 - 65535.
|
||||
*
|
||||
* Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
|
||||
* in the MR register.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
|
||||
#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
|
||||
#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
|
||||
|
||||
/** @name Baud Divisor Rate register
|
||||
*
|
||||
* The baud rate divider register (BDIV) controls how much the bit sample
|
||||
* rate is divided by. It sets the baud rate.
|
||||
* Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
|
||||
*
|
||||
* Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
|
||||
* the MR_CCLK bit in the MR register.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
|
||||
#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Receiver Timeout Register
|
||||
*
|
||||
* Use the receiver timeout register (RTR) to detect an idle condition on
|
||||
* the receiver data line.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
|
||||
#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
|
||||
|
||||
/** @name Receiver FIFO Trigger Level Register
|
||||
*
|
||||
* Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
|
||||
* which the RX FIFO triggers an interrupt event.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
|
||||
#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
|
||||
#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Transmit FIFO Trigger Level Register
|
||||
*
|
||||
* Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
|
||||
* which the TX FIFO triggers an interrupt event.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
|
||||
#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Modem Control Register
|
||||
*
|
||||
* This register (MODEMCR) controls the interface with the modem or data set,
|
||||
* or a peripheral device emulating a modem.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */
|
||||
#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
|
||||
#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
|
||||
/* @} */
|
||||
|
||||
/** @name Modem Status Register
|
||||
*
|
||||
* This register (MODEMSR) indicates the current state of the control lines
|
||||
* from a modem, or another peripheral device, to the CPU. In addition, four
|
||||
* bits of the modem status register provide change information. These bits
|
||||
* are set to a logic 1 whenever a control input from the modem changes state.
|
||||
*
|
||||
* Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
|
||||
* status interrupt is generated and this is reflected in the modem status
|
||||
* register.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
|
||||
#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
|
||||
#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
|
||||
#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
|
||||
#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
|
||||
#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
|
||||
#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
|
||||
#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
|
||||
#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
|
||||
/* @} */
|
||||
|
||||
/** @name Channel Status Register
|
||||
*
|
||||
* The channel status register (CSR) is provided to enable the control logic
|
||||
* to monitor the status of bits in the channel interrupt status register,
|
||||
* even if these are masked out by the interrupt mask register.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
|
||||
#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
|
||||
#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
|
||||
#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
|
||||
#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
|
||||
#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
|
||||
#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
|
||||
#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
|
||||
#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
|
||||
#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
|
||||
/* @} */
|
||||
|
||||
/** @name Flow Delay Register
|
||||
*
|
||||
* Operation of the flow delay register (FLOWDEL) is very similar to the
|
||||
* receive FIFO trigger register. An internal trigger signal activates when the
|
||||
* FIFO is filled to the level set by this register. This trigger will not
|
||||
* cause an interrupt, although it can be read through the channel status
|
||||
* register. In hardware flow control mode, RTS is deactivated when the trigger
|
||||
* becomes active. RTS only resets when the FIFO level is four less than the
|
||||
* level of the flow delay trigger and the flow delay trigger is not activated.
|
||||
* A value less than 4 disables the flow delay.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
|
||||
/* @} */
|
||||
|
||||
/** @name Receiver FIFO Byte Status Register
|
||||
*
|
||||
* The Receiver FIFO Status register is used to have a continuous
|
||||
* monitoring of the raw unmasked byte status information. The register
|
||||
* contains frame, parity and break status information for the top
|
||||
* four bytes in the RX FIFO.
|
||||
*
|
||||
* Receiver FIFO Byte Status Register Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
|
||||
#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
|
||||
#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
|
||||
#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
|
||||
#define XUARTPS_RXBS_MASK 0x00000FFFU /**< 24 bit RX byte status mask */
|
||||
/* @} */
|
||||
|
||||
/*
|
||||
* Defines for backwards compatabilty, will be removed
|
||||
* in the next version of the driver
|
||||
*/
|
||||
#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
|
||||
#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
|
||||
#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
|
||||
#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Read a UART register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset contains the offset from the base address of the
|
||||
* device.
|
||||
*
|
||||
* @return The value read from the register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUartPs_ReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (u32)(RegOffset))
|
||||
|
||||
/***************************************************************************/
|
||||
/**
|
||||
* Write a UART register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset contains the offset from the base address of the
|
||||
* device.
|
||||
* @param RegisterValue is the value to be written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
|
||||
* u16 RegisterValue)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
|
||||
Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Determine if there is receive data in the receiver and/or FIFO.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
*
|
||||
* @return TRUE if there is receive data, FALSE otherwise.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XUartPs_IsReceiveData(u32 BaseAddress)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUartPs_IsReceiveData(BaseAddress) \
|
||||
!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Determine if a byte of data can be sent with the transmitter.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
*
|
||||
* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
|
||||
* FIFO.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUartPs_IsTransmitFull(BaseAddress) \
|
||||
((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XUartPs_SendByte(u32 BaseAddress, u8 Data);
|
||||
|
||||
u8 XUartPs_RecvByte(u32 BaseAddress);
|
||||
|
||||
void XUartPs_ResetHw(u32 BaseAddress);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_io.c
|
||||
*
|
||||
* Contains I/O functions for memory-mapped or non-memory-mapped I/O
|
||||
* architectures. These functions encapsulate Cortex A9 architecture-specific
|
||||
* I/O requirements.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* This file contains architecture-dependent code.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 1.00a ecm/sdm 10/24/09 First release
|
||||
* 3.06a sgd 05/15/12 Pointer volatile used for the all read functions
|
||||
* 3.07a sgd 08/17/12 Removed barriers (SYNCHRONIZE_IO) calls.
|
||||
* 3.09a sgd 02/05/13 Comments cleanup
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xil_io.h"
|
||||
#include "xil_types.h"
|
||||
#include "xpseudo_asm.h"
|
||||
#include "xreg_cortexa9.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for an 8-bit memory location by reading from the
|
||||
* specified address and returning the Value read from that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u8 Xil_In8(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u8*)Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 16-bit memory location by reading from the
|
||||
* specified address and returning the Value read from that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u16 Xil_In16(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u16*)Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 32-bit memory location by reading from the
|
||||
* specified address and returning the Value read from that address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 Xil_In32(INTPTR Addr)
|
||||
{
|
||||
return *(volatile u32*)Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for an 8-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out8(INTPTR Addr, u8 Value)
|
||||
{
|
||||
u8* LocalAddr = (u8*)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 16-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out16(INTPTR Addr, u16 Value)
|
||||
{
|
||||
u16* LocalAddr = (u16*)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 32-bit memory location by writing the
|
||||
* specified Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out32(INTPTR Addr, u32 Value)
|
||||
{
|
||||
u32* LocalAddr = (u32*)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 16-bit memory location by reading from the
|
||||
* specified address and returning the byte-swapped Value read from that
|
||||
* address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The byte-swapped Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u16 Xil_In16BE(INTPTR Addr)
|
||||
{
|
||||
u16 temp;
|
||||
u16 result;
|
||||
|
||||
temp = Xil_In16(Addr);
|
||||
|
||||
result = Xil_EndianSwap16(temp);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an input operation for a 32-bit memory location by reading from the
|
||||
* specified address and returning the byte-swapped Value read from that
|
||||
* address.
|
||||
*
|
||||
* @param Addr contains the address to perform the input operation
|
||||
* at.
|
||||
*
|
||||
* @return The byte-swapped Value read from the specified input address.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 Xil_In32BE(INTPTR Addr)
|
||||
{
|
||||
u32 temp;
|
||||
u32 result;
|
||||
|
||||
temp = Xil_In32(Addr);
|
||||
|
||||
result = Xil_EndianSwap32(temp);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 16-bit memory location by writing the
|
||||
* specified Value to the the specified address. The Value is byte-swapped
|
||||
* before being written.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out16BE(INTPTR Addr, u16 Value)
|
||||
{
|
||||
u16 temp;
|
||||
|
||||
temp = Xil_EndianSwap16(Value);
|
||||
|
||||
Xil_Out16(Addr, temp);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Performs an output operation for a 32-bit memory location by writing the
|
||||
* specified Value to the the specified address. The Value is byte-swapped
|
||||
* before being written.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* at.
|
||||
* @param Value contains the Value to be output at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void Xil_Out32BE(INTPTR Addr, u32 Value)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
temp = Xil_EndianSwap32(Value);
|
||||
|
||||
Xil_Out32(Addr, temp);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a 16-bit endian converion.
|
||||
*
|
||||
* @param Data contains the value to be converted.
|
||||
*
|
||||
* @return converted value.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u16 Xil_EndianSwap16(u16 Data)
|
||||
{
|
||||
return (u16)(((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Perform a 32-bit endian converion.
|
||||
*
|
||||
* @param Data contains the value to be converted.
|
||||
*
|
||||
* @return converted value.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 Xil_EndianSwap32(u32 Data)
|
||||
{
|
||||
u16 LoWord;
|
||||
u16 HiWord;
|
||||
|
||||
/* get each of the half words from the 32 bit word */
|
||||
|
||||
LoWord = (u16)(Data & 0x0000FFFFU);
|
||||
HiWord = (u16)((Data & 0xFFFF0000U) >> 16U);
|
||||
|
||||
/* byte swap each of the 16 bit half words */
|
||||
|
||||
LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
|
||||
HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
|
||||
|
||||
/* swap the half words before returning the value */
|
||||
|
||||
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
|
||||
}
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xuartps_hw.c
|
||||
* @addtogroup uartps_v3_1
|
||||
* @{
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ----------------------------------------------
|
||||
* 1.00 drg/jz 01/12/10 First Release
|
||||
* 1.05a hk 08/22/13 Added reset function
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
#include "xuartps_hw.h"
|
||||
|
||||
#include "mmio_access.h"
|
||||
#include "uart_common_ope.h"
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sends one byte using the device. This function operates in
|
||||
* polled mode and blocks until the data has been put into the TX FIFO register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param Data contains the byte to be sent.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XUartPs_SendByte(u32 BaseAddress, u8 Data)
|
||||
{
|
||||
/* Wait until there is space in TX FIFO */
|
||||
while (XUartPs_IsTransmitFull(BaseAddress)) {
|
||||
;
|
||||
}
|
||||
|
||||
/* Write the byte into the TX FIFO */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function receives a byte from the device. It operates in polled mode
|
||||
* and blocks until a byte has received.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
*
|
||||
* @return The data byte received.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
u8 XUartPs_RecvByte(u32 BaseAddress)
|
||||
{
|
||||
u32 RecievedByte;
|
||||
/* Wait until there is data */
|
||||
while (!XUartPs_IsReceiveData(BaseAddress)) {
|
||||
;
|
||||
}
|
||||
RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
|
||||
/* Return the byte received */
|
||||
return (u8)RecievedByte;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function resets UART
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XUartPs_ResetHw(u32 BaseAddress)
|
||||
{
|
||||
|
||||
/* Disable interrupts */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
|
||||
|
||||
/* Disable receive and transmit */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
|
||||
((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
|
||||
|
||||
/*
|
||||
* Software reset of receive and transmit
|
||||
* This clears the FIFO.
|
||||
*/
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
|
||||
((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
|
||||
|
||||
/* Clear status flags - SW reset wont clear sticky flags. */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
|
||||
|
||||
/*
|
||||
* Mode register reset value : All zeroes
|
||||
* Normal mode, even parity, 1 stop bit
|
||||
*/
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
|
||||
XUARTPS_MR_CHMODE_NORM);
|
||||
|
||||
/* Rx and TX trigger register reset values */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
|
||||
XUARTPS_RXWM_RESET_VAL);
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
|
||||
XUARTPS_TXWM_RESET_VAL);
|
||||
|
||||
/* Rx timeout disabled by default */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
|
||||
XUARTPS_RXTOUT_DISABLE);
|
||||
|
||||
/* Baud rate generator and dividor reset values */
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
|
||||
XUARTPS_BAUDGEN_RESET_VAL);
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
|
||||
XUARTPS_BAUDDIV_RESET_VAL);
|
||||
|
||||
/*
|
||||
* Control register reset value -
|
||||
* RX and TX are disable by default
|
||||
*/
|
||||
XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
|
||||
((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS | (u32)XUARTPS_CR_STOPBRK));
|
||||
}
|
||||
|
||||
#define STDIN_BASEADDRESS 0xE0001000
|
||||
#define STDOUT_BASEADDRESS 0xE0001000
|
||||
void UartPutChar(uint8_t ch)
|
||||
{
|
||||
if (ch == '\n') {
|
||||
XUartPs_SendByte(MMIO_P2V(STDOUT_BASEADDRESS), '\r');
|
||||
}
|
||||
XUartPs_SendByte(MMIO_P2V(STDOUT_BASEADDRESS), ch);
|
||||
}
|
||||
|
||||
static uint8_t UartGetChar()
|
||||
{
|
||||
return XUartPs_RecvByte(MMIO_P2V(STDIN_BASEADDRESS));
|
||||
}
|
||||
|
||||
static void UartInit()
|
||||
{
|
||||
}
|
||||
|
||||
static uint32_t UartGetIrqnum()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct XiziSerialDriver hardkernel_serial_driver = {
|
||||
.sys_serial_init = UartInit,
|
||||
.get_serial_irqnum = UartGetIrqnum,
|
||||
.putc = UartPutChar,
|
||||
.getc = UartGetChar,
|
||||
};
|
||||
|
||||
struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
|
||||
{
|
||||
hardkernel_serial_driver.sys_serial_init();
|
||||
return &hardkernel_serial_driver;
|
||||
}
|
||||
/** @} */
|
||||
|
|
@ -5,32 +5,51 @@ ifeq ($(CONFIG_LIB_NEWLIB),y)
|
|||
KERNELPATHS += -I$(KERNEL_ROOT)/services/lib/newlib/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/services/boards/imx6q-sabrelite)
|
||||
ifeq ($(BOARD), imx6q-sabrelite)
|
||||
KERNELPATHS += \
|
||||
-I$(KERNEL_ROOT)/hardkernel \
|
||||
-I$(KERNEL_ROOT)/hardkernel/boot/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/boot/sdk/imx6/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cpu/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cpu/sdk/imx6/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/gicv2 \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/
|
||||
endif
|
||||
|
||||
ifeq ($(BOARD), zynq7000-zc702)
|
||||
KERNELPATHS += \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv7-a/cortex-a9/$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/gicv2 \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3 \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_$(BOARD)/include \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a9/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/
|
||||
endif
|
||||
|
||||
KERNELPATHS += \
|
||||
-I$(KERNEL_ROOT)/hardkernel \
|
||||
-I$(KERNEL_ROOT)/hardkernel/clock/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/mmu/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/intr/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/uart/ \
|
||||
-I$(KERNEL_ROOT)/hardkernel/cache/
|
||||
|
||||
KERNELPATHS += \
|
||||
-I$(KERNEL_ROOT)/softkernel/include \
|
||||
-I$(KERNEL_ROOT)/kernel_actracer/ \
|
||||
-I$(KERNEL_ROOT)/include
|
||||
endif
|
||||
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list #
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
|
||||
SRC_DIR := fs shell lib tools boards
|
||||
|
||||
SRC_DIR := fs shell lib boards tools app
|
||||
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
ifeq ($(BOARD), imx6q-sabrelite)
|
||||
toolchain ?= arm-none-eabi-
|
||||
user_ldflags = --specs=nosys.specs -Wl,-Map=user.map,-cref -N
|
||||
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
|
||||
endif
|
||||
ifeq ($(BOARD), zynq7000-zc702)
|
||||
toolchain ?= arm-xilinx-eabi-
|
||||
user_ldflags = -Wl,--start-group,-lgcc,-lc,--end-group -N
|
||||
cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
|
||||
board_specs = stub.o
|
||||
#cflags = -Wall -g -std=c11
|
||||
endif
|
||||
|
||||
cc = ${toolchain}gcc
|
||||
ld = ${toolchain}g++
|
||||
objdump = ${toolchain}objdump
|
||||
c_useropts = -O0
|
||||
|
||||
INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \
|
||||
-I$(KERNEL_ROOT)/services/lib/ipc \
|
||||
-I$(KERNEL_ROOT)/services/lib/memory \
|
||||
-I$(KERNEL_ROOT)/services/fs/libfs \
|
||||
-I$(KERNEL_ROOT)/services/boards/$(BOARD) \
|
||||
-I$(KERNEL_ROOT)/services/app
|
||||
|
||||
all: init simple_client simple_server shell fs_server test_priority readme.txt | bin
|
||||
../tools/mkfs/mkfs ./fs.img $^
|
||||
@mv $(filter-out readme.txt, $^) bin
|
||||
@mv *.o bin
|
||||
@mv *.asm bin
|
||||
|
||||
bin:
|
||||
@mkdir -p bin
|
||||
|
||||
shell: shell_port.o libserial.o shell_cmd_list.o shell.o shell_ext.o libfs_to_client.o libipc.o session.o usyscall.o
|
||||
@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
|
||||
@${objdump} -S $@ > $@.asm
|
||||
|
||||
init: init.o libfs_to_client.o libipc.o session.o libserial.o usyscall.o
|
||||
@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
|
||||
@${objdump} -S $@ > $@.asm
|
||||
|
||||
simple_client: simple_client.o libserial.o libipc.o session.o simple_service.o libfs_to_client.o usyscall.o
|
||||
@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
|
||||
@${objdump} -S $@ > $@.asm
|
||||
|
||||
simple_server: simple_server.o libserial.o libipc.o session.o simple_service.o usyscall.o
|
||||
@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
|
||||
@${objdump} -S $@ > $@.asm
|
||||
|
||||
fs_server: fs_server.o libfs_to_client.o fs.o libserial.o libipc.o session.o block_io.o usyscall.o
|
||||
@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
|
||||
@${objdump} -S $@ > $@.asm
|
||||
|
||||
test_priority: test_priority.o libserial.o usyscall.o
|
||||
@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
|
||||
@${objdump} -S $@ > $@.asm
|
||||
|
||||
%.o: %.c
|
||||
@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $<
|
||||
|
||||
%.o: %.S
|
||||
@${cc} ${cflags} ${c_useropts} -o $@ -c $<
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue