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Modify DWC3 reg size to aligned to 4096

This commit is contained in:
songyanguang 2024-09-13 15:31:22 +08:00
parent b9c3e22f5f
commit 7b5369a1f3
1 changed files with 5 additions and 1 deletions
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6
Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/xhci/usb_hc_xhci.h
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@ -60,7 +60,11 @@ extern "C" {
#define USB3_0_BASE_ADDR 0xFCC00000
#define USB3_1_BASE_ADDR 0xFD000000
#define USB3_ADDR_OFFSET_UPPER_BOUND 0x08000
#define USB3_DWC3_ADDR_GAP 0x0C00
/*
* The size of all DWC3 registers (including OTG regs) is 0xC00. However, the XiZi AIOT requires the I/O memory size to be aligned to 4096.
* So we define USB3_DWC3_ADDR_GAP as 0x01000.
*/
#define USB3_DWC3_ADDR_GAP 0x01000
#define USB3_VIRADDR_BASE 0x0000002000000000ULL
#define USB3_0_VIRADDR_BASE USB3_VIRADDR_BASE