forked from xuos/xiuos
add DWC3 codes
This commit is contained in:
xj
parent
33ac3e9048
commit
6229f7b1c8
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@ -8,9 +8,858 @@
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#include "xhci.h"
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#include "gadget.h"
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#define DWC3_MSG_MAX 500
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/* Global constants */
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#define DWC3_EP0_BOUNCE_SIZE 512
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#define DWC3_ENDPOINTS_NUM 32
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#define DWC3_XHCI_RESOURCES_NUM 2
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#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
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#define DWC3_EVENT_SIZE 4 /* bytes */
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#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
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#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
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#define DWC3_EVENT_TYPE_MASK 0xfe
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#define DWC3_EVENT_TYPE_DEV 0
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#define DWC3_EVENT_TYPE_CARKIT 3
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#define DWC3_EVENT_TYPE_I2C 4
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#define DWC3_DEVICE_EVENT_DISCONNECT 0
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#define DWC3_DEVICE_EVENT_RESET 1
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#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
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#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
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#define DWC3_DEVICE_EVENT_WAKEUP 4
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#define DWC3_DEVICE_EVENT_HIBER_REQ 5
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#define DWC3_DEVICE_EVENT_EOPF 6
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#define DWC3_DEVICE_EVENT_SOF 7
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#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
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#define DWC3_DEVICE_EVENT_CMD_CMPL 10
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#define DWC3_DEVICE_EVENT_OVERFLOW 11
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#define DWC3_GEVNTCOUNT_MASK 0xfffc
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#define DWC3_GSNPSID_MASK 0xffff0000
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#define DWC3_GSNPSREV_MASK 0xffff
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/* DWC3 registers memory space boundries */
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#define DWC3_XHCI_REGS_START 0x0
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#define DWC3_XHCI_REGS_END 0x7fff
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#define DWC3_GLOBALS_REGS_START 0xc100
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#define DWC3_GLOBALS_REGS_END 0xc6ff
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#define DWC3_DEVICE_REGS_START 0xc700
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#define DWC3_DEVICE_REGS_END 0xcbff
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#define DWC3_OTG_REGS_START 0xcc00
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#define DWC3_OTG_REGS_END 0xccff
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/* Global Registers */
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#define DWC3_GSBUSCFG0 0xc100
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#define DWC3_GSBUSCFG1 0xc104
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#define DWC3_GTXTHRCFG 0xc108
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#define DWC3_GRXTHRCFG 0xc10c
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#define DWC3_GCTL 0xc110
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#define DWC3_GEVTEN 0xc114
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#define DWC3_GSTS 0xc118
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#define DWC3_GUCTL1 0xc11c
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#define DWC3_GSNPSID 0xc120
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#define DWC3_GGPIO 0xc124
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#define DWC3_GUID 0xc128
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#define DWC3_GUCTL 0xc12c
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#define DWC3_GBUSERRADDR0 0xc130
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#define DWC3_GBUSERRADDR1 0xc134
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#define DWC3_GPRTBIMAP0 0xc138
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#define DWC3_GPRTBIMAP1 0xc13c
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#define DWC3_GHWPARAMS0 0xc140
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#define DWC3_GHWPARAMS1 0xc144
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#define DWC3_GHWPARAMS2 0xc148
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#define DWC3_GHWPARAMS3 0xc14c
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#define DWC3_GHWPARAMS4 0xc150
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#define DWC3_GHWPARAMS5 0xc154
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#define DWC3_GHWPARAMS6 0xc158
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#define DWC3_GHWPARAMS7 0xc15c
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#define DWC3_GDBGFIFOSPACE 0xc160
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#define DWC3_GDBGLTSSM 0xc164
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#define DWC3_GPRTBIMAP_HS0 0xc180
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#define DWC3_GPRTBIMAP_HS1 0xc184
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#define DWC3_GPRTBIMAP_FS0 0xc188
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#define DWC3_GPRTBIMAP_FS1 0xc18c
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#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
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#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
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#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
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#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
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#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
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#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
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#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
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#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
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#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
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#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
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#define DWC3_GHWPARAMS8 0xc600
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/* Device Registers */
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#define DWC3_DCFG 0xc700
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#define DWC3_DCTL 0xc704
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#define DWC3_DEVTEN 0xc708
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#define DWC3_DSTS 0xc70c
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#define DWC3_DGCMDPAR 0xc710
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#define DWC3_DGCMD 0xc714
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#define DWC3_DALEPENA 0xc720
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#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
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#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
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#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
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#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
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/* OTG Registers */
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#define DWC3_OCFG 0xcc00
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#define DWC3_OCTL 0xcc04
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#define DWC3_OEVT 0xcc08
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#define DWC3_OEVTEN 0xcc0C
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#define DWC3_OSTS 0xcc10
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/* Bit fields */
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/* Global Configuration Register */
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#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
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#define DWC3_GCTL_U2RSTECN (1 << 16)
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#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
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#define DWC3_GCTL_CLK_BUS (0)
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#define DWC3_GCTL_CLK_PIPE (1)
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#define DWC3_GCTL_CLK_PIPEHALF (2)
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#define DWC3_GCTL_CLK_MASK (3)
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#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
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#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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#define DWC3_GCTL_PRTCAP_HOST 1
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#define DWC3_GCTL_PRTCAP_DEVICE 2
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_SOFITPSYNC (1 << 10)
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
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#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* Global User Control 1 Register */
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#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
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#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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#define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
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#define USBTRDTIM_UTMI_8_BIT 9
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#define USBTRDTIM_UTMI_16_BIT 5
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#define UTMI_PHYIF_16_BIT 1
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#define UTMI_PHYIF_8_BIT 0
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
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#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
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#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
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#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
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#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
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#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
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#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
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#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
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#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
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/* Global TX Fifo Size Register */
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#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
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#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
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/* Global Event Size Registers */
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#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
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#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
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/* Global HWPARAMS1 Register */
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#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
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#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
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#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
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#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
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#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
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/* Global HWPARAMS3 Register */
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#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
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#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
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#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
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#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
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#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
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#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
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#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
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#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
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#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
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#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
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#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
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/* Global HWPARAMS4 Register */
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#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
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#define DWC3_MAX_HIBER_SCRATCHBUFS 15
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/* Global HWPARAMS6 Register */
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#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
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/* Device Configuration Register */
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#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
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#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
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#define DWC3_DCFG_SPEED_MASK (7 << 0)
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#define DWC3_DCFG_SUPERSPEED (4 << 0)
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#define DWC3_DCFG_HIGHSPEED (0 << 0)
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#define DWC3_DCFG_FULLSPEED2 (1 << 0)
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#define DWC3_DCFG_LOWSPEED (2 << 0)
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#define DWC3_DCFG_FULLSPEED1 (3 << 0)
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#define DWC3_DCFG_LPM_CAP (1 << 22)
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/* Device Control Register */
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#define DWC3_DCTL_RUN_STOP (1 << 31)
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#define DWC3_DCTL_CSFTRST (1 << 30)
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#define DWC3_DCTL_LSFTRST (1 << 29)
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#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
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#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
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#define DWC3_DCTL_APPL1RES (1 << 23)
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/* These apply for core versions 1.87a and earlier */
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#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
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#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
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#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
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#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
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#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
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#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
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#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
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/* These apply for core versions 1.94a and later */
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#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
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#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
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#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
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#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
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#define DWC3_DCTL_CRS (1 << 17)
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#define DWC3_DCTL_CSS (1 << 16)
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#define DWC3_DCTL_INITU2ENA (1 << 12)
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#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
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#define DWC3_DCTL_INITU1ENA (1 << 10)
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#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
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#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
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#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
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#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
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#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
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#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
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#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
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#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
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#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
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#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
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#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
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/* Device Event Enable Register */
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#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
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#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
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#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
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#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
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#define DWC3_DEVTEN_SOFEN (1 << 7)
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#define DWC3_DEVTEN_EOPFEN (1 << 6)
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#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
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#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
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#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
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#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
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#define DWC3_DEVTEN_USBRSTEN (1 << 1)
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#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
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/* Device Status Register */
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#define DWC3_DSTS_DCNRD (1 << 29)
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/* This applies for core versions 1.87a and earlier */
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#define DWC3_DSTS_PWRUPREQ (1 << 24)
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/* These apply for core versions 1.94a and later */
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#define DWC3_DSTS_RSS (1 << 25)
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#define DWC3_DSTS_SSS (1 << 24)
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#define DWC3_DSTS_COREIDLE (1 << 23)
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#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
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#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
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#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
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#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
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#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
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#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
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#define DWC3_DSTS_CONNECTSPD (7 << 0)
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#define DWC3_DSTS_SUPERSPEED (4 << 0)
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#define DWC3_DSTS_HIGHSPEED (0 << 0)
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#define DWC3_DSTS_FULLSPEED2 (1 << 0)
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#define DWC3_DSTS_LOWSPEED (2 << 0)
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#define DWC3_DSTS_FULLSPEED1 (3 << 0)
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/* Device Generic Command Register */
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#define DWC3_DGCMD_SET_LMP 0x01
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#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
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#define DWC3_DGCMD_XMIT_FUNCTION 0x03
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/* These apply for core versions 1.94a and later */
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#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
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#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
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#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
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#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
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#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
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#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
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#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
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#define DWC3_DGCMD_CMDACT (1 << 10)
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#define DWC3_DGCMD_CMDIOC (1 << 8)
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/* Device Generic Command Parameter Register */
|
||||
#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
|
||||
#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
|
||||
#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
|
||||
#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
|
||||
#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
|
||||
#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
|
||||
|
||||
/* Device Endpoint Command Register */
|
||||
#define DWC3_DEPCMD_PARAM_SHIFT 16
|
||||
#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
|
||||
#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
|
||||
#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
|
||||
#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
|
||||
#define DWC3_DEPCMD_CMDACT (1 << 10)
|
||||
#define DWC3_DEPCMD_CMDIOC (1 << 8)
|
||||
|
||||
#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
|
||||
#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
|
||||
#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
|
||||
#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
|
||||
#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
|
||||
#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
|
||||
/* This applies for core versions 1.90a and earlier */
|
||||
#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
|
||||
/* This applies for core versions 1.94a and later */
|
||||
#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
|
||||
#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
|
||||
#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
|
||||
|
||||
/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
|
||||
#define DWC3_DALEPENA_EP(n) (1 << n)
|
||||
|
||||
#define DWC3_DEPCMD_TYPE_CONTROL 0
|
||||
#define DWC3_DEPCMD_TYPE_ISOC 1
|
||||
#define DWC3_DEPCMD_TYPE_BULK 2
|
||||
#define DWC3_DEPCMD_TYPE_INTR 3
|
||||
|
||||
struct dwc3_trb;
|
||||
struct dwc3;
|
||||
|
||||
|
||||
/**
|
||||
* struct dwc3_event_buffer - Software event buffer representation
|
||||
* @buf: _THE_ buffer
|
||||
* @length: size of this buffer
|
||||
* @lpos: event offset
|
||||
* @count: cache of last read event count register
|
||||
* @flags: flags related to this event buffer
|
||||
* @dma: dma_addr_t
|
||||
* @dwc: pointer to DWC controller
|
||||
*/
|
||||
struct dwc3_event_buffer {
|
||||
void *buf;
|
||||
uint16_t length;
|
||||
unsigned int lpos;
|
||||
unsigned int count;
|
||||
unsigned int flags;
|
||||
|
||||
#define DWC3_EVENT_PENDING (1UL << 0)
|
||||
uintptr_t dma;
|
||||
struct dwc3 *dwc;
|
||||
};
|
||||
|
||||
#define DWC3_EP_FLAG_STALLED (1 << 0)
|
||||
#define DWC3_EP_FLAG_WEDGED (1 << 1)
|
||||
|
||||
#define DWC3_EP_DIRECTION_TX true
|
||||
#define DWC3_EP_DIRECTION_RX false
|
||||
|
||||
#define DWC3_TRB_NUM 32
|
||||
#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
|
||||
|
||||
struct dwc3_ep {
|
||||
struct usb_ep endpoint;
|
||||
usb_slist_t request_list;
|
||||
usb_slist_t req_queued;
|
||||
|
||||
struct dwc3_trb *trb_pool;
|
||||
uintptr_t trb_pool_dma;
|
||||
uint32_t free_slot;
|
||||
uint32_t busy_slot;
|
||||
const struct usb_ss_ep_comp_descriptor *comp_desc;
|
||||
struct dwc3 *dwc;
|
||||
|
||||
uint32_t saved_state;
|
||||
unsigned flags;
|
||||
#define DWC3_EP_ENABLED (1 << 0)
|
||||
#define DWC3_EP_STALL (1 << 1)
|
||||
#define DWC3_EP_WEDGE (1 << 2)
|
||||
#define DWC3_EP_BUSY (1 << 4)
|
||||
#define DWC3_EP_PENDING_REQUEST (1 << 5)
|
||||
#define DWC3_EP_MISSED_ISOC (1 << 6)
|
||||
|
||||
/* This last one is specific to EP0 */
|
||||
#define DWC3_EP0_DIR_IN (1 << 31)
|
||||
|
||||
unsigned current_trb;
|
||||
|
||||
uint8_t number;
|
||||
uint8_t type;
|
||||
uint8_t resource_index;
|
||||
uint32_t interval;
|
||||
|
||||
char name[20];
|
||||
|
||||
unsigned direction:1;
|
||||
unsigned stream_capable:1;
|
||||
};
|
||||
|
||||
|
||||
enum usb_dr_mode {
|
||||
USB_DR_MODE_UNKNOWN,
|
||||
USB_DR_MODE_HOST,
|
||||
USB_DR_MODE_PERIPHERAL,
|
||||
USB_DR_MODE_OTG,
|
||||
};
|
||||
|
||||
enum dwc3_phy {
|
||||
DWC3_PHY_UNKNOWN = 0,
|
||||
DWC3_PHY_USB3,
|
||||
DWC3_PHY_USB2,
|
||||
};
|
||||
|
||||
|
||||
enum usb_phy_interface {
|
||||
USBPHY_INTERFACE_MODE_UNKNOWN,
|
||||
USBPHY_INTERFACE_MODE_UTMI,
|
||||
USBPHY_INTERFACE_MODE_UTMIW,
|
||||
};
|
||||
|
||||
enum dwc3_ep0_next {
|
||||
DWC3_EP0_UNKNOWN = 0,
|
||||
DWC3_EP0_COMPLETE,
|
||||
DWC3_EP0_NRDY_DATA,
|
||||
DWC3_EP0_NRDY_STATUS,
|
||||
};
|
||||
|
||||
enum dwc3_ep0_state {
|
||||
EP0_UNCONNECTED = 0,
|
||||
EP0_SETUP_PHASE,
|
||||
EP0_DATA_PHASE,
|
||||
EP0_STATUS_PHASE,
|
||||
};
|
||||
|
||||
enum dwc3_link_state {
|
||||
/* In SuperSpeed */
|
||||
DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
|
||||
DWC3_LINK_STATE_U1 = 0x01,
|
||||
DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
|
||||
DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
|
||||
DWC3_LINK_STATE_SS_DIS = 0x04,
|
||||
DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
|
||||
DWC3_LINK_STATE_SS_INACT = 0x06,
|
||||
DWC3_LINK_STATE_POLL = 0x07,
|
||||
DWC3_LINK_STATE_RECOV = 0x08,
|
||||
DWC3_LINK_STATE_HRESET = 0x09,
|
||||
DWC3_LINK_STATE_CMPLY = 0x0a,
|
||||
DWC3_LINK_STATE_LPBK = 0x0b,
|
||||
DWC3_LINK_STATE_RESET = 0x0e,
|
||||
DWC3_LINK_STATE_RESUME = 0x0f,
|
||||
DWC3_LINK_STATE_MASK = 0x0f,
|
||||
};
|
||||
|
||||
|
||||
/* TRB Length, PCM and Status */
|
||||
#define DWC3_TRB_SIZE_MASK (0x00ffffff)
|
||||
#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
|
||||
#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
|
||||
#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
|
||||
|
||||
#define DWC3_TRBSTS_OK 0
|
||||
#define DWC3_TRBSTS_MISSED_ISOC 1
|
||||
#define DWC3_TRBSTS_SETUP_PENDING 2
|
||||
#define DWC3_TRB_STS_XFER_IN_PROG 4
|
||||
|
||||
/* TRB Control */
|
||||
#define DWC3_TRB_CTRL_HWO (1 << 0)
|
||||
#define DWC3_TRB_CTRL_LST (1 << 1)
|
||||
#define DWC3_TRB_CTRL_CHN (1 << 2)
|
||||
#define DWC3_TRB_CTRL_CSP (1 << 3)
|
||||
#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
|
||||
#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
|
||||
#define DWC3_TRB_CTRL_IOC (1 << 11)
|
||||
#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
|
||||
|
||||
#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
|
||||
#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
|
||||
#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
|
||||
#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
|
||||
#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
|
||||
#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
|
||||
#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
|
||||
#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
|
||||
|
||||
|
||||
struct dwc3_trb {
|
||||
uint32_t bpl;
|
||||
uint32_t bph;
|
||||
uint32_t size;
|
||||
uint32_t ctrl;
|
||||
} __packed;
|
||||
|
||||
|
||||
/**
|
||||
* dwc3_hwparams - copy of HWPARAMS registers
|
||||
* @hwparams0 - GHWPARAMS0
|
||||
* @hwparams1 - GHWPARAMS1
|
||||
* @hwparams2 - GHWPARAMS2
|
||||
* @hwparams3 - GHWPARAMS3
|
||||
* @hwparams4 - GHWPARAMS4
|
||||
* @hwparams5 - GHWPARAMS5
|
||||
* @hwparams6 - GHWPARAMS6
|
||||
* @hwparams7 - GHWPARAMS7
|
||||
* @hwparams8 - GHWPARAMS8
|
||||
*/
|
||||
struct dwc3_hwparams {
|
||||
uint32_t hwparams0;
|
||||
uint32_t hwparams1;
|
||||
uint32_t hwparams2;
|
||||
uint32_t hwparams3;
|
||||
uint32_t hwparams4;
|
||||
uint32_t hwparams5;
|
||||
uint32_t hwparams6;
|
||||
uint32_t hwparams7;
|
||||
uint32_t hwparams8;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* HWPARAMS0 */
|
||||
#define DWC3_MODE(n) ((n) & 0x7)
|
||||
|
||||
#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
|
||||
|
||||
/* HWPARAMS1 */
|
||||
#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
|
||||
|
||||
/* HWPARAMS3 */
|
||||
#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
|
||||
#define DWC3_NUM_EPS_MASK (0x3f << 12)
|
||||
#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
|
||||
(DWC3_NUM_EPS_MASK)) >> 12)
|
||||
#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
|
||||
(DWC3_NUM_IN_EPS_MASK)) >> 18)
|
||||
|
||||
/* HWPARAMS7 */
|
||||
#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
|
||||
|
||||
struct dwc3_request {
|
||||
struct usb_request request;
|
||||
usb_slist_t list;
|
||||
struct dwc3_ep *dep;
|
||||
uint32_t start_slot;
|
||||
|
||||
uint8_t epnum;
|
||||
struct dwc3_trb *trb;
|
||||
uintptr_t trb_dma;
|
||||
|
||||
unsigned direction:1;
|
||||
unsigned mapped:1;
|
||||
unsigned queued:1;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* struct dwc3_scratchpad_array - hibernation scratchpad array
|
||||
* (format defined by hw)
|
||||
*/
|
||||
struct dwc3_scratchpad_array {
|
||||
/* dma_addr should be little end. */
|
||||
uintptr_t dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
|
||||
};
|
||||
|
||||
|
||||
struct dwc3 {
|
||||
struct usb_ctrlrequest *ctrl_req;
|
||||
struct dwc3_trb *ep0_trb;
|
||||
void *ep0_bounce;
|
||||
void *scratchbuf;
|
||||
uint8_t *setup_buf;
|
||||
uintptr_t ctrl_req_addr;
|
||||
uintptr_t ep0_trb_addr;
|
||||
uintptr_t ep0_bounce_addr;
|
||||
uintptr_t scratch_addr;
|
||||
struct dwc3_request ep0_usb_req;
|
||||
|
||||
/* device lock */
|
||||
usb_osal_mutex_t lock;
|
||||
|
||||
struct dwc3_event_buffer **ev_buffs;
|
||||
struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
|
||||
|
||||
struct usb_gadget gadget;
|
||||
struct usb_gadget_driver *gadget_driver;
|
||||
uintptr_t regs;
|
||||
uint32_t regs_size;
|
||||
enum dwc3_phy dr_mode;
|
||||
enum usb_phy_interface hsphy_mode;
|
||||
/* used for suspend/resume */
|
||||
uint32_t dcfg;
|
||||
uint32_t gctl;
|
||||
|
||||
uint32_t nr_scratch;
|
||||
uint32_t num_event_buffers;
|
||||
uint32_t u1u2;
|
||||
uint32_t maximum_speed;
|
||||
uint32_t revision;
|
||||
#define DWC3_REVISION_173A 0x5533173a
|
||||
#define DWC3_REVISION_175A 0x5533175a
|
||||
#define DWC3_REVISION_180A 0x5533180a
|
||||
#define DWC3_REVISION_183A 0x5533183a
|
||||
#define DWC3_REVISION_185A 0x5533185a
|
||||
#define DWC3_REVISION_187A 0x5533187a
|
||||
#define DWC3_REVISION_188A 0x5533188a
|
||||
#define DWC3_REVISION_190A 0x5533190a
|
||||
#define DWC3_REVISION_194A 0x5533194a
|
||||
#define DWC3_REVISION_200A 0x5533200a
|
||||
#define DWC3_REVISION_202A 0x5533202a
|
||||
#define DWC3_REVISION_210A 0x5533210a
|
||||
#define DWC3_REVISION_220A 0x5533220a
|
||||
#define DWC3_REVISION_230A 0x5533230a
|
||||
#define DWC3_REVISION_240A 0x5533240a
|
||||
#define DWC3_REVISION_250A 0x5533250a
|
||||
#define DWC3_REVISION_260A 0x5533260a
|
||||
#define DWC3_REVISION_270A 0x5533270a
|
||||
|
||||
enum dwc3_ep0_next ep0_next_event;
|
||||
enum dwc3_ep0_state ep0state;
|
||||
enum dwc3_link_state link_state;
|
||||
uint16_t isoch_delay;
|
||||
uint16_t u2sel;
|
||||
uint16_t u2pel;
|
||||
uint8_t u1sel;
|
||||
uint8_t u1pel;
|
||||
|
||||
uint8_t speed;
|
||||
|
||||
uint8_t num_out_eps;
|
||||
uint8_t num_in_eps;
|
||||
|
||||
void *mem;
|
||||
struct dwc3_hwparams hwparams;
|
||||
uint8_t test_mode;
|
||||
uint8_t test_mode_nr;
|
||||
uint8_t lpm_nyet_threshold;
|
||||
uint8_t hird_threshold;
|
||||
|
||||
uint32_t delayed_status:1;
|
||||
uint32_t ep0_bounced:1;
|
||||
uint32_t ep0_expect_in:1;
|
||||
uint32_t has_hibernation:1;
|
||||
uint32_t has_lpm_erratum:1;
|
||||
uint32_t is_utmi_l1_suspend:1;
|
||||
uint32_t is_selfpowered:1;
|
||||
uint32_t is_fpga:1;
|
||||
uint32_t needs_fifo_resize:1;
|
||||
uint32_t pullups_connected:1;
|
||||
uint32_t resize_fifos:1;
|
||||
uint32_t setup_packet_pending:1;
|
||||
uint32_t start_config_issued:1;
|
||||
uint32_t three_stage_setup:1;
|
||||
|
||||
uint32_t disable_scramble_quirk:1;
|
||||
uint32_t u2exit_lfps_quirk:1;
|
||||
uint32_t u2ss_inp3_quirk:1;
|
||||
uint32_t req_p1p2p3_quirk:1;
|
||||
uint32_t del_p1p2p3_quirk:1;
|
||||
uint32_t del_phy_power_chg_quirk:1;
|
||||
uint32_t lfps_filter_quirk:1;
|
||||
uint32_t rx_detect_poll_quirk:1;
|
||||
uint32_t dis_u3_susphy_quirk:1;
|
||||
uint32_t dis_u2_susphy_quirk:1;
|
||||
uint32_t dis_u1u2_quirk:1;
|
||||
uint32_t dis_enblslpm_quirk:1;
|
||||
uint32_t dis_u2_freeclk_exists_quirk:1;
|
||||
|
||||
uint32_t tx_de_emphasis_quirk:1;
|
||||
uint32_t tx_de_emphasis:2;
|
||||
uint32_t usb2_phyif_utmi_width:5;
|
||||
int index;
|
||||
usb_slist_t list;
|
||||
};
|
||||
|
||||
struct dwc3_event_type {
|
||||
uint32_t is_devspec:1;
|
||||
uint32_t type:7;
|
||||
uint32_t reserved8_31:24;
|
||||
} __packed;
|
||||
|
||||
#define DWC3_DEPEVT_XFERCOMPLETE 0x01
|
||||
#define DWC3_DEPEVT_XFERINPROGRESS 0x02
|
||||
#define DWC3_DEPEVT_XFERNOTREADY 0x03
|
||||
#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
|
||||
#define DWC3_DEPEVT_STREAMEVT 0x06
|
||||
#define DWC3_DEPEVT_EPCMDCMPLT 0x07
|
||||
|
||||
static inline const char *dwc3_ep_event_string(uint8_t event)
|
||||
{
|
||||
switch (event) {
|
||||
case DWC3_DEPEVT_XFERCOMPLETE:
|
||||
return "Transfer Complete";
|
||||
case DWC3_DEPEVT_XFERINPROGRESS:
|
||||
return "Transfer In-Progress";
|
||||
case DWC3_DEPEVT_XFERNOTREADY:
|
||||
return "Transfer Not Ready";
|
||||
case DWC3_DEPEVT_RXTXFIFOEVT:
|
||||
return "FIFO";
|
||||
case DWC3_DEPEVT_STREAMEVT:
|
||||
return "Stream";
|
||||
case DWC3_DEPEVT_EPCMDCMPLT:
|
||||
return "Endpoint Command Complete";
|
||||
}
|
||||
|
||||
return "UNKNOWN";
|
||||
}
|
||||
|
||||
struct dwc3_event_depevt {
|
||||
uint32_t one_bit:1;
|
||||
uint32_t endpoint_number:5;
|
||||
uint32_t endpoint_event:4;
|
||||
uint32_t reserved11_10:2;
|
||||
uint32_t status:4;
|
||||
|
||||
/* Within XferNotReady */
|
||||
#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
|
||||
|
||||
/* Within XferComplete */
|
||||
#define DEPEVT_STATUS_BUSERR (1 << 0)
|
||||
#define DEPEVT_STATUS_SHORT (1 << 1)
|
||||
#define DEPEVT_STATUS_IOC (1 << 2)
|
||||
#define DEPEVT_STATUS_LST (1 << 3)
|
||||
|
||||
/* Stream event only */
|
||||
#define DEPEVT_STREAMEVT_FOUND 1
|
||||
#define DEPEVT_STREAMEVT_NOTFOUND 2
|
||||
|
||||
/* Control-only Status */
|
||||
#define DEPEVT_STATUS_CONTROL_DATA 1
|
||||
#define DEPEVT_STATUS_CONTROL_STATUS 2
|
||||
|
||||
uint32_t parameters:16;
|
||||
} __packed;
|
||||
|
||||
|
||||
/**
|
||||
* struct dwc3_event_devt - Device Events
|
||||
* @one_bit: indicates this is a non-endpoint event (not used)
|
||||
* @device_event: indicates it's a device event. Should read as 0x00
|
||||
* @type: indicates the type of device event.
|
||||
* 0 - DisconnEvt
|
||||
* 1 - USBRst
|
||||
* 2 - ConnectDone
|
||||
* 3 - ULStChng
|
||||
* 4 - WkUpEvt
|
||||
* 5 - Reserved
|
||||
* 6 - EOPF
|
||||
* 7 - SOF
|
||||
* 8 - Reserved
|
||||
* 9 - ErrticErr
|
||||
* 10 - CmdCmplt
|
||||
* 11 - EvntOverflow
|
||||
* 12 - VndrDevTstRcved
|
||||
* @reserved15_12: Reserved, not used
|
||||
* @event_info: Information about this event
|
||||
* @reserved31_25: Reserved, not used
|
||||
*/
|
||||
struct dwc3_event_devt {
|
||||
uint32_t one_bit:1;
|
||||
uint32_t device_event:7;
|
||||
uint32_t type:4;
|
||||
uint32_t reserved15_12:4;
|
||||
uint32_t event_info:9;
|
||||
uint32_t reserved31_25:7;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* struct dwc3_event_gevt - Other Core Events
|
||||
* @one_bit: indicates this is a non-endpoint event (not used)
|
||||
* @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
|
||||
* @phy_port_number: self-explanatory
|
||||
* @reserved31_12: Reserved, not used.
|
||||
*/
|
||||
struct dwc3_event_gevt {
|
||||
uint32_t one_bit:1;
|
||||
uint32_t device_event:7;
|
||||
uint32_t phy_port_number:4;
|
||||
uint32_t reserved31_12:20;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* union dwc3_event - representation of Event Buffer contents
|
||||
* @raw: raw 32-bit event
|
||||
* @type: the type of the event
|
||||
* @depevt: Device Endpoint Event
|
||||
* @devt: Device Event
|
||||
* @gevt: Global Event
|
||||
*/
|
||||
union dwc3_event {
|
||||
uint32_t raw;
|
||||
struct dwc3_event_type type;
|
||||
struct dwc3_event_depevt depevt;
|
||||
struct dwc3_event_devt devt;
|
||||
struct dwc3_event_gevt gevt;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dwc3_gadget_ep_cmd_params - representation of endpoint command
|
||||
* parameters
|
||||
* @param2: third parameter
|
||||
* @param1: second parameter
|
||||
* @param0: first parameter
|
||||
*/
|
||||
struct dwc3_gadget_ep_cmd_params {
|
||||
uint32_t param2;
|
||||
uint32_t param1;
|
||||
uint32_t param0;
|
||||
};
|
||||
|
||||
/*
|
||||
* DWC3 Features to be used as Driver Data
|
||||
*/
|
||||
|
||||
#define DWC3_HAS_PERIPHERAL BIT(0)
|
||||
#define DWC3_HAS_XHCI BIT(1)
|
||||
#define DWC3_HAS_OTG BIT(3)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -102,7 +102,24 @@ struct usb_gadget {
|
|||
};
|
||||
|
||||
|
||||
struct usb_request {
|
||||
void *buf;
|
||||
unsigned length;
|
||||
uintptr_t dma;
|
||||
|
||||
unsigned stream_id:16;
|
||||
unsigned no_interrupt:1;
|
||||
unsigned zero:1;
|
||||
unsigned short_not_ok:1;
|
||||
|
||||
void (*complete)(struct usb_ep *ep,
|
||||
struct usb_request *req);
|
||||
void *context;
|
||||
usb_slist_t list;
|
||||
|
||||
int status;
|
||||
unsigned actual;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue