diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c index ccd9c5dac..f4fdeb357 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c @@ -284,7 +284,6 @@ #define GMAC_DESC3_LD (0x1 << 28) #define GMAC_DESC3_BUF1V (0x1 << 24) -#define DES3_ERROR_SUMMARY (1 << 15) #define DES3_ERROR_SUMMARY (1 << 15) /* Generic MII registers. */ @@ -1515,19 +1514,24 @@ void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC) */ HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *txDescs, - uint8_t *txBuff, uint32_t count) + struct GMAC_Desc *txDescs_dma, + uint8_t *txBuff, uint8_t *txBuff_dma, uint32_t count) { struct GMAC_Desc *desc; uint32_t i = 0; HAL_ASSERT(pGMAC != NULL); HAL_ASSERT(txDescs != NULL); + HAL_ASSERT(txDescs_dma != NULL); HAL_ASSERT(txBuff != NULL); + HAL_ASSERT(txBuff_dma != NULL); pGMAC->txDescIdx = 0; pGMAC->txDescs = txDescs; + pGMAC->txDescs_dma = txDescs_dma; pGMAC->txBuf = txBuff; + pGMAC->txBuf_dma = txBuff_dma; pGMAC->txSize = count; /* Fill each DMATxDesc descriptor with the right values */ @@ -1557,19 +1561,24 @@ HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, */ HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *rxDescs, - uint8_t *rxBuff, uint32_t count) + struct GMAC_Desc *rxDescs_dma, + uint8_t *rxBuff, uint8_t *rxBuff_dma, uint32_t count) { struct GMAC_Desc *desc; uint32_t i = 0; HAL_ASSERT(pGMAC != NULL); HAL_ASSERT(rxDescs != NULL); + HAL_ASSERT(rxDescs_dma != NULL); HAL_ASSERT(rxBuff != NULL); + HAL_ASSERT(rxBuff_dma != NULL); pGMAC->rxDescIdx = 0; pGMAC->rxDescs = rxDescs; + pGMAC->rxDescs_dma = rxDescs_dma; pGMAC->rxBuf = rxBuff; + pGMAC->rxBuf_dma = rxBuff_dma; pGMAC->rxSize = count; /* Fill each DMARxDesc descriptor with the right values */ @@ -1577,7 +1586,7 @@ HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, /* Get the pointer on the ith member of the Rx Desc list */ desc = rxDescs + i; - desc->des0 = (uint64_t)(rxBuff + i * HAL_GMAC_MAX_PACKET_SIZE); + desc->des0 = (uint32_t)(uint64_t)(rxBuff_dma + i * HAL_GMAC_MAX_PACKET_SIZE); desc->des1 = 0; desc->des2 = 0; desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC; @@ -1771,7 +1780,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) /* DMA init */ WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, DMA_SYSBUS_MODE_BLEN16 | - DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4); + DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4 | 1 << 12 | 1 << 14); /* Mask interrupts by writing to CSR7 */ WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, DMA_CHAN_INTR_DEFAULT_MASK); @@ -1787,9 +1796,9 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) value |= (rxFifosz << DMA_CH0_RX_CONTROL_RBSZ_SHIFT) & DMA_CH0_RX_CONTROL_RBSZ_MASK; value = value | (8 << DMA_CH0_RX_CONTROL_RXPBL_SHIFT); WRITE_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL, value); - WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_LIST_ADDRESS, (uint64_t)pGMAC->rxDescs); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_LIST_ADDRESS, (uint32_t)(uint64_t)pGMAC->rxDescs_dma); WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, - (uint64_t)(pGMAC->rxDescs + pGMAC->rxSize)); + (uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxSize)); /* init tx chan */ value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL); @@ -1797,8 +1806,8 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr) value |= DMA_CH0_TX_CONTROL_OSF; WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value); - WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_LIST_ADDRESS, (uint64_t)pGMAC->txDescs); - WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, (uint64_t)pGMAC->txDescs); + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_LIST_ADDRESS, (uint32_t)(uint64_t)pGMAC->txDescs_dma); + WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, (uint32_t)(uint64_t)pGMAC->txDescs_dma); HAL_GMAC_WriteHWAddr(pGMAC, addr); @@ -1935,6 +1944,12 @@ uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC) return pGMAC->txBuf + pGMAC->txDescIdx * HAL_GMAC_MAX_PACKET_SIZE; } +uint8_t *HAL_GMAC_GetTXBufferDMA(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->txBuf_dma + pGMAC->txDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} /** * @brief Get current RX buffer. * @param pGMAC: pointer to a GMAC_HANDLE structure that contains @@ -1949,6 +1964,13 @@ uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC) return pGMAC->rxBuf + pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE; } +uint8_t *HAL_GMAC_GetRXBufferDMA(struct GMAC_HANDLE *pGMAC) +{ + HAL_ASSERT(pGMAC != NULL); + + return pGMAC->rxBuf_dma + pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE; +} + /** * @brief Send a packet with the length, clean packet' dcached memory before send. * @param pGMAC: pointer to a GMAC_HANDLE structure that contains @@ -1977,8 +1999,8 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, pGMAC->txDescIdx++; pGMAC->txDescIdx %= pGMAC->txSize; - - desc->des0 = (uint64_t)packet; + + desc->des0 = (uint32_t)(uint64_t)packet; desc->des1 = 0; desc->des2 = length; /* @@ -1986,9 +2008,8 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, * writes to the rest of the descriptor too. */ desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_FD | GMAC_DESC3_LD; - WRITE_REG(pGMAC->pReg->DMA_CH0_TXDESC_TAIL_POINTER, - (uint64_t)(pGMAC->txDescs + pGMAC->txDescIdx)); + (uint32_t)(uint64_t)(pGMAC->txDescs_dma + pGMAC->txDescIdx)); for (i = 0; i < 1000000; i++) { if (!(desc->des3 & GMAC_DESC3_OWN)) { @@ -2025,6 +2046,7 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length) *length = 0; desc = pGMAC->rxDescs + pGMAC->rxDescIdx; + HAL_DBG("Rx at %p\n", desc->des0); des3 = desc->des3; if (des3 & GMAC_DESC3_OWN) { HAL_DBG("%s: RX packet not available\n", __func__); @@ -2072,18 +2094,22 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length) void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC) { struct GMAC_Desc *desc; + struct GMAC_Desc *desc_dma; HAL_ASSERT(pGMAC != NULL); /* Get the pointer on the ith member of the Tx Desc list */ desc = pGMAC->rxDescs + pGMAC->rxDescIdx; - desc->des0 = (uint64_t)(pGMAC->rxBuf + (pGMAC->rxDescIdx * + desc->des0 = (uint32_t)(uint64_t)(pGMAC->rxBuf_dma + (pGMAC->rxDescIdx * HAL_GMAC_MAX_PACKET_SIZE)); desc->des1 = 0; desc->des2 = 0; desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC; - WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, (uint64_t)desc); + HAL_DBG("Clean buff %p\n", desc->des0); + desc_dma = pGMAC->rxDescs_dma + pGMAC->rxDescIdx; + HAL_DBG("Clean desc %p\n", desc_dma); + WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, (uint32_t)(uint64_t)desc_dma); pGMAC->rxDescIdx++; pGMAC->rxDescIdx %= pGMAC->rxSize; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c index 12ba26179..35d9bb0fa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c @@ -6,7 +6,7 @@ #include "hal_bsp.h" #include "hal_base.h" #include "hal_gmac.h" - +#include "usyscall.h" #if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)) /*************************** GMAC DRIVER ****************************/ @@ -14,11 +14,6 @@ /***************************** MACRO Definition ******************************/ #define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') -#define CONFIG_SYS_NONCACHED_MEMORY (4 << 20) /* 4M */ - -/* 1MB granularity */ -#define MMU_SECTION_SIZE (1 << 20) - /***************************** Structure Definition **************************/ /***************************** Function Declare ******************************/ @@ -51,7 +46,7 @@ #define BMCR_RESET 0x8000 /* Reset to default state */ #define BMCR_SPEED10 0x0000 /* Select 10Mbps */ -#define GMAC_TEST_TIMES 1600 +#define GMAC_TEST_TIMES 16 /********************* Private Structure Definition **************************/ /* GMAC consumer config data. */ @@ -74,10 +69,14 @@ struct GMAC_ETH_CONFIG { int32_t rxDelay; struct GMAC_Desc *txDescs; + struct GMAC_Desc *txDescs_dma; struct GMAC_Desc *rxDescs; + struct GMAC_Desc *rxDescs_dma; uint8_t *txBuff; + uint8_t *txBuff_dma; uint8_t *rxBuff; + uint8_t *rxBuff_dma; /* MAC address info, hw address */ uint8_t macAddr[6]; @@ -85,20 +84,8 @@ struct GMAC_ETH_CONFIG { /********************* Private Variable Definition ***************************/ -static const unsigned long long os_no_cache_start = 0x2a00000000ULL; - -/* - * Reserve one MMU section worth of address space below the malloc() area that - * will be mapped uncached. - */ -static volatile unsigned long long noncached_start = 0x2a00000000ULL; -static volatile unsigned long long noncached_end = 0x2a00400000ULL; -static volatile unsigned long long noncached_next = 0x2a00000000ULL; - -static unsigned int m_nocachemem_inited = 0; - -static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +static uint8_t dstAddr[6] = { 0x00, 0x0C, 0x29, 0xf8, 0x7a, 0x6b }; #if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568) static struct GMAC_ETH_CONFIG ethConfigTable[] = @@ -111,31 +98,30 @@ static struct GMAC_ETH_CONFIG ethConfigTable[] = .extClk = false, - .resetGpioBank = GPIO2, - .resetGpioNum = GPIO_PIN_D3, + .resetGpioBank = GPIO3, + .resetGpioNum = GPIO_PIN_A4, .resetDelayMs = { 0, 20, 100 }, - .txDelay = 0x3C, - .rxDelay = 0x2f, + .txDelay = 0x2f, + .rxDelay = 0x00, }, -#ifdef HAL_GMAC1 - { - .halDev = &g_gmac1Dev, - .mode = PHY_INTERFACE_MODE_RGMII, - .maxSpeed = 1000, - .phyAddr = 1, - .extClk = false, + // { + // .halDev = &g_gmac1Dev, + // .mode = PHY_INTERFACE_MODE_RGMII, + // .maxSpeed = 1000, + // .phyAddr = 1, - .resetGpioBank = GPIO2, - .resetGpioNum = GPIO_PIN_D1, - .resetDelayMs = { 0, 20, 100 }, + // .extClk = false, - .txDelay = 0x4f, - .rxDelay = 0x26, - }, -#endif + // .resetGpioBank = GPIO4, + // .resetGpioNum = GPIO_PIN_B6, + // .resetDelayMs = { 0, 20, 100 }, + + // .txDelay = 0x4f, + // .rxDelay = 0x26, + // }, }; #endif @@ -264,15 +250,12 @@ static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config) static inline void NET_Random_ETHAddr(uint8_t *addr) { - unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff; - uint8_t i; - - for (i = 0; i < 6; i++) { - addr[i] = rand(); - } - - addr[0] &= 0xfe; /* clear multicast bit */ - addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + addr[0] = 0xe6; + addr[1] = 0x47; + addr[2] = 0xcd; + addr[3] = 0x20; + addr[4] = 0xcf; + addr[5] = 0xd9; } static inline void NET_Random_Package(uint8_t *addr, uint16_t len) @@ -296,7 +279,7 @@ static void PHY_Update_Links(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pG return; } - HAL_DelayMs(7000); + HAL_DelayMs(10000); status = HAL_GMAC_PHYUpdateLink(pGMAC); if (status == HAL_OK) { @@ -353,77 +336,42 @@ static HAL_Status GMAC_ETH_IRQ(struct GMAC_HANDLE *pGMAC) /* rt_interrupt_leave(); */ } -static HAL_Status noncached_init(void) -{ - unsigned long long start, end; - size_t size; - printf("noncached_start %#llX \n", os_no_cache_start); - if (os_no_cache_start <= 0) { - printf("Noncached_init failed, plase defined no cached memort\n"); - return -1; - } - start = HAL_GMAC_ALIGN(os_no_cache_start, 64); - printf("start %#llX \n", start); - size = HAL_GMAC_ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); - end = start + size; - printf("end %#llX \n", end); - - noncached_start = start; - printf("noncached_start %#X\n", noncached_start); - noncached_end = end; - noncached_next = start; - m_nocachemem_inited = 1; - printf("noncached_start %#X, noncached_end %#X, noncached_next %#X\n", noncached_start, noncached_end, noncached_next); - return 0; -} - -static unsigned long noncached_alloc(size_t size, size_t align) -{ - if (!m_nocachemem_inited) { - if (noncached_init()) - return (unsigned long)NULL; - } - - unsigned long next = HAL_GMAC_ALIGN(noncached_next, align); - - if (next >= noncached_end || (noncached_end - next) < size) { - return 0; - } - printf("noncached_start %#X, noncached_end %#X, noncached_next %#X\n", noncached_start, noncached_end, noncached_next); - noncached_next = next + size; - printf("noncached_start %#X, noncached_end %#X, noncached_next %#X\n", noncached_start, noncached_end, noncached_next); - return next; -} - -static void *malloc_align(size_t size, size_t align) +static void *malloc_align(size_t size, size_t align, uintptr_t va, uintptr_t *pa) { void *align_ptr; - void *ptr; + // void *ptr; size_t align_size; /* align the alignment size to 4 byte */ align = ((align + 0x03) & ~0x03); /* get total aligned size */ - align_size = ((size + 0x03) & ~0x03) + align; + align_size = ((size + 0x03) & ~0x03); /* allocate memory block from heap */ - ptr = malloc(align_size); - if (ptr != NULL) { - /* the allocated memory block is aligned */ - if (((uint64_t)ptr & (align - 1)) == 0) { - align_ptr = (void *)((uint64_t)ptr + align); - } else { - align_ptr = (void *)(((uint64_t)ptr + (align - 1)) & ~(align - 1)); - } + HAL_DBG("size: %d, align:%d\n",align_size, align); + // ptr = malloc(align_size); - /* set the pointer before alignment pointer to the real pointer */ - *((uint64_t *)((uint64_t)align_ptr - sizeof(void *))) = (uint64_t)ptr; - - ptr = align_ptr; + if (naive_mmap(&va, pa, align_size, true) < 0){ + HAL_DBG("Alloc failed\n"); } + // printf("%p,%p\n",(void *)va, *pa); + // void* ptr = (void *)va; + // if (ptr != 0) { + // /* the allocated memory block is aligned */ + // if (((uint64_t)ptr & (align - 1)) == 0) { + // align_ptr = (void *)((uint64_t)ptr + align); + // } else { + // align_ptr = (void *)(((uint64_t)ptr + (align - 1)) & ~(align - 1)); + // } - return ptr; + // /* set the pointer before alignment pointer to the real pointer */ + // *((uint64_t *)((uint64_t)align_ptr - sizeof(void *))) = (uint64_t)ptr; + + // ptr = align_ptr; + // } + + return (void *)va; } static void free_align(void *ptr) @@ -432,6 +380,7 @@ static void free_align(void *ptr) real_ptr = (void *)*(uint64_t *)((uint64_t)ptr - sizeof(void *)); free(real_ptr); + } /********************* Public Function Definition ****************************/ @@ -443,6 +392,7 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE HAL_Status status; if (!pGMAC->phyStatus.link) { + HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link); return -1; } @@ -452,6 +402,7 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE } ptr = (uint8_t *)HAL_GMAC_GetTXBuffer(pGMAC); + HAL_DBG("txPtr:%p\n", ptr); memcpy(ptr, dstAddr, 6); memcpy(ptr + 6, eth->macAddr, 6); ptr[12] = 0x40; @@ -466,14 +417,16 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE } /* dump packages */ - Dump_Hex("Tx", ptr, len); + // Dump_Hex("Tx", ptr, len); // HAL_DCACHE_CleanByRange((uint64_t)ptr, len); - status = HAL_GMAC_Send(pGMAC, ptr, len); + uint8_t * ptr_dma = (uint8_t *)HAL_GMAC_GetTXBufferDMA(pGMAC); + status = HAL_GMAC_Send(pGMAC, ptr_dma, len); if (status) { printf("GMAC send failed: %d\n", status); } - + + print_desc(pGMAC); return status; } @@ -484,12 +437,14 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC) int32_t size; if (!pGMAC->phyStatus.link) { + HAL_DBG("pGMAC->phyStatus.link: %d", pGMAC->phyStatus.link); return -1; } status = GMAC_ETH_IRQ(pGMAC); ptr = HAL_GMAC_Recv(pGMAC, &size); while (status && ptr) { + print_desc(pGMAC); if (size > 0 && ptr) { /* dump packages */ Dump_Hex("Rx", ptr, size); @@ -502,37 +457,59 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC) } ptr = HAL_GMAC_Recv(pGMAC, &size); } - return 0; } static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC) -{ - eth->rxDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_RX_SIZE, ARCH_DMA_MINALIGN); - eth->txDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_TX_SIZE, ARCH_DMA_MINALIGN); +{ + uintptr_t rx_va = 0x1000000000, rx_pa = 0; + if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){ + HAL_DBG("RX Desc alloc failed\n"); + } + eth->rxDescs = (struct GMAC_Desc *)0x1000000000; + eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa; - if (!eth->rxDescs || !eth->txDescs) - return -1; - printf("%x\n",eth->rxDescs); - printf("%x\n",eth->txDescs); - eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN); - eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN); + uintptr_t tx_va = 0x1000400000, tx_pa = 0; + if (naive_mmap(&tx_va, &tx_pa, GMAC_DESC_TX_SIZE, true) < 0){ + HAL_DBG("TX Desc alloc failed\n"); + } + eth->txDescs = (struct GMAC_Desc *)0x1000400000; + eth->txDescs_dma = (struct GMAC_Desc *)tx_pa; - if (!eth->rxBuff || !eth->txBuff) + if (!eth->rxDescs || !eth->txDescs_dma || + !eth->txDescs || !eth->txDescs_dma){ return -1; - printf("1\n"); + } + + HAL_DBG("rx:%p, %p\n",eth->rxDescs, eth->rxDescs_dma); + HAL_DBG("tx:%p, %p\n",eth->txDescs, eth->txDescs_dma); + + uintptr_t rxbuf_va = 0x1000800000, rxbuf_pa = 0; + uintptr_t txbuf_va = 0x1000C00000, txbuf_pa = 0; + eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa); + eth->rxBuff = (void *)0x1000800000; + eth->rxBuff_dma = (void *)rxbuf_pa; + eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN, txbuf_va, &txbuf_pa); + eth->txBuff = (void *)0x1000C00000; + eth->txBuff_dma = (void *)txbuf_pa; + + if (!eth->rxBuff || !eth->txBuff || + !eth->rxBuff_dma || !eth->txBuff_dma){ + return -1; + } + HAL_DBG("rx_buff:%p,%p\n",eth->rxBuff, eth->rxBuff_dma); + HAL_DBG("tx_buff:%p,%p,\n",eth->txBuff, eth->txBuff_dma); + HAL_DBG("GMAC_DESC_RX_SIZE:%d\n", GMAC_DESC_RX_SIZE); + HAL_DBG("GMAC_RX_BUFFER_SIZE:%d\n", GMAC_RX_BUFFER_SIZE); memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE); - printf("2\n"); memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE); - printf("3\n"); memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE); // HAL_DCACHE_InvalidateByRange((uint64_t)eth->rxBuff, GMAC_RX_BUFFER_SIZE); - printf("4\n"); memset(eth->txBuff, 0, GMAC_TX_BUFFER_SIZE); // HAL_DCACHE_CleanByRange((uint64_t)eth->txBuff, GMAC_TX_BUFFER_SIZE); - HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxBuff, GMAC_DESCRIPTORS_RX); - HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txBuff, GMAC_DESCRIPTORS_TX); + HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxDescs_dma, eth->rxBuff, eth->rxBuff_dma, GMAC_DESCRIPTORS_RX); + HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txDescs_dma, eth->txBuff, eth->txBuff_dma, GMAC_DESCRIPTORS_TX); print_desc(pGMAC); @@ -606,6 +583,7 @@ static void GMAC0_Iomux_Config(void) GPIO_PIN_B6, /* gmac0_rxd0 */ PIN_CONFIG_MUX_FUNC1); HAL_PINCTRL_SetIOMUX(GPIO_BANK2, + GPIO_PIN_C0 | ///* eth0_refclko25m */ GPIO_PIN_C3 | /* gmac0_mdc */ GPIO_PIN_C4 | /* gmac0_mdio */ GPIO_PIN_C0 | /* gmac0_rxdvcrs */ @@ -630,16 +608,6 @@ static void GMAC0_Iomux_Config(void) GPIO_PIN_B0, PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL1); -#if 0 - /* io-domian: 1.8v or 3.3v for vccio4 */ - WRITE_REG_MASK_WE(GRF->IO_VSEL0, - GRF_IO_VSEL0_POC_VCCIO4_SEL18_MASK, - (1 << GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT)); - - WRITE_REG_MASK_WE(GRF->IO_VSEL1, - GRF_IO_VSEL1_POC_VCCIO4_SEL33_MASK, - (0 << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT)); -#endif } #endif @@ -658,7 +626,6 @@ static void GMAC_Iomux_Config(uint8_t id) #include "usyscall.h" - // IPC_SERVER_INTERFACE(Ipc_intr, 1); // IPC_SERVER_REGISTER_INTERFACES(IpIntrHandler, 1, Ipc_intr); @@ -680,22 +647,27 @@ int main() { return -1; } HAL_DBG("map GMAC0\n"); - if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 65536, true)) { + if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 0x10000, true)) { printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0); exit(1); } HAL_DBG("map GPIO2\n"); - if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 65536, true)) { + if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 0x10000, true)) { + printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2); + exit(1); + } + HAL_DBG("map GPIO3\n"); + if (!mmap(0x2000000000ULL + GPIO3_BASE, GPIO3_BASE, 0x10000, true)) { printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2); exit(1); } - if (!mmap(0x2000000000ULL + GRF_BASE, GRF_BASE, 327680, true)) { + if (!mmap(0x2000000000ULL + GRF_BASE, GRF_BASE, 0x50000, true)) { printf("eth_hal: mmap GRF(%8x) failed\n", GRF); exit(1); } - if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 65535, true)) { + if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 0x10000, true)) { printf("eth_hal: mmap GRF(%8x) failed\n", GRF); exit(1); } @@ -703,10 +675,11 @@ int main() { printf("eth_hal: mmap GRF(%8x) failed\n", GRF); exit(1); } - if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 65535, true)) { + if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 0x10000, true)) { printf("eth_hal: mmap GRF(%8x) failed\n", GRF); exit(1); } + HAL_DBG("config iomux\n"); /* ionmux */ GMAC_Iomux_Config(bus); @@ -730,35 +703,40 @@ int main() { /* Enable GMAC and DMA transmission and reception */ HAL_DBG("start gmac\n"); HAL_GMAC_Start(pGMAC, eth->macAddr); - + // print_desc(pGMAC); /* Update links information */ HAL_DBG("phy update link\n"); PHY_Update_Links(eth, pGMAC, bus); + // print_desc(pGMAC); /* Dump MAC Regs */ Dump_Regs(pGMAC); /* Dump PHY Regs */ - PHY_Dump(eth, pGMAC); - + // PHY_Dump(eth, pGMAC); + HAL_DBG("Init Down\n"); for (i = 0; i < GMAC_TEST_TIMES; i++) { + HAL_DBG("TEST Send %d\n", i); /* GMAC Send 64 bytes */ - GMAC_Send_Test(eth, pGMAC, 64); + // GMAC_Send_Test(eth, pGMAC, 64); /* GMAC Send 1500 bytes */ GMAC_Send_Test(eth, pGMAC, 1500); HAL_DelayMs(1000); - + HAL_DBG("TEST Recv %d\n", i); /* GMAC Recv */ GMAC_Recv_Test(pGMAC); } - + Dump_Regs(pGMAC); HAL_CRU_ClkDisable(eth->halDev->pclkGateID); HAL_CRU_ClkDisable(eth->halDev->clkGateID); - free_align(eth->txBuff); - free_align(eth->rxBuff); + // free_align(eth->txBuff); + // free_align(eth->rxBuff); + HAL_DBG("done\n"); } + exit(0); return 0; } + // typedef void (*isr_handler_t)(int vector, void *param); // typedef void (*NVIC_IRQHandler)(void); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h index 66eca849e..5f6c731e4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h @@ -207,10 +207,10 @@ struct GMAC_Link { * @brief GMAC DMA Descriptors Data Structure Definition */ struct GMAC_Desc { - uint64_t des0; /**< DMA Descriptors first word */ - uint64_t des1; /**< DMA Descriptors second word */ - uint64_t des2; /**< DMA Descriptors third word */ - uint64_t des3; /**< DMA Descriptors four word */ + uint32_t des0; /**< DMA Descriptors first word */ + uint32_t des1; /**< DMA Descriptors second word */ + uint32_t des2; /**< DMA Descriptors third word */ + uint32_t des3; /**< DMA Descriptors four word */ }; /** @@ -269,9 +269,13 @@ struct GMAC_HANDLE { struct GMAC_DMAStats extraStatus; /**< GMAC DMA transfer status */ struct GMAC_Desc *rxDescs; /**< First Rx descriptor pointer */ + struct GMAC_Desc *rxDescs_dma; struct GMAC_Desc *txDescs; /**< First Tx descriptor pointer */ + struct GMAC_Desc *txDescs_dma; uint8_t *txBuf; /**< First Tx buffer pointer */ + uint8_t *txBuf_dma; uint8_t *rxBuf; /**< First Tx buffer pointer */ + uint8_t *rxBuf_dma; uint32_t txDescIdx; /**< Current Tx descriptor index */ uint32_t rxDescIdx; /**< Current Rx descriptor pointer */ uint32_t txSize; /**< Tx descriptor size*/ @@ -307,17 +311,21 @@ void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC); void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC); HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *txDescs, - uint8_t *txBuff, uint32_t txBuffCount); + struct GMAC_Desc *txDescs_dma, + uint8_t *txBuff, uint8_t *txBuff_dma, uint32_t txBuffCount); HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC, struct GMAC_Desc *rxDescs, - uint8_t *rxBuff, uint32_t rxBuffCount); + struct GMAC_Desc *rxDescs_dma, + uint8_t *rxBuff, uint8_t *rxBuff_dma, uint32_t rxBuffCount); eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC); HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay, int32_t rxDelay); uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC); uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC); uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetTXBufferDMA(struct GMAC_HANDLE *pGMAC); uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC); +uint8_t *HAL_GMAC_GetRXBufferDMA(struct GMAC_HANDLE *pGMAC); HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet, uint32_t length); uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h index 86e449ff1..09e399c20 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/3568/include/rk3568.h @@ -1287,7 +1287,7 @@ struct INTMUX_REG { #define SARADC ((struct SARADC_REG *) SARADC_BASE) #define GPIO1 ((struct GPIO_REG *) GPIO1_BASE) #define GPIO2 ((struct GPIO_REG *) (GPIO2_BASE + 0x2000000000ULL)) -#define GPIO3 ((struct GPIO_REG *) GPIO3_BASE) +#define GPIO3 ((struct GPIO_REG *) (GPIO3_BASE + 0x2000000000ULL)) #define GPIO4 ((struct GPIO_REG *) GPIO4_BASE) #define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) #define INTMUX ((struct INTMUX_REG *) INTMUX_BASE) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c index 9e1779fc6..f9501b6f8 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_level3.c @@ -93,7 +93,6 @@ void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) for (uintptr_t l3_entry_idx = 0; l3_entry_idx < NUM_LEVEL3_PDE; l3_entry_idx++) { uintptr_t* l4_table_paddr = (uintptr_t*)LEVEL4_PTE_ADDR(l3_table_vaddr[l3_entry_idx]); if (l4_table_paddr != NULL) { - uintptr_t* l4_table_vaddr = P2V(l4_table_paddr); kfree(P2V(l4_table_paddr)); } }