diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c index c985ca48f..387f953dc 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c @@ -323,7 +323,7 @@ const struct HAL_CANFD_DEV g_can2Dev = #ifdef HAL_GMAC_MODULE_ENABLED const struct HAL_GMAC_DEV g_gmac0Dev = { - .pReg = GMAC0, + .pReg = GMAC0_VADDR, .clkID = CLK_MAC0_2TOP, .clkGateID = CLK_MAC0_2TOP_GATE, .pclkID = PCLK_PHP, diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c index 8a48a630c..c685a6149 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c @@ -956,268 +956,6 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) } #endif -#ifdef CRU_CLK_USE_CON_BANK -static const struct HAL_CRU_DEV *CRU_GetInfo(void) -{ - return &g_cruDev; -} - -HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - HAL_Check ret; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - ret = (HAL_Check)(!((CRU_READ(reg) & (1 << shift)) >> shift)); - - return ret; -} - -HAL_Status HAL_CRU_ClkEnable(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 0U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkDisable(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 1U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t reg; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; - CRU_WRITE(reg, 0, 0, val); - - return HAL_OK; -} - -HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); - uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - HAL_Check ret; - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - ret = (HAL_Check)((CRU_READ(reg) & (1 << shift)) >> shift); - - return ret; -} - -HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); - uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - HAL_ASSERT(shift < 16); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 1U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); - uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); - uint32_t bank = CLK_GATE_GET_REG_BANK(clk); - uint32_t reg; - - HAL_ASSERT(shift < 16); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, shift, 1U << shift, 0U); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); - uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]); - uint32_t val = 0; - uint32_t reg; - int i; - - for (i = 0; i < numClks; i++) { - val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); - if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { - return HAL_ERROR; - } - } - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, 0, val, val); - HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]); - uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]); - uint32_t val = 0; - uint32_t reg; - int i; - - for (i = 0; i < numClks; i++) { - val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i])); - if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) { - return HAL_ERROR; - } - } - - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; - CRU_WRITE(reg, 0, val, 0); - HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index; - uint32_t reg, bank; - - index = CLK_DIV_GET_REG_OFFSET(divName); - shift = CLK_DIV_GET_BITS_SHIFT(divName); - HAL_ASSERT(shift < 16); - mask = CLK_DIV_GET_MASK(divName); - if (divValue > mask) { - divValue = mask; - } - - bank = CLK_DIV_GET_BANK(divName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - CRU_WRITE(reg, shift, mask, (divValue - 1U)); - - return HAL_OK; -} - -uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index, divValue; - uint32_t reg, bank; - - index = CLK_DIV_GET_REG_OFFSET(divName); - shift = CLK_DIV_GET_BITS_SHIFT(divName); - HAL_ASSERT(shift < 16); - mask = CLK_DIV_GET_MASK(divName); - bank = CLK_DIV_GET_BANK(divName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - divValue = ((CRU_READ(reg) & mask) >> shift) + 1; - - return divValue; -} - -HAL_SECTION_SRAM_CODE -HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index; - uint32_t reg, bank; - - index = CLK_MUX_GET_REG_OFFSET(muxName); - shift = CLK_MUX_GET_BITS_SHIFT(muxName); - HAL_ASSERT(shift < 16); - mask = CLK_MUX_GET_MASK(muxName); - bank = CLK_MUX_GET_BANK(muxName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - CRU_WRITE(reg, shift, mask, muxValue); - - return HAL_OK; -} - -HAL_SECTION_SRAM_CODE -uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t shift, mask, index, muxValue; - uint32_t reg, bank; - - index = CLK_MUX_GET_REG_OFFSET(muxName); - shift = CLK_MUX_GET_BITS_SHIFT(muxName); - HAL_ASSERT(shift < 16); - mask = CLK_MUX_GET_MASK(muxName); - bank = CLK_MUX_GET_BANK(muxName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - muxValue = ((CRU_READ(reg) & mask) >> shift); - - return muxValue; -} - -HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, - uint32_t numerator, - uint32_t denominator) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t reg, bank; - uint32_t index; - - index = CLK_DIV_GET_REG_OFFSET(fracDivName); - bank = CLK_DIV_GET_BANK(fracDivName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - CRU_WRITE(reg, 0, 0, ((numerator << 16) | denominator)); - - return HAL_OK; -} - -HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, - uint32_t *numerator, - uint32_t *denominator) -{ - const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); - uint32_t reg, bank; - uint32_t index; - uint32_t val; - - index = CLK_DIV_GET_REG_OFFSET(fracDivName); - bank = CLK_DIV_GET_BANK(fracDivName); - reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; - val = CRU_READ(reg); - - *numerator = (val & 0xffff0000) >> 16; - *denominator = (val & 0x0000ffff); - - return HAL_OK; -} -#else /* CRU_CLK_USE_CON_BANK */ - HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) { uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); @@ -1575,7 +1313,7 @@ HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, return HAL_OK; } -#endif /* CRU_CLK_USE_CON_BANK */ + HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, uint32_t *numerator, diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c index 740b49e30..e0ee79d88 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c @@ -84,11 +84,9 @@ struct GMAC_ETH_CONFIG { }; /********************* Private Variable Definition ***************************/ -#ifdef NC_MEM_BASE -static const unsigned long os_no_cache_start = (unsigned long)NC_MEM_BASE; -#else + static const unsigned long os_no_cache_start = 0; -#endif + /* * Reserve one MMU section worth of address space below the malloc() area that @@ -113,7 +111,7 @@ static struct GMAC_ETH_CONFIG ethConfigTable[] = .extClk = false, - .resetGpioBank = GPIO2, + .resetGpioBank = GPIO2_VADDR, .resetGpioNum = GPIO_PIN_D3, .resetDelayMs = { 0, 20, 100 }, @@ -223,31 +221,6 @@ static void Dump_Regs(struct GMAC_HANDLE *pGMAC) } } -static void PHY_Read(struct GMAC_HANDLE *pGMAC, uint32_t phyReg) -{ - int data; - - data = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyConfig.phyAddress, phyReg); - if (data >= 0) { - printf("PHY_Read: %02lX --> %08X\n", phyReg, data); - } else { - printf("PHY_Read: %02lX --> faild\n", phyReg); - } -} - -static void PHY_Write(struct GMAC_HANDLE *pGMAC, uint32_t phyReg, uint32_t data) -{ - // struct GMAC_HANDLE *pGMAC; - int status; - - status = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyConfig.phyAddress, phyReg, data); - if (!status) { - printf("PHY_Write: %02lX --> %08lX\n", phyReg, data); - } else { - printf("PHY_Write: %02lX --> faild\n", phyReg); - } -} - static void PHY_Dump(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC) { int data, i; @@ -682,12 +655,14 @@ static void GMAC_Iomux_Config(uint8_t id) } - - - - /*************************** GMAC TEST MAIN ****************************/ +#include "usyscall.h" + + +// IPC_SERVER_INTERFACE(Ipc_intr, 1); +// IPC_SERVER_REGISTER_INTERFACES(IpIntrHandler, 1, Ipc_intr); + int main() { struct GMAC_ETH_CONFIG *eth; struct GMAC_HANDLE *pGMAC; @@ -707,6 +682,16 @@ int main() { return -1; } + if (!mmap(0x1000000000U + GMAC0_BASE, GMAC0_BASE, 4096, true)) { + printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0); + exit(1); + } + + if (!mmap(0x2000000000U + GPIO2_BASE, GPIO2_BASE, 4096, true)) { + printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2); + exit(1); + } + /* ionmux */ GMAC_Iomux_Config(bus); @@ -714,7 +699,7 @@ int main() { HAL_CRU_ClkEnable(eth->halDev->clkGateID); /* Register irq */ - + // register_irq(eth->halDev->irqNum, ); /* PHY reset */ GMAC_PHY_Reset(eth); @@ -754,3 +739,16 @@ int main() { return 0; } +// typedef void (*isr_handler_t)(int vector, void *param); +// typedef void (*NVIC_IRQHandler)(void); + +// isr_handler_t interrupt_install(int vector, +// isr_handler_t handler, +// void *param, +// const char *name) +// { + +// HAL_NVIC_SetIRQHandler(vector, (NVIC_IRQHandler)handler); +// return handler; +// } + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h index e131a5a08..c21b152fe 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h @@ -18,6 +18,8 @@ #include "hal_driver.h" #include "hal_debug.h" +#define GMAC0_VADDR ((struct GMAC_REG *)(0x1000000000U + GMAC0_BASE)) +#define GPIO2_VADDR ((struct GPIO_REG *)(0x2000000000U + GPIO2_BASE)) /***************************** MACRO Definition ******************************/ /** @defgroup HAL_BASE_Exported_Definition_Group1 Basic Definition diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h index c7fbfb38c..66eca849e 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h @@ -207,10 +207,10 @@ struct GMAC_Link { * @brief GMAC DMA Descriptors Data Structure Definition */ struct GMAC_Desc { - uint32_t des0; /**< DMA Descriptors first word */ - uint32_t des1; /**< DMA Descriptors second word */ - uint32_t des2; /**< DMA Descriptors third word */ - uint32_t des3; /**< DMA Descriptors four word */ + uint64_t des0; /**< DMA Descriptors first word */ + uint64_t des1; /**< DMA Descriptors second word */ + uint64_t des2; /**< DMA Descriptors third word */ + uint64_t des3; /**< DMA Descriptors four word */ }; /**