35 lines
2.3 KiB
XML
35 lines
2.3 KiB
XML
<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
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<FileList>
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<File path="src/ipdefs/gowin_dpb_32x8k/gowin_dpb_32x8k.v" type="file.verilog" enable="1"/>
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<File path="src/ipdefs/gowin_dpb_8x4k/gowin_dpb_8x4k.v" type="file.verilog" enable="1"/>
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<File path="src/ipdefs/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_clint.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_csr.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_exu.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_exu_div.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_exu_mul.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_idu.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_mau.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_pcgen.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_rtu.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_top.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/core/pa_core_xreg.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/pa_chip_param.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/pa_chip_top.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/perips/pa_perips_gpio.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/perips/pa_perips_tcm.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/perips/pa_perips_tcm2.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/perips/pa_perips_timer.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/perips/pa_perips_uart.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/soc/pa_soc_rbm.v" type="file.verilog" enable="1"/>
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<File path="src/rtl/utils/pa_dff.v" type="file.verilog" enable="1"/>
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<File path="src/fpga_project.cst" type="file.cst" enable="1"/>
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<File path="src/fpga_project.sdc" type="file.sdc" enable="1"/>
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</FileList>
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</Project>
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