180 lines
3.3 KiB
ArmAsm
180 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2020-2021, SERI Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-29 Lyons first version
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*/
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.section .text
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.global interrupt_enable
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.align 2
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interrupt_disable:
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csrrci a0, mstatus, 8
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ret
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.global interrupt_disable
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.align 2
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interrupt_enable:
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csrw mstatus, a0
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ret
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/* Macro for saving task context */
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.macro save_context
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addi sp, sp, -32*4
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sw x1, 1*4(sp)
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csrr x1, mepc
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sw x1, 0*4(sp)
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li x1, 0x0088
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sw x1, 2*4(sp)
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sw x4, 4*4(sp)
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sw x5, 5*4(sp)
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sw x6, 6*4(sp)
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sw x7, 7*4(sp)
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sw x8, 8*4(sp)
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sw x9, 9*4(sp)
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sw x10, 10*4(sp)
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sw x11, 11*4(sp)
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sw x12, 12*4(sp)
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sw x13, 13*4(sp)
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sw x14, 14*4(sp)
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sw x15, 15*4(sp)
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sw x16, 16*4(sp)
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sw x17, 17*4(sp)
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sw x18, 18*4(sp)
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sw x19, 19*4(sp)
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sw x20, 20*4(sp)
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sw x21, 21*4(sp)
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sw x22, 22*4(sp)
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sw x23, 23*4(sp)
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sw x24, 24*4(sp)
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sw x25, 25*4(sp)
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sw x26, 26*4(sp)
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sw x27, 27*4(sp)
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sw x28, 28*4(sp)
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sw x29, 29*4(sp)
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sw x30, 30*4(sp)
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sw x31, 31*4(sp)
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.endm
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/* Macro for restoring task context */
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.macro restore_context
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lw x1, 0*4(sp)
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csrw mepc, x1
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lw x1, 1*4(sp)
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li t0, 0x1800
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csrw mstatus, t0
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lw t0, 2*4(sp)
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csrs mstatus, t0
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lw x4, 4*4(sp)
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lw x5, 5*4(sp)
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lw x6, 6*4(sp)
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lw x7, 7*4(sp)
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lw x8, 8*4(sp)
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lw x9, 9*4(sp)
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lw x10, 10*4(sp)
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lw x11, 11*4(sp)
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lw x12, 12*4(sp)
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lw x13, 13*4(sp)
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lw x14, 14*4(sp)
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lw x15, 15*4(sp)
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lw x16, 16*4(sp)
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lw x17, 17*4(sp)
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lw x18, 18*4(sp)
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lw x19, 19*4(sp)
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lw x20, 20*4(sp)
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lw x21, 21*4(sp)
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lw x22, 22*4(sp)
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lw x23, 23*4(sp)
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lw x24, 24*4(sp)
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lw x25, 25*4(sp)
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lw x26, 26*4(sp)
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lw x27, 27*4(sp)
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lw x28, 28*4(sp)
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lw x29, 29*4(sp)
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lw x30, 30*4(sp)
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lw x31, 31*4(sp)
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addi sp, sp, 32*4
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.endm
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.global trap_entry
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.align 2
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trap_entry:
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j vector_handler
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vector_handler:
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_save:
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save_context
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#ifdef OS_ENABLE_RT_THREAD
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la t0, rt_interrupt_nest
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li t1, 1
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sb t1, 0(t0)
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#endif
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csrr a0, mcause
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csrr a1, mepc
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srli t0, a0, 31
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beq t0, a0, _is_exception
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csrw mscratch, sp
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mv sp, gp
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call trap_handler
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csrr sp, mscratch
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j _is_interrupt
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_is_exception:
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addi a1, a1, 4
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csrw mepc, a1
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_is_interrupt:
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#ifdef OS_ENABLE_RT_THREAD
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la s0, rt_thread_switch_interrupt_flag
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lw s2, 0(s0)
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beqz s2, _restore
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sw zero, 0(s0)
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la s0, rt_interrupt_from_thread
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lw s1, 0(s0)
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sw sp, 0(s1)
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la s0, rt_interrupt_to_thread
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lw s1, 0(s0)
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lw sp, 0(s1)
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#endif
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_restore:
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#ifdef OS_ENABLE_RT_THREAD
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la t0, rt_interrupt_nest
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sb zero, 0(t0)
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#endif
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restore_context
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mret
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_nop_list:
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nop
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nop
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nop
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.weak trap_handler
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trap_handler:
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ret
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