dc40bc7368
Further fixes on top of 9e2f316ed. Writing some doco for gcc on
inline assembly woke me up to some more errors.
- dgemv_kernel_4x4 asm did not mention *ap as a memory input, and
*y is both read and write.
- sasum_kernel_32 and casum_kernel_16 did not use %x for a vsx insn
operand, a problem if the "=f" sum output was ever allocated a vsx
reg in the altivec set. This might be possible with inlining and
future gcc optimisation.
300 lines
8.8 KiB
C
300 lines
8.8 KiB
C
/***************************************************************************
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Copyright (c) 2013-2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2016/03/30 Werner Saar (wernsaar@googlemail.com)
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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* LAPACK-TEST : OK
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**************************************************************************************/
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#define HAVE_KERNEL_4x4 1
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static void dgemv_kernel_4x4 (long n, double *ap, long lda, double *x, double *y, double alpha)
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{
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double *a0;
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double *a1;
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double *a2;
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double *a3;
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__asm__
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(
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"lxvd2x 34, 0, %10 \n\t" // x0, x1
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"lxvd2x 35, %11, %10 \n\t" // x2, x3
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"xxspltd 32, %x9, 0 \n\t" // alpha, alpha
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"sldi %6, %13, 3 \n\t" // lda * sizeof (double)
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"xvmuldp 34, 34, 32 \n\t" // x0 * alpha, x1 * alpha
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"xvmuldp 35, 35, 32 \n\t" // x2 * alpha, x3 * alpha
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"add %4, %3, %6 \n\t" // a0 = ap, a1 = a0 + lda
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"add %6, %6, %6 \n\t" // 2 * lda
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"xxspltd 32, 34, 0 \n\t" // x0 * alpha, x0 * alpha
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"xxspltd 33, 34, 1 \n\t" // x1 * alpha, x1 * alpha
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"xxspltd 34, 35, 0 \n\t" // x2 * alpha, x2 * alpha
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"xxspltd 35, 35, 1 \n\t" // x3 * alpha, x3 * alpha
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"add %5, %3, %6 \n\t" // a2 = a0 + 2 * lda
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"add %6, %4, %6 \n\t" // a3 = a1 + 2 * lda
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"dcbt 0, %3 \n\t"
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"dcbt 0, %4 \n\t"
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"dcbt 0, %5 \n\t"
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"dcbt 0, %6 \n\t"
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"lxvd2x 40, 0, %3 \n\t" // a0[0], a0[1]
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"lxvd2x 41, %11, %3 \n\t" // a0[2], a0[3]
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"lxvd2x 42, 0, %4 \n\t" // a1[0], a1[1]
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"lxvd2x 43, %11, %4 \n\t" // a1[2], a1[3]
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"lxvd2x 44, 0, %5 \n\t" // a2[0], a2[1]
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"lxvd2x 45, %11, %5 \n\t" // a2[2], a2[3]
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"lxvd2x 46, 0, %6 \n\t" // a3[0], a3[1]
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"lxvd2x 47, %11, %6 \n\t" // a3[2], a3[3]
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"dcbt 0, %2 \n\t"
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"addi %3, %3, 32 \n\t"
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"addi %4, %4, 32 \n\t"
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"addi %5, %5, 32 \n\t"
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"addi %6, %6, 32 \n\t"
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"addic. %1, %1, -4 \n\t"
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"ble 2f \n\t"
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".p2align 5 \n"
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"1: \n\t"
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"lxvd2x 36, 0, %2 \n\t" // y0, y1
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"lxvd2x 37, %11, %2 \n\t" // y2, y3
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"xvmaddadp 36, 40, 32 \n\t"
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"xvmaddadp 37, 41, 32 \n\t"
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"lxvd2x 40, 0, %3 \n\t" // a0[0], a0[1]
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"lxvd2x 41, %11, %3 \n\t" // a0[2], a0[3]
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"xvmaddadp 36, 42, 33 \n\t"
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"addi %3, %3, 32 \n\t"
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"xvmaddadp 37, 43, 33 \n\t"
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"lxvd2x 42, 0, %4 \n\t" // a1[0], a1[1]
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"lxvd2x 43, %11, %4 \n\t" // a1[2], a1[3]
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"xvmaddadp 36, 44, 34 \n\t"
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"addi %4, %4, 32 \n\t"
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"xvmaddadp 37, 45, 34 \n\t"
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"lxvd2x 44, 0, %5 \n\t" // a2[0], a2[1]
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"lxvd2x 45, %11, %5 \n\t" // a2[2], a2[3]
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"xvmaddadp 36, 46, 35 \n\t"
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"addi %5, %5, 32 \n\t"
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"xvmaddadp 37, 47, 35 \n\t"
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"stxvd2x 36, 0, %2 \n\t" // y0, y1
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"stxvd2x 37, %11, %2 \n\t" // y2, y3
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"lxvd2x 46, 0, %6 \n\t" // a3[0], a3[1]
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"lxvd2x 47, %11, %6 \n\t" // a3[2], a3[3]
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"addi %6, %6, 32 \n\t"
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"addi %2, %2, 32 \n\t"
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"addic. %1, %1, -4 \n\t"
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"ble 2f \n\t"
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"lxvd2x 36, 0, %2 \n\t" // y0, y1
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"lxvd2x 37, %11, %2 \n\t" // y2, y3
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"xvmaddadp 36, 40, 32 \n\t"
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"xvmaddadp 37, 41, 32 \n\t"
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"lxvd2x 40, 0, %3 \n\t" // a0[0], a0[1]
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"lxvd2x 41, %11, %3 \n\t" // a0[2], a0[3]
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"xvmaddadp 36, 42, 33 \n\t"
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"addi %3, %3, 32 \n\t"
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"xvmaddadp 37, 43, 33 \n\t"
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"lxvd2x 42, 0, %4 \n\t" // a1[0], a1[1]
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"lxvd2x 43, %11, %4 \n\t" // a1[2], a1[3]
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"xvmaddadp 36, 44, 34 \n\t"
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"addi %4, %4, 32 \n\t"
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"xvmaddadp 37, 45, 34 \n\t"
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"lxvd2x 44, 0, %5 \n\t" // a2[0], a2[1]
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"lxvd2x 45, %11, %5 \n\t" // a2[2], a2[3]
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"xvmaddadp 36, 46, 35 \n\t"
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"addi %5, %5, 32 \n\t"
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"xvmaddadp 37, 47, 35 \n\t"
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"stxvd2x 36, 0, %2 \n\t" // y0, y1
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"stxvd2x 37, %11, %2 \n\t" // y2, y3
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"lxvd2x 46, 0, %6 \n\t" // a3[0], a3[1]
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"lxvd2x 47, %11, %6 \n\t" // a3[2], a3[3]
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"addi %6, %6, 32 \n\t"
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"addi %2, %2, 32 \n\t"
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"addic. %1, %1, -4 \n\t"
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"ble 2f \n\t"
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"lxvd2x 36, 0, %2 \n\t" // y0, y1
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"lxvd2x 37, %11, %2 \n\t" // y2, y3
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"xvmaddadp 36, 40, 32 \n\t"
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"xvmaddadp 37, 41, 32 \n\t"
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"lxvd2x 40, 0, %3 \n\t" // a0[0], a0[1]
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"lxvd2x 41, %11, %3 \n\t" // a0[2], a0[3]
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"xvmaddadp 36, 42, 33 \n\t"
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"addi %3, %3, 32 \n\t"
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"xvmaddadp 37, 43, 33 \n\t"
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"lxvd2x 42, 0, %4 \n\t" // a1[0], a1[1]
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"lxvd2x 43, %11, %4 \n\t" // a1[2], a1[3]
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"xvmaddadp 36, 44, 34 \n\t"
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"addi %4, %4, 32 \n\t"
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"xvmaddadp 37, 45, 34 \n\t"
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"lxvd2x 44, 0, %5 \n\t" // a2[0], a2[1]
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"lxvd2x 45, %11, %5 \n\t" // a2[2], a2[3]
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"xvmaddadp 36, 46, 35 \n\t"
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"addi %5, %5, 32 \n\t"
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"xvmaddadp 37, 47, 35 \n\t"
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"stxvd2x 36, 0, %2 \n\t" // y0, y1
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"stxvd2x 37, %11, %2 \n\t" // y2, y3
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"lxvd2x 46, 0, %6 \n\t" // a3[0], a3[1]
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"lxvd2x 47, %11, %6 \n\t" // a3[2], a3[3]
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"addi %6, %6, 32 \n\t"
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"addi %2, %2, 32 \n\t"
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"addic. %1, %1, -4 \n\t"
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"ble 2f \n\t"
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"lxvd2x 36, 0, %2 \n\t" // y0, y1
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"lxvd2x 37, %11, %2 \n\t" // y2, y3
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"xvmaddadp 36, 40, 32 \n\t"
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"xvmaddadp 37, 41, 32 \n\t"
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"lxvd2x 40, 0, %3 \n\t" // a0[0], a0[1]
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"lxvd2x 41, %11, %3 \n\t" // a0[2], a0[3]
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"xvmaddadp 36, 42, 33 \n\t"
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"addi %3, %3, 32 \n\t"
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"xvmaddadp 37, 43, 33 \n\t"
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"lxvd2x 42, 0, %4 \n\t" // a1[0], a1[1]
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"lxvd2x 43, %11, %4 \n\t" // a1[2], a1[3]
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"xvmaddadp 36, 44, 34 \n\t"
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"addi %4, %4, 32 \n\t"
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"xvmaddadp 37, 45, 34 \n\t"
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"lxvd2x 44, 0, %5 \n\t" // a2[0], a2[1]
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"lxvd2x 45, %11, %5 \n\t" // a2[2], a2[3]
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"xvmaddadp 36, 46, 35 \n\t"
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"addi %5, %5, 32 \n\t"
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"xvmaddadp 37, 47, 35 \n\t"
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"stxvd2x 36, 0, %2 \n\t" // y0, y1
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"stxvd2x 37, %11, %2 \n\t" // y2, y3
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"lxvd2x 46, 0, %6 \n\t" // a3[0], a3[1]
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"lxvd2x 47, %11, %6 \n\t" // a3[2], a3[3]
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"addi %6, %6, 32 \n\t"
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"addi %2, %2, 32 \n\t"
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"addic. %1, %1, -4 \n\t"
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"bgt 1b \n"
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"2: \n\t"
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"lxvd2x 36, 0, %2 \n\t" // y0, y1
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"lxvd2x 37, %11, %2 \n\t" // y2, y3
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"xvmaddadp 36, 40, 32 \n\t"
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"xvmaddadp 37, 41, 32 \n\t"
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"xvmaddadp 36, 42, 33 \n\t"
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"xvmaddadp 37, 43, 33 \n\t"
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"xvmaddadp 36, 44, 34 \n\t"
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"xvmaddadp 37, 45, 34 \n\t"
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"xvmaddadp 36, 46, 35 \n\t"
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"xvmaddadp 37, 47, 35 \n\t"
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"stxvd2x 36, 0, %2 \n\t" // y0, y1
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"stxvd2x 37, %11, %2 \n" // y2, y3
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"#n=%1 ap=%8=%12 lda=%13 x=%7=%10 y=%0=%2 alpha=%9 o16=%11\n"
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"#a0=%3 a1=%4 a2=%5 a3=%6"
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:
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"+m" (*y),
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"+r" (n), // 1
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"+b" (y), // 2
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"=b" (a0), // 3
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"=b" (a1), // 4
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"=&b" (a2), // 5
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"=&b" (a3) // 6
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:
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"m" (*x),
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"m" (*ap),
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"d" (alpha), // 9
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"r" (x), // 10
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"b" (16), // 11
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"3" (ap), // 12
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"4" (lda) // 13
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:
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"cr0",
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"vs32","vs33","vs34","vs35","vs36","vs37",
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"vs40","vs41","vs42","vs43","vs44","vs45","vs46","vs47"
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);
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}
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