9e2f316ede
Quoting patch author amodra from #1078 Lots of issues here. - The vsx regs weren't listed as clobbered. - Poor choice of vsx regs, which along with the lack of clobbers led to trashing v0..v21 and fr14..fr23. Ideally you'd let gcc choose all temp vsx regs, but asms currently have a limit of 30 i/o parms. - Other regs were clobbered unnecessarily, seemingly in an attempt to clobber inputs, with gcc-7 complaining about the clobber of r2. (Changed inputs should be also listed as outputs or as an i/o.) - "r" constraint used instead of "b" for gprs used in insns where the r0 encoding means zero rather than r0. - There were unused asm inputs too. - All memory was clobbered rather than hooking up memory outputs with proper memory constraints, and that and the lack of proper memory input constraints meant the asms needed to be volatile and their containing function noinline. - Some parameters were being passed unnecessarily via memory. - When a copy of a
176 lines
5.5 KiB
C
176 lines
5.5 KiB
C
/***************************************************************************
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Copyright (c) 2013-2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2016/03/21 Werner Saar (wernsaar@googlemail.com)
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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* LAPACK-TEST : OK
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**************************************************************************************/
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#define HAVE_KERNEL_16 1
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static float sdot_kernel_16 (long n, float *x, float *y)
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{
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float dot;
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__vector float t0;
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__vector float t1;
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__vector float t2;
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__vector float t3;
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__asm__
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(
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"dcbt 0, %2 \n\t"
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"dcbt 0, %3 \n\t"
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"xxlxor 32, 32, 32 \n\t"
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"xxlxor 33, 33, 33 \n\t"
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"xxlxor 34, 34, 34 \n\t"
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"xxlxor 35, 35, 35 \n\t"
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"xxlxor 36, 36, 36 \n\t"
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"xxlxor 37, 37, 37 \n\t"
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"xxlxor 38, 38, 38 \n\t"
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"xxlxor 39, 39, 39 \n\t"
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"lxvw4x 40, 0, %2 \n\t"
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"lxvw4x 48, 0, %3 \n\t"
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"lxvw4x 41, %10, %2 \n\t"
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"lxvw4x 49, %10, %3 \n\t"
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"lxvw4x 42, %11, %2 \n\t"
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"lxvw4x 50, %11, %3 \n\t"
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"lxvw4x 43, %12, %2 \n\t"
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"lxvw4x 51, %12, %3 \n\t"
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"lxvw4x 44, %13, %2 \n\t"
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"lxvw4x %x4, %13, %3 \n\t"
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"lxvw4x 45, %14, %2 \n\t"
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"lxvw4x %x5, %14, %3 \n\t"
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"lxvw4x 46, %15, %2 \n\t"
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"lxvw4x %x6, %15, %3 \n\t"
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"lxvw4x 47, %16, %2 \n\t"
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"lxvw4x %x7, %16, %3 \n\t"
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"addi %2, %2, 128 \n\t"
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"addi %3, %3, 128 \n\t"
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"addic. %1, %1, -32 \n\t"
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"ble 2f \n\t"
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".p2align 5 \n"
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"1: \n\t"
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"xvmaddasp 32, 40, 48 \n\t"
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"lxvw4x 40, 0, %2 \n\t"
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"lxvw4x 48, 0, %3 \n\t"
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"xvmaddasp 33, 41, 49 \n\t"
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"lxvw4x 41, %10, %2 \n\t"
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"lxvw4x 49, %10, %3 \n\t"
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"xvmaddasp 34, 42, 50 \n\t"
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"lxvw4x 42, %11, %2 \n\t"
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"lxvw4x 50, %11, %3 \n\t"
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"xvmaddasp 35, 43, 51 \n\t"
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"lxvw4x 43, %12, %2 \n\t"
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"lxvw4x 51, %12, %3 \n\t"
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"xvmaddasp 36, 44, %x4 \n\t"
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"lxvw4x 44, %13, %2 \n\t"
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"lxvw4x %x4, %13, %3 \n\t"
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"xvmaddasp 37, 45, %x5 \n\t"
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"lxvw4x 45, %14, %2 \n\t"
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"lxvw4x %x5, %14, %3 \n\t"
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"xvmaddasp 38, 46, %x6 \n\t"
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"lxvw4x 46, %15, %2 \n\t"
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"lxvw4x %x6, %15, %3 \n\t"
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"xvmaddasp 39, 47, %x7 \n\t"
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"lxvw4x 47, %16, %2 \n\t"
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"lxvw4x %x7, %16, %3 \n\t"
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"addi %2, %2, 128 \n\t"
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"addi %3, %3, 128 \n\t"
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"addic. %1, %1, -32 \n\t"
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"bgt 1b \n"
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"2: \n\t"
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"xvmaddasp 32, 40, 48 \n\t"
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"xvmaddasp 33, 41, 49 \n\t"
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"xvmaddasp 34, 42, 50 \n\t"
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"xvmaddasp 35, 43, 51 \n\t"
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"xvmaddasp 36, 44, %x4 \n\t"
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"xvmaddasp 37, 45, %x5 \n\t"
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"xvmaddasp 38, 46, %x6 \n\t"
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"xvmaddasp 39, 47, %x7 \n\t"
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"xvaddsp 32, 32, 33 \n\t"
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"xvaddsp 34, 34, 35 \n\t"
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"xvaddsp 36, 36, 37 \n\t"
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"xvaddsp 38, 38, 39 \n\t"
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"xvaddsp 32, 32, 34 \n\t"
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"xvaddsp 36, 36, 38 \n\t"
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"xvaddsp 32, 32, 36 \n\t"
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"xxsldwi 33, 32, 32, 2 \n\t"
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"xvaddsp 32, 32, 33 \n\t"
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"xxsldwi 33, 32, 32, 1 \n\t"
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"xvaddsp 32, 32, 33 \n\t"
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"xscvspdp %x0, 32 \n"
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"#dot=%0 n=%1 x=%8=%2 y=%9=%3 o16=%10 o32=%11 o48=%12 o64=%13 o80=%14 o96=%15 o122=%16\n"
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"#t0=%x4 t1=%x5 t2=%x6 t3=%x7"
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:
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"=f" (dot), // 0
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"+r" (n), // 1
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"+b" (x), // 2
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"+b" (y), // 3
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"=wa" (t0), // 4
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"=wa" (t1), // 5
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"=wa" (t2), // 6
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"=wa" (t3) // 7
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:
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"m" (*x),
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"m" (*y),
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"b" (16), // 10
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"b" (32), // 11
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"b" (48), // 12
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"b" (64), // 13
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"b" (80), // 14
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"b" (96), // 15
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"b" (112) // 16
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:
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"cr0",
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"vs32","vs33","vs34","vs35","vs36","vs37","vs38","vs39",
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"vs40","vs41","vs42","vs43","vs44","vs45","vs46","vs47",
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"vs48","vs49","vs50","vs51"
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);
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return dot;
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}
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