9e2f316ede
Quoting patch author amodra from #1078 Lots of issues here. - The vsx regs weren't listed as clobbered. - Poor choice of vsx regs, which along with the lack of clobbers led to trashing v0..v21 and fr14..fr23. Ideally you'd let gcc choose all temp vsx regs, but asms currently have a limit of 30 i/o parms. - Other regs were clobbered unnecessarily, seemingly in an attempt to clobber inputs, with gcc-7 complaining about the clobber of r2. (Changed inputs should be also listed as outputs or as an i/o.) - "r" constraint used instead of "b" for gprs used in insns where the r0 encoding means zero rather than r0. - There were unused asm inputs too. - All memory was clobbered rather than hooking up memory outputs with proper memory constraints, and that and the lack of proper memory input constraints meant the asms needed to be volatile and their containing function noinline. - Some parameters were being passed unnecessarily via memory. - When a copy of a
156 lines
5.0 KiB
C
156 lines
5.0 KiB
C
/***************************************************************************
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Copyright (c) 2013-2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2016/03/25 Werner Saar (wernsaar@googlemail.com)
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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* LAPACK-TEST : OK
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**************************************************************************************/
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#define HAVE_KERNEL_32 1
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static void ccopy_kernel_32 (long n, float *x, float *y)
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{
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__asm__
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(
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"lxvw4x 32, 0, %2 \n\t"
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"lxvw4x 33, %5, %2 \n\t"
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"lxvw4x 34, %6, %2 \n\t"
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"lxvw4x 35, %7, %2 \n\t"
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"lxvw4x 36, %8, %2 \n\t"
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"lxvw4x 37, %9, %2 \n\t"
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"lxvw4x 38, %10, %2 \n\t"
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"lxvw4x 39, %11, %2 \n\t"
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"addi %2, %2, 128 \n\t"
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"lxvw4x 40, 0, %2 \n\t"
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"lxvw4x 41, %5, %2 \n\t"
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"lxvw4x 42, %6, %2 \n\t"
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"lxvw4x 43, %7, %2 \n\t"
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"lxvw4x 44, %8, %2 \n\t"
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"lxvw4x 45, %9, %2 \n\t"
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"lxvw4x 46, %10, %2 \n\t"
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"lxvw4x 47, %11, %2 \n\t"
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"addi %2, %2, 128 \n\t"
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"addic. %1, %1, -32 \n\t"
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"ble 2f \n\t"
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".p2align 5 \n"
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"1: \n\t"
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"stxvw4x 32, 0, %3 \n\t"
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"stxvw4x 33, %5, %3 \n\t"
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"lxvw4x 32, 0, %2 \n\t"
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"lxvw4x 33, %5, %2 \n\t"
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"stxvw4x 34, %6, %3 \n\t"
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"stxvw4x 35, %7, %3 \n\t"
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"lxvw4x 34, %6, %2 \n\t"
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"lxvw4x 35, %7, %2 \n\t"
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"stxvw4x 36, %8, %3 \n\t"
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"stxvw4x 37, %9, %3 \n\t"
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"lxvw4x 36, %8, %2 \n\t"
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"lxvw4x 37, %9, %2 \n\t"
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"stxvw4x 38, %10, %3 \n\t"
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"stxvw4x 39, %11, %3 \n\t"
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"lxvw4x 38, %10, %2 \n\t"
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"lxvw4x 39, %11, %2 \n\t"
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"addi %3, %3, 128 \n\t"
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"addi %2, %2, 128 \n\t"
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"stxvw4x 40, 0, %3 \n\t"
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"stxvw4x 41, %5, %3 \n\t"
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"lxvw4x 40, 0, %2 \n\t"
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"lxvw4x 41, %5, %2 \n\t"
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"stxvw4x 42, %6, %3 \n\t"
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"stxvw4x 43, %7, %3 \n\t"
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"lxvw4x 42, %6, %2 \n\t"
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"lxvw4x 43, %7, %2 \n\t"
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"stxvw4x 44, %8, %3 \n\t"
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"stxvw4x 45, %9, %3 \n\t"
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"lxvw4x 44, %8, %2 \n\t"
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"lxvw4x 45, %9, %2 \n\t"
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"stxvw4x 46, %10, %3 \n\t"
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"stxvw4x 47, %11, %3 \n\t"
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"lxvw4x 46, %10, %2 \n\t"
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"lxvw4x 47, %11, %2 \n\t"
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"addi %3, %3, 128 \n\t"
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"addi %2, %2, 128 \n\t"
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"addic. %1, %1, -32 \n\t"
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"bgt 1b \n"
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"2: \n\t"
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"stxvw4x 32, 0, %3 \n\t"
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"stxvw4x 33, %5, %3 \n\t"
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"stxvw4x 34, %6, %3 \n\t"
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"stxvw4x 35, %7, %3 \n\t"
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"stxvw4x 36, %8, %3 \n\t"
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"stxvw4x 37, %9, %3 \n\t"
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"stxvw4x 38, %10, %3 \n\t"
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"stxvw4x 39, %11, %3 \n\t"
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"addi %3, %3, 128 \n\t"
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"stxvw4x 40, 0, %3 \n\t"
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"stxvw4x 41, %5, %3 \n\t"
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"stxvw4x 42, %6, %3 \n\t"
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"stxvw4x 43, %7, %3 \n\t"
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"stxvw4x 44, %8, %3 \n\t"
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"stxvw4x 45, %9, %3 \n\t"
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"stxvw4x 46, %10, %3 \n\t"
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"stxvw4x 47, %11, %3 \n"
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"#n=%1 x=%4=%2 y=%0=%3 o16=%5 o32=%6 o48=%7 o64=%8 o80=%9 o96=%10 o112=%11"
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:
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"=m" (*y),
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"+r" (n), // 1
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"+b" (x), // 2
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"+b" (y) // 3
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:
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"m" (*x),
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"b" (16), // 5
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"b" (32), // 6
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"b" (48), // 7
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"b" (64), // 8
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"b" (80), // 9
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"b" (96), // 10
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"b" (112) // 11
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:
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"cr0",
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"vs32","vs33","vs34","vs35","vs36","vs37","vs38","vs39",
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"vs40","vs41","vs42","vs43","vs44","vs45","vs46","vs47"
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);
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}
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