222 lines
		
	
	
		
			7.6 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			222 lines
		
	
	
		
			7.6 KiB
		
	
	
	
		
			C
		
	
	
	
| /***************************************************************************
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| Copyright (c) 2020, The OpenBLAS Project
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| All rights reserved.
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| Redistribution and use in source and binary forms, with or without
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| modification, are permitted provided that the following conditions are
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| met:
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| 1. Redistributions of source code must retain the above copyright
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| notice, this list of conditions and the following disclaimer.
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| 2. Redistributions in binary form must reproduce the above copyright
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| notice, this list of conditions and the following disclaimer in
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| the documentation and/or other materials provided with the
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| distribution.
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| 3. Neither the name of the OpenBLAS project nor the names of
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| its contributors may be used to endorse or promote products
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| derived from this software without specific prior written permission.
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| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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| USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| *****************************************************************************/
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| 
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| #define HAVE_KERNEL_8 1
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| static void caxpy_kernel_8 (long n, float *x, float *y,
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| 			    float alpha_r, float alpha_i)
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| {
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| #if !defined(CONJ)
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|   static const float mvec[4] = { -1.0, 1.0, -1.0, 1.0 };
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| #else
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|   static const float mvec[4] = { 1.0, -1.0, 1.0, -1.0 };
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| #endif
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|   const float *mvecp = mvec;
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|   /* We have to load reverse mask for big endian.  */
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| #if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
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|   __vector unsigned char mask={ 4,5,6,7,0,1,2,3,12,13,14,15,8,9,10,11}; 
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| #else
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|   __vector unsigned char mask = { 11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4};
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| #endif
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| 
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|   long ytmp;
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| 
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|   __asm__
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|     (
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|        "xscvdpspn 32, %7    \n\t"
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|        "xscvdpspn 33, %8    \n\t"
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|        "xxspltw 32, 32, 0   \n\t"
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|        "xxspltw 33, 33, 0   \n\t"
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|        "lxvd2x          36, 0, %9       \n\t"   // mvec
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| 
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| #if !defined(CONJ)
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|        "xvmulsp		33, 33, 36	\n\t"	// alpha_i * mvec
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| #else
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|        "xvmulsp		32, 32, 36	\n\t"	// alpha_r * mvec
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| #endif
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|        "mr		%4, %3		\n\t"
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|        "dcbt		0, %2		\n\t"
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|        "dcbt		0, %3		\n\t"
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| 
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|        "lxvp		40, 0(%2)	\n\t"	// x0
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|        "lxvp		42, 32(%2)	\n\t"	// x2
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|        "lxvp		48, 0(%3)	\n\t"	// y0
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|        "lxvp		50, 32(%3)	\n\t"	// y2
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| 
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|        "xxperm 52, 40, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 53, 41, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 54, 42, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 55, 43, %x10 \n\t"       // exchange real and imag part
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| 
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|        "lxvp		44, 64(%2)	\n\t"	// x4
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|        "lxvp		46, 96(%2)	\n\t"	// x6
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|        "lxvp		34, 64(%3)	\n\t"	// y4
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|        "lxvp		38, 96(%3)	\n\t"	// y6
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| 
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|        "xxperm 56, 44, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 57, 45, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 58, 46, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 59, 47, %x10 \n\t"       // exchange real and imag part
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| 
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|        "addi		%2, %2, 128	\n\t"
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|        "addi		%3, %3, 128	\n\t"
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| 
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|        "addic.		%1, %1, -16	\n\t"
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|        "ble		two%=		\n\t"
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| 
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|        ".align	5		\n"
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|        "one%=:				\n\t"
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| 
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|        "xvmaddasp	48, 40, 32	\n\t"	// alpha_r * x0_r , alpha_r * x0_i
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|        "xvmaddasp	49, 41, 32	\n\t"
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|        "lxvp		40, 0(%2)	\n\t"	// x0
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|        "xvmaddasp	50, 42, 32	\n\t"
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|        "xvmaddasp	51, 43, 32	\n\t"
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|        "lxvp		42, 32(%2)	\n\t"	// x2
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| 
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|        "xvmaddasp	34, 44, 32	\n\t"
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|        "xvmaddasp	35, 45, 32	\n\t"
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|        "lxvp		44, 64(%2)	\n\t"	// x4
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|        "xvmaddasp	38, 46, 32	\n\t"
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|        "xvmaddasp	39, 47, 32	\n\t"
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|        "lxvp		46, 96(%2)	\n\t"	// x6
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| 
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|        "xvmaddasp	48, 52, 33	\n\t"	// alpha_i * x0_i , alpha_i * x0_r
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|        "addi		%2, %2, 128	\n\t"
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|        "xvmaddasp	49, 53, 33	\n\t"
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|        "xvmaddasp	50, 54, 33	\n\t"
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|        "xvmaddasp	51, 55, 33	\n\t"
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| 
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|        "xvmaddasp	34, 56, 33	\n\t"
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|        "xvmaddasp	35, 57, 33	\n\t"
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|        "xvmaddasp	38, 58, 33	\n\t"
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|        "xvmaddasp	39, 59, 33	\n\t"
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| 
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| #if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
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|        "stxv        48, 0(%4)   \n\t"
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|        "stxv        49, 16(%4)  \n\t"
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|        "stxv        50, 32(%4)  \n\t"
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|        "stxv        51, 48(%4)  \n\t"
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|        "stxv        34, 64(%4)  \n\t"
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|        "stxv        35, 80(%4)  \n\t"
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|        "stxv        38, 96(%4)  \n\t"
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|        "stxv        39, 112(%4) \n\t"
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| #else 
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|        "stxv		49, 0(%4)	\n\t"
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|        "stxv		48, 16(%4)	\n\t"
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|        "stxv		51, 32(%4)	\n\t"
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|        "stxv		50, 48(%4)	\n\t"
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|        "stxv		35, 64(%4)	\n\t"
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|        "stxv		34, 80(%4)	\n\t"
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|        "stxv		39, 96(%4)	\n\t"
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|        "stxv		38, 112(%4)	\n\t"
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| #endif
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| 
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|        "addi		%4, %4, 128	\n\t"
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|        "xxperm 52, 40, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 53, 41, %x10 \n\t"       // exchange real and imag part
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| 
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|        "lxvp		48, 0(%3)	\n\t"	// y0
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|        "xxperm 54, 42, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 55, 43, %x10 \n\t"       // exchange real and imag part
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|        "lxvp		50, 32(%3)	\n\t"	// y2
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| 
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|        "xxperm 56, 44, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 57, 45, %x10 \n\t"       // exchange real and imag part
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|        "lxvp		34, 64(%3)	\n\t"	// y4
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|        "xxperm 58, 46, %x10 \n\t"       // exchange real and imag part
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|        "xxperm 59, 47, %x10 \n\t"       // exchange real and imag part
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|        "lxvp		38, 96(%3)	\n\t"	// y6
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| 
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|        "addi		%3, %3, 128	\n\t"
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| 
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|        "addic.		%1, %1, -16	\n\t"
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|        "bgt		one%=		\n"
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| 
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|        "two%=:				\n\t"
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|        "xvmaddasp	48, 40, 32	\n\t"	// alpha_r * x0_r , alpha_r * x0_i
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|        "xvmaddasp	49, 41, 32	\n\t"
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|        "xvmaddasp	50, 42, 32	\n\t"
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|        "xvmaddasp	51, 43, 32	\n\t"
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| 
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|        "xvmaddasp	34, 44, 32	\n\t"
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|        "xvmaddasp	35, 45, 32	\n\t"
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|        "xvmaddasp	38, 46, 32	\n\t"
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|        "xvmaddasp	39, 47, 32	\n\t"
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| 
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|        "xvmaddasp	48, 52, 33	\n\t"	// alpha_i * x0_i , alpha_i * x0_r
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|        "xvmaddasp	49, 53, 33	\n\t"
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|        "xvmaddasp	50, 54, 33	\n\t"
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|        "xvmaddasp	51, 55, 33	\n\t"
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| 
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|        "xvmaddasp	34, 56, 33	\n\t"
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|        "xvmaddasp	35, 57, 33	\n\t"
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|        "xvmaddasp	38, 58, 33	\n\t"
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|        "xvmaddasp	39, 59, 33	\n\t"
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| 
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| #if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
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|        "stxv        48, 0(%4)   \n\t"
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|        "stxv        49, 16(%4)  \n\t"
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|        "stxv        50, 32(%4)  \n\t"
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|        "stxv        51, 48(%4)  \n\t"
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|        "stxv        34, 64(%4)  \n\t"
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|        "stxv        35, 80(%4)  \n\t"
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|        "stxv        38, 96(%4)  \n\t"
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|        "stxv        39, 112(%4) \n\t"
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| #else
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|        "stxv		49, 0(%4)	\n\t"
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|        "stxv		48, 16(%4)	\n\t"
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|        "stxv		51, 32(%4)	\n\t"
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|        "stxv		50, 48(%4)	\n\t"
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|        "stxv		35, 64(%4)	\n\t"
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|        "stxv		34, 80(%4)	\n\t"
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|        "stxv		39, 96(%4)	\n\t"
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|        "stxv		38, 112(%4)	\n\t"
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| #endif
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| 
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|      "#n=%1 x=%5=%2 y=%0=%3 alpha=(%7,%8) mvecp=%6=%9 ytmp=%4\n"
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|      :
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|        "+m" (*y),
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|        "+r" (n),	// 1
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|        "+b" (x),	// 2
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|        "+b" (y),	// 3
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|        "=b" (ytmp)	// 4 
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|      :
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|        "m" (*x),
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|        "m" (*mvecp),
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|        "d" (alpha_r),	// 7
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|        "d" (alpha_i),	// 8
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|        "4" (mvecp),	// 9
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|        "wa" (mask)
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|      :
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|        "cr0",
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|        "vs32","vs33","vs34","vs35","vs36","vs37","vs38","vs39",
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|        "vs40","vs41","vs42","vs43","vs44","vs45","vs46","vs47",
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|        "vs48","vs49","vs50","vs51","vs52","vs53","vs54","vs55",
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|        "vs56","vs57","vs58","vs59"
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|      );
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| }
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