148 lines
2.9 KiB
ArmAsm
148 lines
2.9 KiB
ArmAsm
#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r17
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#define TEMP $r18
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#define t1 $r15
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#define t2 $r12
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#define t3 $r13
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#define t4 $r14
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#define VX0 $xr12
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#define VX1 $xr13
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#define VX2 $xr14
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#define VX3 $xr15
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#define VT0 $xr23
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#define VT1 $xr22
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#define res1 $xr16
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#define res2 $xr17
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#define res0 $xr18
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#define neg1 $xr19
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PROLOGUE
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xvxor.v res1, res1, res1
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xvxor.v res2, res2, res2
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xvxor.v res0, res0, res0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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li.d t1, -1
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xvreplgr2vr.d neg1, t1
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xvffint.d.l neg1, neg1
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li.d TEMP, SIZE
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slli.d INCX, INCX, BASE_SHIFT
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srai.d I, N, 3
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bne INCX, TEMP, .L20
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bge $r0, I, .L13
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.align 3
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.L11:
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xvld VX0, X, 0 * SIZE
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xvld VX1, X, 4 * SIZE
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xvfmul.d VX2, neg1, VX0
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xvfmul.d VX3, neg1, VX1
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xvfcmp.clt.d VT0, VX0, res0
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xvfcmp.clt.d VT1, VX1, res0
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xvbitsel.v VX0, VX0, VX2, VT0
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xvbitsel.v VX1, VX1, VX3, VT1
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xvfadd.d res2, VX0, VX1
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xvfadd.d res1, res1, res2
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addi.d X, X, 8 * SIZE
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addi.d I, I, -1
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blt $r0, I, .L11
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.align 3
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.L12:
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xvpickve.d VX1, res1, 1
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xvpickve.d VX2, res1, 2
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xvpickve.d VX3, res1, 3
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xvfadd.d res1, VX1, res1
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xvfadd.d res1, VX2, res1
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xvfadd.d res1, VX3, res1
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.align 3
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.L13:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L14:
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fld.d $f12, X, 0 * SIZE
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fabs.d $f12, $f12
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fadd.d $f16, $f12, $f16
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addi.d I, I, -1
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addi.d X, X, SIZE
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blt $r0, I, .L14
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b .L999
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.align 3
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.L20:
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bge $r0, I, .L23
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.align 3
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.L21:
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX0, t1, 0
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xvinsgr2vr.d VX0, t2, 1
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xvinsgr2vr.d VX0, t3, 2
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xvinsgr2vr.d VX0, t4, 3
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t4, X, 0 * SIZE
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add.d X, X, INCX
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xvinsgr2vr.d VX1, t1, 0
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xvinsgr2vr.d VX1, t2, 1
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xvinsgr2vr.d VX1, t3, 2
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xvinsgr2vr.d VX1, t4, 3
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xvfmul.d VX2, neg1, VX0
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xvfmul.d VX3, neg1, VX1
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xvfcmp.clt.d VT0, VX0, res0
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xvfcmp.clt.d VT1, VX1, res0
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xvbitsel.v VX0, VX0, VX2, VT0
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xvbitsel.v VX1, VX1, VX3, VT1
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xvfadd.d res2, VX0, VX1
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xvfadd.d res1, res1, res2
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addi.d I, I, -1
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blt $r0, I, .L21
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.align 3
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.L22:
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xvpickve.d VX1, res1, 1
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xvpickve.d VX2, res1, 2
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xvpickve.d VX3, res1, 3
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xvfadd.d res1, VX1, res1
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xvfadd.d res1, VX2, res1
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xvfadd.d res1, VX3, res1
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.align 3
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.L23:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L24:
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fld.d $f12, X, 0 * SIZE
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fabs.d $f12, $f12
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fadd.d $f16, $f12, $f16
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addi.d I, I, -1
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add.d X, X, INCX
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blt $r0, I, .L24
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.align 3
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.L999:
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fmov.d $f0, $f16
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jirl $r0, $r1, 0x0
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.align 3
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EPILOGUE |