9e2f316ede
Quoting patch author amodra from #1078 Lots of issues here. - The vsx regs weren't listed as clobbered. - Poor choice of vsx regs, which along with the lack of clobbers led to trashing v0..v21 and fr14..fr23. Ideally you'd let gcc choose all temp vsx regs, but asms currently have a limit of 30 i/o parms. - Other regs were clobbered unnecessarily, seemingly in an attempt to clobber inputs, with gcc-7 complaining about the clobber of r2. (Changed inputs should be also listed as outputs or as an i/o.) - "r" constraint used instead of "b" for gprs used in insns where the r0 encoding means zero rather than r0. - There were unused asm inputs too. - All memory was clobbered rather than hooking up memory outputs with proper memory constraints, and that and the lack of proper memory input constraints meant the asms needed to be volatile and their containing function noinline. - Some parameters were being passed unnecessarily via memory. - When a copy of a
214 lines
6.7 KiB
C
214 lines
6.7 KiB
C
/***************************************************************************
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Copyright (c) 2013-2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2016/03/27 Werner Saar (wernsaar@googlemail.com)
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*
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* I don't use fused multiply-add ( precision problems with lapack )
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*
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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* LAPACK-TEST : OK
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**************************************************************************************/
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#define HAVE_KERNEL_16 1
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static void drot_kernel_16 (long n, double *x, double *y, double c, double s)
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{
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__vector double t0;
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__vector double t1;
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__vector double t2;
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__vector double t3;
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__vector double t4;
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__vector double t5;
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__vector double t6;
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__vector double t7;
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__asm__
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(
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"xxspltd 36, %x13, 0 \n\t" // load c to both dwords
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"xxspltd 37, %x14, 0 \n\t" // load s to both dwords
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"lxvd2x 32, 0, %3 \n\t" // load x
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"lxvd2x 33, %15, %3 \n\t"
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"lxvd2x 34, %16, %3 \n\t"
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"lxvd2x 35, %17, %3 \n\t"
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"lxvd2x 48, 0, %4 \n\t" // load y
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"lxvd2x 49, %15, %4 \n\t"
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"lxvd2x 50, %16, %4 \n\t"
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"lxvd2x 51, %17, %4 \n\t"
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"addi %3, %3, 64 \n\t"
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"addi %4, %4, 64 \n\t"
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"addic. %2, %2, -8 \n\t"
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"ble 2f \n\t"
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".p2align 5 \n"
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"1: \n\t"
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"xvmuldp 40, 32, 36 \n\t" // c * x
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"xvmuldp 41, 33, 36 \n\t"
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"xvmuldp 42, 34, 36 \n\t"
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"xvmuldp 43, 35, 36 \n\t"
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"xvmuldp %x5, 48, 36 \n\t" // c * y
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"xvmuldp %x6, 49, 36 \n\t"
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"xvmuldp %x7, 50, 36 \n\t"
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"xvmuldp %x8, 51, 36 \n\t"
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"xvmuldp 44, 32, 37 \n\t" // s * x
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"xvmuldp 45, 33, 37 \n\t"
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"lxvd2x 32, 0, %3 \n\t" // load x
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"lxvd2x 33, %15, %3 \n\t"
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"xvmuldp 46, 34, 37 \n\t"
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"xvmuldp 47, 35, 37 \n\t"
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"lxvd2x 34, %16, %3 \n\t"
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"lxvd2x 35, %17, %3 \n\t"
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"xvmuldp %x9, 48, 37 \n\t" // s * y
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"xvmuldp %x10, 49, 37 \n\t"
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"lxvd2x 48, 0, %4 \n\t" // load y
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"lxvd2x 49, %15, %4 \n\t"
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"xvmuldp %x11, 50, 37 \n\t"
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"xvmuldp %x12, 51, 37 \n\t"
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"lxvd2x 50, %16, %4 \n\t"
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"lxvd2x 51, %17, %4 \n\t"
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"xvadddp 40, 40, %x9 \n\t" // c * x + s * y
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"xvadddp 41, 41, %x10 \n\t" // c * x + s * y
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"addi %3, %3, -64 \n\t"
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"addi %4, %4, -64 \n\t"
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"xvadddp 42, 42, %x11 \n\t" // c * x + s * y
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"xvadddp 43, 43, %x12 \n\t" // c * x + s * y
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"xvsubdp %x5, %x5, 44 \n\t" // c * y - s * x
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"xvsubdp %x6, %x6, 45 \n\t" // c * y - s * x
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"xvsubdp %x7, %x7, 46 \n\t" // c * y - s * x
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"xvsubdp %x8, %x8, 47 \n\t" // c * y - s * x
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"stxvd2x 40, 0, %3 \n\t" // store x
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"stxvd2x 41, %15, %3 \n\t"
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"stxvd2x 42, %16, %3 \n\t"
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"stxvd2x 43, %17, %3 \n\t"
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"stxvd2x %x5, 0, %4 \n\t" // store y
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"stxvd2x %x6, %15, %4 \n\t"
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"stxvd2x %x7, %16, %4 \n\t"
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"stxvd2x %x8, %17, %4 \n\t"
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"addi %3, %3, 128 \n\t"
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"addi %4, %4, 128 \n\t"
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"addic. %2, %2, -8 \n\t"
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"bgt 1b \n"
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"2: \n\t"
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"xvmuldp 40, 32, 36 \n\t" // c * x
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"xvmuldp 41, 33, 36 \n\t"
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"xvmuldp 42, 34, 36 \n\t"
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"xvmuldp 43, 35, 36 \n\t"
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"xvmuldp %x5, 48, 36 \n\t" // c * y
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"xvmuldp %x6, 49, 36 \n\t"
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"xvmuldp %x7, 50, 36 \n\t"
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"xvmuldp %x8, 51, 36 \n\t"
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"xvmuldp 44, 32, 37 \n\t" // s * x
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"xvmuldp 45, 33, 37 \n\t"
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"xvmuldp 46, 34, 37 \n\t"
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"xvmuldp 47, 35, 37 \n\t"
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"xvmuldp %x9, 48, 37 \n\t" // s * y
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"xvmuldp %x10, 49, 37 \n\t"
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"xvmuldp %x11, 50, 37 \n\t"
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"xvmuldp %x12, 51, 37 \n\t"
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"addi %3, %3, -64 \n\t"
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"addi %4, %4, -64 \n\t"
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"xvadddp 40, 40, %x9 \n\t" // c * x + s * y
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"xvadddp 41, 41, %x10 \n\t" // c * x + s * y
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"xvadddp 42, 42, %x11 \n\t" // c * x + s * y
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"xvadddp 43, 43, %x12 \n\t" // c * x + s * y
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"xvsubdp %x5, %x5, 44 \n\t" // c * y - s * x
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"xvsubdp %x6, %x6, 45 \n\t" // c * y - s * x
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"xvsubdp %x7, %x7, 46 \n\t" // c * y - s * x
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"xvsubdp %x8, %x8, 47 \n\t" // c * y - s * x
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"stxvd2x 40, 0, %3 \n\t" // store x
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"stxvd2x 41, %15, %3 \n\t"
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"stxvd2x 42, %16, %3 \n\t"
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"stxvd2x 43, %17, %3 \n\t"
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"stxvd2x %x5, 0, %4 \n\t" // store y
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"stxvd2x %x6, %15, %4 \n\t"
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"stxvd2x %x7, %16, %4 \n\t"
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"stxvd2x %x8, %17, %4 \n"
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"#n=%2 x=%0=%3 y=%1=%4 c=%13 s=%14 o16=%15 o32=%16 o48=%17\n"
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"#t0=%x5 t1=%x6 t2=%x7 t3=%x8 t4=%x9 t5=%x10 t6=%x11 t7=%x12"
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:
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"+m" (*x),
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"+m" (*y),
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"+r" (n), // 2
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"+b" (x), // 3
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"+b" (y), // 4
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"=wa" (t0), // 5
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"=wa" (t1), // 6
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"=wa" (t2), // 7
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"=wa" (t3), // 8
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"=wa" (t4), // 9
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"=wa" (t5), // 10
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"=wa" (t6), // 11
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"=wa" (t7) // 12
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:
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"d" (c), // 13
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"d" (s), // 14
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"b" (16), // 15
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"b" (32), // 16
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"b" (48) // 17
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:
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"cr0",
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"vs32","vs33","vs34","vs35","vs36","vs37",
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"vs40","vs41","vs42","vs43","vs44","vs45","vs46","vs47",
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"vs48","vs49","vs50","vs51"
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);
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}
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