727 lines
14 KiB
ArmAsm
727 lines
14 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2013/11/29 Saar
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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*
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**************************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define STACKSIZE 256
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#if !defined(__ARM_PCS_VFP)
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#define OLD_ALPHAR [fp, #0 ]
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#define OLD_ALPHAI [fp, #8 ]
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#define OLD_A_SOFTFP [fp, #16]
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#define OLD_LDA [fp, #20]
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#define X [fp, #24]
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#define OLD_INC_X [fp, #28]
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#define Y [fp, #32]
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#define OLD_INC_Y [fp, #36]
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#else
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#define OLD_LDA [fp, #0 ]
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#define X [fp, #4 ]
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#define OLD_INC_X [fp, #8 ]
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#define Y [fp, #12 ]
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#define OLD_INC_Y [fp, #16 ]
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#endif
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#define OLD_A r3
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#define OLD_M r0
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#define AO1 r0
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#define N r1
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#define J r2
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#define AO2 r4
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#define XO r5
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#define YO r6
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#define LDA r7
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#define INC_X r8
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#define INC_Y r9
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#define I r12
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#define FP_ZERO [fp, #-228]
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#define FP_ZERO_0 [fp, #-228]
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#define FP_ZERO_1 [fp, #-224]
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#define ALPHA_I [fp, #-236]
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#define ALPHA_R [fp, #-244]
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#define M [fp, #-252 ]
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#define A [fp, #-256 ]
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#define X_PRE 64
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#define Y_PRE 0
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#define A_PRE 0
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/**************************************************************************************/
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#if !defined(CONJ) && !defined(XCONJ)
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#define KMAC_R vmls.f64
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#define KMAC_I fmacd
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#define FMAC_R1 fmacd
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#define FMAC_R2 vmls.f64
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#define FMAC_I1 fmacd
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#define FMAC_I2 fmacd
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#elif defined(CONJ) && !defined(XCONJ)
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#define KMAC_R fmacd
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#define KMAC_I vmls.f64
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#define FMAC_R1 fmacd
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#define FMAC_R2 vmls.f64
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#define FMAC_I1 fmacd
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#define FMAC_I2 fmacd
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#elif !defined(CONJ) && defined(XCONJ)
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#define KMAC_R fmacd
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#define KMAC_I vmls.f64
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#define FMAC_R1 fmacd
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#define FMAC_R2 fmacd
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#define FMAC_I1 vmls.f64
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#define FMAC_I2 fmacd
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#else
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#define KMAC_R vmls.f64
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#define KMAC_I fmacd
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#define FMAC_R1 fmacd
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#define FMAC_R2 fmacd
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#define FMAC_I1 vmls.f64
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#define FMAC_I2 fmacd
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#endif
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.macro INIT_F4
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pld [ YO, #Y_PRE ]
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fldd d8, FP_ZERO
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vmov.f64 d9 , d8
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vmov.f64 d10, d8
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vmov.f64 d11, d8
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vmov.f64 d12, d8
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vmov.f64 d13, d8
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vmov.f64 d14, d8
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vmov.f64 d15, d8
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.endm
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.macro KERNEL_F4X4
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pld [ XO, #X_PRE ]
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KERNEL_F4X1
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KERNEL_F4X1
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pld [ XO, #X_PRE ]
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KERNEL_F4X1
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KERNEL_F4X1
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.endm
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.macro KERNEL_F4X1
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fldd d0 , [ AO1 ]
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fldd d4 , [ XO ]
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fldd d5 , [ XO, #8 ]
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pld [ AO2, #A_PRE ]
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fldd d1 , [ AO1, #8 ]
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fmacd d8 , d0, d4
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fldd d2 , [ AO1, #16 ]
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fmacd d9 , d0, d5
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fldd d3 , [ AO1, #24 ]
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fmacd d10 , d2, d4
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fldd d0 , [ AO1, #32 ]
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fmacd d11 , d2, d5
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KMAC_R d8 , d1, d5
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KMAC_I d9 , d1, d4
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KMAC_R d10 , d3, d5
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fldd d1 , [ AO1, #40 ]
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KMAC_I d11 , d3, d4
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fldd d2 , [ AO1, #48 ]
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fmacd d12 , d0, d4
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fldd d3 , [ AO1, #56 ]
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fmacd d13 , d0, d5
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pld [ AO2, #A_PRE+32 ]
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fmacd d14 , d2, d4
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fmacd d15 , d2, d5
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KMAC_R d12 , d1, d5
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add XO , XO, #16
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KMAC_I d13 , d1, d4
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add AO1 , AO1, LDA
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KMAC_R d14 , d3, d5
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add AO2 , AO2, LDA
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KMAC_I d15 , d3, d4
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.endm
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.macro SAVE_F4
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fldd d0, ALPHA_R
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fldd d1, ALPHA_I
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vldmia.f64 YO, { d4 - d7 }
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FMAC_R1 d4 , d0 , d8
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FMAC_I1 d5 , d0 , d9
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FMAC_R2 d4 , d1 , d9
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FMAC_I2 d5 , d1 , d8
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FMAC_R1 d6 , d0 , d10
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FMAC_I1 d7 , d0 , d11
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FMAC_R2 d6 , d1 , d11
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FMAC_I2 d7 , d1 , d10
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vstmia.f64 YO!, { d4 - d7 }
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vldmia.f64 YO, { d4 - d7 }
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FMAC_R1 d4 , d0 , d12
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FMAC_I1 d5 , d0 , d13
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FMAC_R2 d4 , d1 , d13
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FMAC_I2 d5 , d1 , d12
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FMAC_R1 d6 , d0 , d14
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FMAC_I1 d7 , d0 , d15
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FMAC_R2 d6 , d1 , d15
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FMAC_I2 d7 , d1 , d14
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vstmia.f64 YO!, { d4 - d7 }
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.endm
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.macro INIT_F1
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fldd d8, FP_ZERO
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vmov.f64 d9 , d8
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.endm
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.macro KERNEL_F1X1
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fldd d0 , [ AO1 ]
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fldd d1 , [ AO1, #8 ]
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fldd d4 , [ XO ]
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fldd d5 , [ XO, #8 ]
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fmacd d8 , d0, d4
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fmacd d9 , d0, d5
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KMAC_R d8 , d1, d5
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KMAC_I d9 , d1, d4
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add XO , XO, #16
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add AO1 , AO1, LDA
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.endm
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.macro SAVE_F1
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fldd d0, ALPHA_R
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fldd d1, ALPHA_I
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d8
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FMAC_I1 d5 , d0 , d9
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FMAC_R2 d4 , d1 , d9
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FMAC_I2 d5 , d1 , d8
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vstmia.f64 YO, { d4 - d5 }
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add YO, YO, #16
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.endm
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/****************************************************************************************/
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.macro INIT_S4
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fldd d8, FP_ZERO
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vmov.f64 d9 , d8
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vmov.f64 d10, d8
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vmov.f64 d11, d8
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vmov.f64 d12, d8
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vmov.f64 d13, d8
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vmov.f64 d14, d8
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vmov.f64 d15, d8
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.endm
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.macro KERNEL_S4X4
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KERNEL_S4X1
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KERNEL_S4X1
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KERNEL_S4X1
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KERNEL_S4X1
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.endm
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.macro KERNEL_S4X1
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fldd d0 , [ AO1 ]
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fldd d1 , [ AO1, #8 ]
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fldd d2 , [ AO1, #16 ]
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fldd d3 , [ AO1, #24 ]
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fldd d4 , [ XO ]
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fldd d5 , [ XO, #8 ]
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fmacd d8 , d0, d4
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fmacd d9 , d0, d5
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fmacd d10 , d2, d4
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fmacd d11 , d2, d5
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KMAC_R d8 , d1, d5
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KMAC_I d9 , d1, d4
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KMAC_R d10 , d3, d5
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KMAC_I d11 , d3, d4
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fldd d0 , [ AO1, #32 ]
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fldd d1 , [ AO1, #40 ]
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fldd d2 , [ AO1, #48 ]
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fldd d3 , [ AO1, #56 ]
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fmacd d12 , d0, d4
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fmacd d13 , d0, d5
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fmacd d14 , d2, d4
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fmacd d15 , d2, d5
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KMAC_R d12 , d1, d5
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KMAC_I d13 , d1, d4
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KMAC_R d14 , d3, d5
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KMAC_I d15 , d3, d4
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add XO , XO, INC_X
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add AO1 , AO1, LDA
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add AO2 , AO2, LDA
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.endm
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.macro SAVE_S4
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fldd d0, ALPHA_R
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fldd d1, ALPHA_I
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d8
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FMAC_I1 d5 , d0 , d9
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FMAC_R2 d4 , d1 , d9
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FMAC_I2 d5 , d1 , d8
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vstmia.f64 YO, { d4 - d5 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d6 - d7 }
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FMAC_R1 d6 , d0 , d10
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FMAC_I1 d7 , d0 , d11
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FMAC_R2 d6 , d1 , d11
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FMAC_I2 d7 , d1 , d10
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vstmia.f64 YO, { d6 - d7 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d12
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FMAC_I1 d5 , d0 , d13
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FMAC_R2 d4 , d1 , d13
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FMAC_I2 d5 , d1 , d12
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vstmia.f64 YO, { d4 - d5 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d6 - d7 }
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FMAC_R1 d6 , d0 , d14
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FMAC_I1 d7 , d0 , d15
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FMAC_R2 d6 , d1 , d15
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FMAC_I2 d7 , d1 , d14
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vstmia.f64 YO, { d6 - d7 }
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add YO, YO, INC_Y
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.endm
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.macro INIT_S1
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fldd d8, FP_ZERO
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vmov.f64 d9 , d8
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.endm
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.macro KERNEL_S1X1
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fldd d0 , [ AO1 ]
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fldd d1 , [ AO1, #8 ]
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fldd d4 , [ XO ]
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fldd d5 , [ XO, #8 ]
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fmacd d8 , d0, d4
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fmacd d9 , d0, d5
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KMAC_R d8 , d1, d5
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KMAC_I d9 , d1, d4
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add XO , XO, INC_X
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add AO1 , AO1, LDA
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.endm
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.macro SAVE_S1
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fldd d0, ALPHA_R
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fldd d1, ALPHA_I
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d8
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FMAC_I1 d5 , d0 , d9
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FMAC_R2 d4 , d1 , d9
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FMAC_I2 d5 , d1 , d8
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vstmia.f64 YO, { d4 - d5 }
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add YO, YO, INC_Y
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.endm
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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push {r4 - r9 , fp}
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add fp, sp, #28
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sub sp, sp, #STACKSIZE // reserve stack
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sub r12, fp, #192
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#if defined(DOUBLE)
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vstm r12, { d8 - d15 } // store floating point registers
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#else
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vstm r12, { s8 - s15 } // store floating point registers
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#endif
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movs r12, #0
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str r12, FP_ZERO
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str r12, FP_ZERO_1
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cmp OLD_M, #0
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ble zgemvn_kernel_L999
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cmp N, #0
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ble zgemvn_kernel_L999
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#if !defined(__ARM_PCS_VFP)
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vldr d0, OLD_ALPHAR
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vldr d1, OLD_ALPHAI
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ldr OLD_A, OLD_A_SOFTFP
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#endif
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str OLD_A, A
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str OLD_M, M
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vstr d0 , ALPHA_R
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vstr d1 , ALPHA_I
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ldr INC_X , OLD_INC_X
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ldr INC_Y , OLD_INC_Y
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cmp INC_X, #0
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beq zgemvn_kernel_L999
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cmp INC_Y, #0
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beq zgemvn_kernel_L999
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ldr LDA, OLD_LDA
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#if defined(DOUBLE)
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lsl LDA, LDA, #4 // LDA * SIZE * 2
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#else
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lsl LDA, LDA, #3 // LDA * SIZE * 2
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#endif
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cmp INC_X, #1
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bne zgemvn_kernel_S4_BEGIN
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cmp INC_Y, #1
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bne zgemvn_kernel_S4_BEGIN
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zgemvn_kernel_F4_BEGIN:
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ldr YO , Y
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ldr I, M
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asrs I, I, #2 // I = M / 4
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ble zgemvn_kernel_F1_BEGIN
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zgemvn_kernel_F4X4:
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ldr AO1, A
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add AO2, AO1, LDA
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add r3 , AO1, #64
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str r3 , A
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add AO2, AO2, LDA
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add AO2, AO2, LDA
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ldr XO , X
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INIT_F4
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asrs J, N, #2 // J = N / 4
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ble zgemvn_kernel_F4X1
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zgemvn_kernel_F4X4_10:
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KERNEL_F4X4
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subs J, J, #1
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bne zgemvn_kernel_F4X4_10
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zgemvn_kernel_F4X1:
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ands J, N , #3
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ble zgemvn_kernel_F4_END
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zgemvn_kernel_F4X1_10:
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KERNEL_F4X1
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subs J, J, #1
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bne zgemvn_kernel_F4X1_10
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zgemvn_kernel_F4_END:
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SAVE_F4
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subs I , I , #1
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bne zgemvn_kernel_F4X4
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|
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zgemvn_kernel_F1_BEGIN:
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ldr I, M
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ands I, I , #3
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ble zgemvn_kernel_L999
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|
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zgemvn_kernel_F1X1:
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|
|
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ldr AO1, A
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|
add r3, AO1, #16
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|
str r3, A
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|
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ldr XO , X
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|
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|
INIT_F1
|
|
|
|
mov J, N
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|
|
|
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zgemvn_kernel_F1X1_10:
|
|
|
|
KERNEL_F1X1
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|
|
|
subs J, J, #1
|
|
bne zgemvn_kernel_F1X1_10
|
|
|
|
|
|
zgemvn_kernel_F1_END:
|
|
|
|
SAVE_F1
|
|
|
|
subs I , I , #1
|
|
bne zgemvn_kernel_F1X1
|
|
|
|
b zgemvn_kernel_L999
|
|
|
|
|
|
|
|
/*************************************************************************************************************/
|
|
|
|
zgemvn_kernel_S4_BEGIN:
|
|
|
|
#if defined(DOUBLE)
|
|
lsl INC_X, INC_X, #4 // INC_X * SIZE * 2
|
|
lsl INC_Y, INC_Y, #4 // INC_Y * SIZE * 2
|
|
#else
|
|
lsl INC_X, INC_X, #3 // INC_X * SIZE * 2
|
|
lsl INC_Y, INC_Y, #3 // INC_Y * SIZE * 2
|
|
#endif
|
|
|
|
ldr YO , Y
|
|
|
|
ldr I, M
|
|
asrs I, I, #2 // I = M / 4
|
|
ble zgemvn_kernel_S1_BEGIN
|
|
|
|
zgemvn_kernel_S4X4:
|
|
|
|
ldr AO1, A
|
|
add AO2, AO1, LDA
|
|
add r3 , AO1, #64
|
|
str r3 , A
|
|
|
|
ldr XO , X
|
|
|
|
INIT_S4
|
|
|
|
asrs J, N, #2 // J = N / 4
|
|
ble zgemvn_kernel_S4X1
|
|
|
|
|
|
zgemvn_kernel_S4X4_10:
|
|
|
|
KERNEL_S4X4
|
|
|
|
subs J, J, #1
|
|
bne zgemvn_kernel_S4X4_10
|
|
|
|
|
|
zgemvn_kernel_S4X1:
|
|
|
|
ands J, N , #3
|
|
ble zgemvn_kernel_S4_END
|
|
|
|
zgemvn_kernel_S4X1_10:
|
|
|
|
KERNEL_S4X1
|
|
|
|
subs J, J, #1
|
|
bne zgemvn_kernel_S4X1_10
|
|
|
|
|
|
zgemvn_kernel_S4_END:
|
|
|
|
SAVE_S4
|
|
|
|
subs I , I , #1
|
|
bne zgemvn_kernel_S4X4
|
|
|
|
|
|
zgemvn_kernel_S1_BEGIN:
|
|
|
|
ldr I, M
|
|
ands I, I , #3
|
|
ble zgemvn_kernel_L999
|
|
|
|
zgemvn_kernel_S1X1:
|
|
|
|
ldr AO1, A
|
|
add r3, AO1, #16
|
|
str r3, A
|
|
|
|
ldr XO , X
|
|
|
|
INIT_S1
|
|
|
|
mov J, N
|
|
|
|
|
|
zgemvn_kernel_S1X1_10:
|
|
|
|
KERNEL_S1X1
|
|
|
|
subs J, J, #1
|
|
bne zgemvn_kernel_S1X1_10
|
|
|
|
|
|
zgemvn_kernel_S1_END:
|
|
|
|
SAVE_S1
|
|
|
|
subs I , I , #1
|
|
bne zgemvn_kernel_S1X1
|
|
|
|
|
|
/*************************************************************************************************************/
|
|
|
|
zgemvn_kernel_L999:
|
|
|
|
sub r3, fp, #192
|
|
|
|
#if defined(DOUBLE)
|
|
vldm r3, { d8 - d15 } // restore floating point registers
|
|
#else
|
|
vldm r3, { s8 - s15 } // restore floating point registers
|
|
#endif
|
|
|
|
mov r0, #0 // set return value
|
|
|
|
sub sp, fp, #28
|
|
pop {r4 -r9 ,fp}
|
|
bx lr
|
|
|
|
EPILOGUE
|
|
|