783 lines
12 KiB
ArmAsm
783 lines
12 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2013/11/28 Saar
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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*
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**************************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define STACKSIZE 256
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#if !defined(__ARM_PCS_VFP)
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#if !defined(DOUBLE)
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#define OLD_ALPHA r3
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#define OLD_A_SOFTFP [fp, #0 ]
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#define OLD_LDA [fp, #4 ]
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#define X [fp, #8 ]
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#define OLD_INC_X [fp, #12 ]
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#define Y [fp, #16 ]
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#define OLD_INC_Y [fp, #20 ]
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#else
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#define OLD_ALPHA [fp, #0 ]
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#define OLD_A_SOFTFP [fp, #8 ]
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#define OLD_LDA [fp, #12]
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#define X [fp, #16]
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#define OLD_INC_X [fp, #20]
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#define Y [fp, #24]
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#define OLD_INC_Y [fp, #28]
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#endif
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#else
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#define OLD_LDA [fp, #0 ]
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#define X [fp, #4 ]
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#define OLD_INC_X [fp, #8 ]
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#define Y [fp, #12 ]
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#define OLD_INC_Y [fp, #16 ]
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#endif
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#define OLD_A r3
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#define OLD_M r0
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#define AO1 r0
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#define N r1
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#define J r2
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#define AO2 r4
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#define XO r5
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#define YO r6
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#define LDA r7
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#define INC_X r8
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#define INC_Y r9
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#define I r12
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#define FP_ZERO [fp, #-228]
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#define FP_ZERO_0 [fp, #-228]
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#define FP_ZERO_1 [fp, #-224]
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#define M [fp, #-252 ]
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#define A [fp, #-256 ]
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#define X_PRE 64
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#define Y_PRE 0
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#define A_PRE 0
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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#if defined(DOUBLE)
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.macro INIT_F8
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pld [ YO , #Y_PRE ]
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pld [ YO , #Y_PRE+32 ]
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fldd d8 , FP_ZERO
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vmov.f64 d9 , d8
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vmov.f64 d10 , d8
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vmov.f64 d11 , d8
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vmov.f64 d12 , d8
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vmov.f64 d13 , d8
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vmov.f64 d14 , d8
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vmov.f64 d15 , d8
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.endm
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.macro KERNEL_F8X8
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pld [ XO , #X_PRE ]
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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pld [ XO , #X_PRE ]
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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.endm
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.macro KERNEL_F8X1
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pld [ AO2 , #A_PRE ]
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vldmia.f64 XO! , { d2 }
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vldmia.f64 AO1 , { d4 - d7 }
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vmla.f64 d8 , d2 , d4
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pld [ AO2 , #4*SIZE ]
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vmla.f64 d9 , d2 , d5
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add r3, AO1, #4*SIZE
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vmla.f64 d10 , d2 , d6
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vmla.f64 d11 , d2 , d7
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vldmia.f64 r3 , { d4 - d7 }
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vmla.f64 d12 , d2 , d4
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vmla.f64 d13 , d2 , d5
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add AO1, AO1, LDA
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vmla.f64 d14 , d2 , d6
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add AO2, AO2, LDA
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vmla.f64 d15 , d2 , d7
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.endm
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.macro SAVE_F8
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vldmia.f64 YO, { d4 - d7 }
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vmla.f64 d4 , d0, d8
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vmla.f64 d5 , d0, d9
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vmla.f64 d6 , d0, d10
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vmla.f64 d7 , d0, d11
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vstmia.f64 YO!, { d4 - d7 }
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vldmia.f64 YO, { d4 - d7 }
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vmla.f64 d4 , d0, d12
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vmla.f64 d5 , d0, d13
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vmla.f64 d6 , d0, d14
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vmla.f64 d7 , d0, d15
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vstmia.f64 YO!, { d4 - d7 }
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.endm
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.macro INIT_F1
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fldd d12 , FP_ZERO
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.endm
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.macro KERNEL_F1X1
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vldmia.f64 XO! , { d2 }
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vldmia.f64 AO1 , { d8 }
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vmla.f64 d12 , d2 , d8
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add AO1, AO1, LDA
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.endm
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.macro SAVE_F1
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vldmia.f64 YO, { d4 }
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vmla.f64 d4, d0, d12
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vstmia.f64 YO!, { d4 }
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.endm
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/*********************************************************************************************/
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.macro INIT_S4
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fldd d12 , FP_ZERO
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vmov.f64 d13 , d12
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vmov.f64 d14 , d12
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vmov.f64 d15 , d12
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.endm
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.macro KERNEL_S4X4
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KERNEL_S4X1
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KERNEL_S4X1
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KERNEL_S4X1
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KERNEL_S4X1
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.endm
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.macro KERNEL_S4X1
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pld [ AO2 , #A_PRE ]
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vldmia.f64 XO , { d2 }
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vldmia.f64 AO1 , { d8 - d11 }
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vmla.f64 d12 , d2 , d8
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add AO1, AO1, LDA
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vmla.f64 d13 , d2 , d9
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add AO2, AO2, LDA
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vmla.f64 d14 , d2 , d10
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vmla.f64 d15 , d2 , d11
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add XO, XO , INC_X
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.endm
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.macro SAVE_S4
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vldmia.f64 YO, { d4 }
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vmla.f64 d4 , d0, d12
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vstmia.f64 YO, { d4 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d5 }
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vmla.f64 d5 , d0, d13
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vstmia.f64 YO, { d5 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d4 }
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vmla.f64 d4 , d0, d14
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vstmia.f64 YO, { d4 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d5 }
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vmla.f64 d5 , d0, d15
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vstmia.f64 YO, { d5 }
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add YO, YO, INC_Y
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.endm
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.macro INIT_S1
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fldd d12 , FP_ZERO
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.endm
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.macro KERNEL_S1X1
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vldmia.f64 XO , { d2 }
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vldmia.f64 AO1 , { d8 }
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vmla.f64 d12 , d2 , d8
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add AO1, AO1, LDA
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add XO, XO , INC_X
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.endm
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.macro SAVE_S1
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vldmia.f64 YO, { d4 }
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vmla.f64 d4, d0, d12
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vstmia.f64 YO , { d4 }
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add YO, YO, INC_Y
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.endm
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#else /************************* SINGLE PRECISION *****************************************/
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.macro INIT_F8
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pld [ YO , #Y_PRE ]
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flds s8 , FP_ZERO
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vmov.f32 s9 , s8
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vmov.f32 s10 , s8
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vmov.f32 s11 , s8
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vmov.f32 s12 , s8
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vmov.f32 s13 , s8
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vmov.f32 s14 , s8
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vmov.f32 s15 , s8
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.endm
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.macro KERNEL_F8X8
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pld [ XO , #X_PRE ]
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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KERNEL_F8X1
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.endm
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.macro KERNEL_F8X1
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pld [ AO2, #A_PRE ]
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vldmia.f32 XO! , { s2 }
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vldmia.f32 AO1 , { s4 - s7 }
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vmla.f32 s8 , s2 , s4
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vmla.f32 s9 , s2 , s5
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vmla.f32 s10 , s2 , s6
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vmla.f32 s11 , s2 , s7
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add r3, AO1, #4*SIZE
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vldmia.f32 r3 , { s4 - s7 }
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vmla.f32 s12 , s2 , s4
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vmla.f32 s13 , s2 , s5
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vmla.f32 s14 , s2 , s6
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vmla.f32 s15 , s2 , s7
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add AO1, AO1, LDA
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add AO2, AO2, LDA
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.endm
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.macro SAVE_F8
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vldmia.f32 YO, { s4 - s7 }
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vmla.f32 s4 , s0, s8
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vmla.f32 s5 , s0, s9
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vmla.f32 s6 , s0, s10
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vmla.f32 s7 , s0, s11
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vstmia.f32 YO!, { s4 - s7 }
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vldmia.f32 YO, { s4 - s7 }
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vmla.f32 s4 , s0, s12
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vmla.f32 s5 , s0, s13
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vmla.f32 s6 , s0, s14
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vmla.f32 s7 , s0, s15
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vstmia.f32 YO!, { s4 - s7 }
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.endm
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.macro INIT_F1
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flds s12 , FP_ZERO
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.endm
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.macro KERNEL_F1X1
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vldmia.f32 XO! , { s2 }
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vldmia.f32 AO1 , { s8 }
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vmla.f32 s12 , s2 , s8
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add AO1, AO1, LDA
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.endm
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.macro SAVE_F1
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vldmia.f32 YO, { s4 }
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vmla.f32 s4, s0, s12
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vstmia.f32 YO!, { s4 }
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.endm
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/*********************************************************************************************/
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.macro INIT_S4
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flds s12 , FP_ZERO
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vmov.f32 s13 , s12
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vmov.f32 s14 , s12
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vmov.f32 s15 , s12
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.endm
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.macro KERNEL_S4X4
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pld [ AO2 , #A_PRE ]
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KERNEL_S4X1
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KERNEL_S4X1
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pld [ AO2 , #A_PRE ]
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KERNEL_S4X1
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KERNEL_S4X1
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.endm
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.macro KERNEL_S4X1
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vldmia.f32 XO , { s2 }
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vldmia.f32 AO1 , { s8 - s11 }
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vmla.f32 s12 , s2 , s8
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vmla.f32 s13 , s2 , s9
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vmla.f32 s14 , s2 , s10
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vmla.f32 s15 , s2 , s11
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add AO1, AO1, LDA
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add AO2, AO2, LDA
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add XO, XO , INC_X
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.endm
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.macro SAVE_S4
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vldmia.f32 YO, { s4 }
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vmla.f32 s4 , s0, s12
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vstmia.f32 YO, { s4 }
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add YO, YO, INC_Y
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vldmia.f32 YO, { s5 }
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vmla.f32 s5 , s0, s13
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vstmia.f32 YO, { s5 }
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add YO, YO, INC_Y
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vldmia.f32 YO, { s4 }
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vmla.f32 s4 , s0, s14
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vstmia.f32 YO, { s4 }
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add YO, YO, INC_Y
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vldmia.f32 YO, { s5 }
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vmla.f32 s5 , s0, s15
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vstmia.f32 YO, { s5 }
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add YO, YO, INC_Y
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.endm
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.macro INIT_S1
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flds s12 , FP_ZERO
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.endm
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.macro KERNEL_S1X1
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vldmia.f32 XO , { s2 }
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vldmia.f32 AO1 , { s8 }
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vmla.f32 s12 , s2 , s8
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add AO1, AO1, LDA
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add XO, XO , INC_X
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.endm
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.macro SAVE_S1
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vldmia.f32 YO, { s4 }
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vmla.f32 s4, s0, s12
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vstmia.f32 YO , { s4 }
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add YO, YO, INC_Y
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.endm
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#endif
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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push {r4 - r9 , fp}
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add fp, sp, #28
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sub sp, sp, #STACKSIZE // reserve stack
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sub r12, fp, #192
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#if defined(DOUBLE)
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vstm r12, { d8 - d15 } // store floating point registers
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#else
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vstm r12, { s8 - s15 } // store floating point registers
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#endif
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movs r12, #0
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str r12, FP_ZERO
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str r12, FP_ZERO_1
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cmp OLD_M, #0
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ble gemvn_kernel_L999
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cmp N, #0
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ble gemvn_kernel_L999
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#if !defined(__ARM_PCS_VFP)
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#if !defined(DOUBLE)
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vmov s0, OLD_ALPHA
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#else
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vldr d0, OLD_ALPHA
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#endif
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ldr OLD_A, OLD_A_SOFTFP
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#endif
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str OLD_A, A
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str OLD_M, M
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ldr INC_X , OLD_INC_X
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ldr INC_Y , OLD_INC_Y
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cmp INC_X, #0
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beq gemvn_kernel_L999
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cmp INC_Y, #0
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beq gemvn_kernel_L999
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ldr LDA, OLD_LDA
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#if defined(DOUBLE)
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lsl LDA, LDA, #3 // LDA * SIZE
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#else
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lsl LDA, LDA, #2 // LDA * SIZE
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#endif
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cmp INC_X, #1
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bne gemvn_kernel_S4_BEGIN
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cmp INC_Y, #1
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bne gemvn_kernel_S4_BEGIN
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gemvn_kernel_F4_BEGIN:
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ldr YO , Y
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ldr I, M
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asrs I, I, #3 // I = M / 8
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ble gemvn_kernel_F1_BEGIN
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gemvn_kernel_F4X4:
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ldr AO1, A
|
|
add AO2, AO1, LDA
|
|
add r3 , AO1, #8*SIZE
|
|
str r3 , A
|
|
|
|
add AO2, AO2, LDA
|
|
add AO2, AO2, LDA
|
|
|
|
ldr XO , X
|
|
|
|
INIT_F8
|
|
|
|
asrs J, N, #3 // J = N / 8
|
|
ble gemvn_kernel_F4X1
|
|
|
|
|
|
gemvn_kernel_F4X4_10:
|
|
|
|
KERNEL_F8X8
|
|
|
|
subs J, J, #1
|
|
bne gemvn_kernel_F4X4_10
|
|
|
|
|
|
gemvn_kernel_F4X1:
|
|
|
|
ands J, N , #7
|
|
ble gemvn_kernel_F4_END
|
|
|
|
gemvn_kernel_F4X1_10:
|
|
|
|
KERNEL_F8X1
|
|
|
|
subs J, J, #1
|
|
bne gemvn_kernel_F4X1_10
|
|
|
|
|
|
gemvn_kernel_F4_END:
|
|
|
|
SAVE_F8
|
|
|
|
subs I , I , #1
|
|
bne gemvn_kernel_F4X4
|
|
|
|
|
|
gemvn_kernel_F1_BEGIN:
|
|
|
|
ldr I, M
|
|
ands I, I , #7
|
|
ble gemvn_kernel_L999
|
|
|
|
gemvn_kernel_F1X1:
|
|
|
|
ldr AO1, A
|
|
add r3, AO1, #SIZE
|
|
str r3, A
|
|
|
|
ldr XO , X
|
|
|
|
INIT_F1
|
|
|
|
mov J, N
|
|
|
|
|
|
gemvn_kernel_F1X1_10:
|
|
|
|
KERNEL_F1X1
|
|
|
|
subs J, J, #1
|
|
bne gemvn_kernel_F1X1_10
|
|
|
|
|
|
gemvn_kernel_F1_END:
|
|
|
|
SAVE_F1
|
|
|
|
subs I , I , #1
|
|
bne gemvn_kernel_F1X1
|
|
|
|
b gemvn_kernel_L999
|
|
|
|
|
|
|
|
/*************************************************************************************************************/
|
|
|
|
gemvn_kernel_S4_BEGIN:
|
|
|
|
#if defined(DOUBLE)
|
|
lsl INC_X, INC_X, #3 // INC_X * SIZE
|
|
lsl INC_Y, INC_Y, #3 // INC_Y * SIZE
|
|
#else
|
|
lsl INC_X, INC_X, #2 // INC_X * SIZE
|
|
lsl INC_Y, INC_Y, #2 // INC_Y * SIZE
|
|
#endif
|
|
|
|
ldr YO , Y
|
|
|
|
ldr I, M
|
|
asrs I, I, #2 // I = M / 4
|
|
ble gemvn_kernel_S1_BEGIN
|
|
|
|
gemvn_kernel_S4X4:
|
|
|
|
ldr AO1, A
|
|
add AO2, AO1, LDA
|
|
add r3 , AO1, #4*SIZE
|
|
str r3 , A
|
|
|
|
ldr XO , X
|
|
|
|
INIT_S4
|
|
|
|
asrs J, N, #2 // J = N / 4
|
|
ble gemvn_kernel_S4X1
|
|
|
|
|
|
gemvn_kernel_S4X4_10:
|
|
|
|
KERNEL_S4X4
|
|
|
|
subs J, J, #1
|
|
bne gemvn_kernel_S4X4_10
|
|
|
|
|
|
gemvn_kernel_S4X1:
|
|
|
|
ands J, N , #3
|
|
ble gemvn_kernel_S4_END
|
|
|
|
gemvn_kernel_S4X1_10:
|
|
|
|
KERNEL_S4X1
|
|
|
|
subs J, J, #1
|
|
bne gemvn_kernel_S4X1_10
|
|
|
|
|
|
gemvn_kernel_S4_END:
|
|
|
|
SAVE_S4
|
|
|
|
subs I , I , #1
|
|
bne gemvn_kernel_S4X4
|
|
|
|
|
|
gemvn_kernel_S1_BEGIN:
|
|
|
|
ldr I, M
|
|
ands I, I , #3
|
|
ble gemvn_kernel_L999
|
|
|
|
gemvn_kernel_S1X1:
|
|
|
|
ldr AO1, A
|
|
add r3, AO1, #SIZE
|
|
str r3, A
|
|
|
|
ldr XO , X
|
|
|
|
INIT_S1
|
|
|
|
mov J, N
|
|
|
|
|
|
gemvn_kernel_S1X1_10:
|
|
|
|
KERNEL_S1X1
|
|
|
|
subs J, J, #1
|
|
bne gemvn_kernel_S1X1_10
|
|
|
|
|
|
gemvn_kernel_S1_END:
|
|
|
|
SAVE_S1
|
|
|
|
subs I , I , #1
|
|
bne gemvn_kernel_S1X1
|
|
|
|
|
|
/*************************************************************************************************************/
|
|
|
|
gemvn_kernel_L999:
|
|
|
|
sub r3, fp, #192
|
|
|
|
#if defined(DOUBLE)
|
|
vldm r3, { d8 - d15 } // restore floating point registers
|
|
#else
|
|
vldm r3, { s8 - s15 } // restore floating point registers
|
|
#endif
|
|
|
|
mov r0, #0 // set return value
|
|
|
|
sub sp, fp, #28
|
|
pop {r4 -r9 ,fp}
|
|
bx lr
|
|
|
|
EPILOGUE
|
|
|