429 lines
10 KiB
ArmAsm
429 lines
10 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r12
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#define t1 $r13
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#define t2 $r15
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#define t3 $r18
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#define t4 $r16
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#define i0 $r17
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#define i1 $r14
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#define TEMP $r19
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#define x1 $vr9
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#define x2 $vr10
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#define x3 $vr11
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#define x4 $vr12
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#define VX0 $vr13
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#define VX1 $vr14
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#define VM0 $vr15
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#define VM1 $vr16
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#define VI0 $vr20
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#define VI1 $vr21
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#define VI2 $vr22
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#define VI3 $vr8
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#define VI4 $vr19
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#define VT0 $vr23
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PROLOGUE
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li.d i0, 0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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li.d TEMP, 1
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slli.d TEMP, TEMP, BASE_SHIFT
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slli.d INCX, INCX, BASE_SHIFT
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bne INCX, TEMP, .L20
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vld VM0, X, 0
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#ifdef DOUBLE
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addi.d i0, i0, 1
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srai.d I, N, 3
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bge $r0, I, .L21
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slli.d i0, i0, 1 //2
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vreplgr2vr.d $vr17, i0
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slli.d i0, i0, 1 //4
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vreplgr2vr.d $vr18, i0
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addi.d i0, i0, -7
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vinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
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addi.d i0, i0, 1
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vinsgr2vr.d VI1, i0, 1
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addi.d i0, i0, 3
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vinsgr2vr.d VI0, i0, 0 //1
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addi.d i0, i0, 1
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vinsgr2vr.d VI0, i0, 1 //2
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#else
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addi.w i0, i0, 1
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srai.d I, N, 3
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bge $r0, I, .L21
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slli.w i0, i0, 2 //4
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vreplgr2vr.w $vr17, i0
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slli.w i0, i0, 1 //8
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vreplgr2vr.w $vr18, i0
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addi.w i0, i0, -15
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vinsgr2vr.w VI1, i0, 0 //initialize the index value for vectorization
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addi.w i0, i0, 1
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vinsgr2vr.w VI1, i0, 1
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addi.w i0, i0, 1
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vinsgr2vr.w VI1, i0, 2
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addi.w i0, i0, 1
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vinsgr2vr.w VI1, i0, 3
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addi.w i0, i0, 5
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vinsgr2vr.w VI0, i0, 0 //1
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addi.w i0, i0, 1
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vinsgr2vr.w VI0, i0, 1 //2
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addi.w i0, i0, 1
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vinsgr2vr.w VI0, i0, 2 //3
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addi.w i0, i0, 1
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vinsgr2vr.w VI0, i0, 3 //4
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#endif
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.align 3
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.L10:
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vld VX0, X, 0 * SIZE
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#ifdef DOUBLE
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vadd.d VI1, VI1, $vr18
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vld VX1, X, 2 * SIZE
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vadd.d VI2, VI1, $vr17
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VCMPLT VT0, VX1, VX0
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vbitsel.v x1, VX0, VX1, VT0
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vbitsel.v x2, VI1, VI2, VT0
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vld VX0, X, 4 * SIZE
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vadd.d VI1, VI2, $vr17
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vld VX1, X, 6 * SIZE
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vadd.d VI2, VI1, $vr17
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VCMPLT VT0, VX1, VX0
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addi.d I, I, -1
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vbitsel.v x3, VX0, VX1, VT0
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vbitsel.v x4, VI1, VI2, VT0
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VCMPLT VT0, x3, x1
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addi.d X, X, 8 * SIZE
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vbitsel.v x1, x1, x3, VT0
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vbitsel.v x2, x2, x4, VT0
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VCMPLT VT0, x1, VM0
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vbitsel.v VM0, VM0, x1, VT0
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vbitsel.v VI0, VI0, x2, VT0
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#else
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vadd.w VI1, VI1, $vr18
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vld VX1, X, 4 * SIZE
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vadd.w VI2, VI1, $vr17
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VCMPLT VT0, VX1, VX0
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addi.d I, I, -1
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vbitsel.v VM1, VX0, VX1, VT0
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vbitsel.v VI2, VI1, VI2, VT0
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VCMPLT VT0, VM1, VM0
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addi.d X, X, 8 * SIZE
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vbitsel.v VM0, VM0, VM1, VT0
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vbitsel.v VI0, VI0, VI2, VT0
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#endif
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blt $r0, I, .L10
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.align 3
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.L15:
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#ifdef DOUBLE
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vreplvei.d VI1, VI0, 0
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vreplvei.d VI2, VI0, 1
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vreplvei.d x1, VM0, 0
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vreplvei.d x2, VM0, 1
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fcmp.ceq.d $fcc0, $f10, $f9
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bceqz $fcc0, .L26
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VCMPLT VT0, VI1, VI2
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vbitsel.v VI0, VI2, VI1, VT0
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b .L27
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#else
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vreplvei.w VI1, VI0, 0
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vreplvei.w VI2, VI0, 1
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vreplvei.w VI3, VI0, 2
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vreplvei.w VI4, VI0, 3
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vreplvei.w x1, VM0, 0
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vreplvei.w x2, VM0, 1
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vreplvei.w x3, VM0, 2
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vreplvei.w x4, VM0, 3
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VCMPLT VT0, x2, x1
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vbitsel.v VM1, x1, x2, VT0
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vbitsel.v $vr17, VI1, VI2, VT0
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VCMPLT VT0, x4, x3
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vbitsel.v VM0, x3, x4, VT0
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vbitsel.v $vr18, VI3, VI4, VT0
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VCMPLT VT0, VM1, VM0
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vbitsel.v VM0, VM0, VM1, VT0
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vbitsel.v VI0, $vr18, $vr17, VT0
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fcmp.ceq.d $fcc0, $f15, $f9
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bceqz $fcc0, .L26
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VCMPLT VT0, VI1, VI0
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vbitsel.v VI0, VI0, VI1, VT0
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b .L26
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#endif
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.align 3
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.L20: // INCX!=1
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move TEMP, X
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#ifdef DOUBLE
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addi.d i0, i0, 1
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ld.d t1, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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vinsgr2vr.d VM0, t1, 0
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srai.d I, N, 3
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bge $r0, I, .L21
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ld.d t2, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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vinsgr2vr.d VM0, t2, 1
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slli.d i0, i0, 1 //2
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vreplgr2vr.d $vr17, i0
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slli.d i0, i0, 1 //4
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vreplgr2vr.d $vr18, i0
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addi.d i0, i0, -7
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vinsgr2vr.d VI1, i0, 0 //initialize the index value for vectorization
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addi.d i0, i0, 1
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vinsgr2vr.d VI1, i0, 1
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addi.d i0, i0, 3
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vinsgr2vr.d VI0, i0, 0 //1
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addi.d i0, i0, 1
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vinsgr2vr.d VI0, i0, 1 //2
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#else
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addi.w i0, i0, 1
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ld.w t1, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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vinsgr2vr.w VM0, t1, 0
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srai.d I, N, 3
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bge $r0, I, .L21
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ld.w t2, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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ld.w t3, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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ld.w t4, TEMP, 0 * SIZE
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add.d TEMP, TEMP, INCX
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vinsgr2vr.w VM0, t2, 1
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vinsgr2vr.w VM0, t3, 2
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vinsgr2vr.w VM0, t4, 3
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slli.w i0, i0, 2 //4
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vreplgr2vr.w $vr17, i0
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slli.w i0, i0, 1 //8
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vreplgr2vr.w $vr18, i0
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addi.w i0, i0, -15
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vinsgr2vr.w VI1, i0, 0 //initialize the index value for vectorization
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addi.w i0, i0, 1
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vinsgr2vr.w VI1, i0, 1
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addi.w i0, i0, 1
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vinsgr2vr.w VI1, i0, 2
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addi.w i0, i0, 1
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vinsgr2vr.w VI1, i0, 3
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addi.w i0, i0, 5
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vinsgr2vr.w VI0, i0, 0 //1
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addi.w i0, i0, 1
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vinsgr2vr.w VI0, i0, 1 //2
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addi.w i0, i0, 1
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vinsgr2vr.w VI0, i0, 2 //3
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addi.w i0, i0, 1
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vinsgr2vr.w VI0, i0, 3 //4
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#endif
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.align 3
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.L24:
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#ifdef DOUBLE
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX0, t1, 0
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vinsgr2vr.d VX0, t2, 1
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vadd.d VI1, VI1, $vr18
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX1, t1, 0
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vinsgr2vr.d VX1, t2, 1
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vadd.d VI2, VI1, $vr17
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VCMPLT VT0, VX1, VX0
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vbitsel.v x1, VX0, VX1, VT0
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vbitsel.v x2, VI1, VI2, VT0
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX0, t1, 0
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vinsgr2vr.d VX0, t2, 1
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vadd.d VI1, VI2, $vr17
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ld.d t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.d t2, X, 0 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX1, t1, 0
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vinsgr2vr.d VX1, t2, 1
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vadd.d VI2, VI1, $vr17
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VCMPLT VT0, VX1, VX0
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vbitsel.v x3, VX0, VX1, VT0
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vbitsel.v x4, VI1, VI2, VT0
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VCMPLT VT0, x3, x1
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vbitsel.v x1, x1, x3, VT0
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vbitsel.v x2, x2, x4, VT0
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VCMPLT VT0, x1, VM0
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addi.d I, I, -1
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vbitsel.v VM0, VM0, x1, VT0
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vbitsel.v VI0, VI0, x2, VT0
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#else
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ld.w t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t4, X, 0 * SIZE
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add.d X, X, INCX
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vinsgr2vr.w VX0, t1, 0
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vinsgr2vr.w VX0, t2, 1
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vinsgr2vr.w VX0, t3, 2
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vinsgr2vr.w VX0, t4, 3
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vadd.w VI1, VI1, $vr18
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ld.w t1, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t2, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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add.d X, X, INCX
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ld.w t4, X, 0 * SIZE
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add.d X, X, INCX
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vinsgr2vr.w VX1, t1, 0
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vinsgr2vr.w VX1, t2, 1
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vinsgr2vr.w VX1, t3, 2
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vinsgr2vr.w VX1, t4, 3
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vadd.w VI2, VI1, $vr17
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VCMPLT VT0, VX1, VX0
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addi.d I, I, -1
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vbitsel.v VM1, VX0, VX1, VT0
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vbitsel.v VI2, VI1, VI2, VT0
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VCMPLT VT0, VM1, VM0
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vbitsel.v VM0, VM0, VM1, VT0
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vbitsel.v VI0, VI0, VI2, VT0
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#endif
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blt $r0, I, .L24
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.align 3
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.L25:
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#ifdef DOUBLE
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vreplvei.d VI1, VI0, 0
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vreplvei.d VI2, VI0, 1
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vreplvei.d x1, VM0, 0
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vreplvei.d x2, VM0, 1
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fcmp.ceq.d $fcc0, $f10, $f9
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bceqz $fcc0, .L26
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VCMPLT VT0, VI1, VI2
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vbitsel.v VI0, VI2, VI1, VT0
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b .L27
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#else
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vreplvei.w VI1, VI0, 0
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vreplvei.w VI2, VI0, 1
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vreplvei.w VI3, VI0, 2
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vreplvei.w VI4, VI0, 3
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vreplvei.w x1, VM0, 0
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vreplvei.w x2, VM0, 1
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vreplvei.w x3, VM0, 2
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vreplvei.w x4, VM0, 3
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VCMPLT VT0, x2, x1
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vbitsel.v VM1, x1, x2, VT0
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vbitsel.v $vr17, VI1, VI2, VT0
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VCMPLT VT0, x4, x3
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vbitsel.v VM0, x3, x4, VT0
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vbitsel.v $vr18, VI3, VI4, VT0
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VCMPLT VT0, VM1, VM0
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vbitsel.v VM0, VM0, VM1, VT0
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vbitsel.v VI0, $vr18, $vr17, VT0
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fcmp.ceq.d $fcc0, $f15, $f9
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bceqz $fcc0, .L26
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VCMPLT VT0, VI1, VI0
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vbitsel.v VI0, VI0, VI1, VT0
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#endif
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.align 3
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.L26:
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#ifdef DOUBLE
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VCMPLT VT0, x2, x1
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vbitsel.v VM0, x1, x2, VT0
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vbitsel.v VI0, VI1, VI2, VT0
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#else
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fcmp.ceq.d $fcc0, $f15, $f10
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bceqz $fcc0, .L27
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VCMPLT VT0, VI2, VI0
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vbitsel.v VI0, VI0, VI2, VT0
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#endif
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.align 3
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.L27:
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#ifndef DOUBLE
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fcmp.ceq.d $fcc0, $f15, $f11
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bceqz $fcc0, .L28
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VCMPLT VT0, VI3, VI0
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vbitsel.v VI0, VI0, VI3, VT0
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.align 3
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.L28:
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fcmp.ceq.d $fcc0, $f15, $f12
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bceqz $fcc0, .L29
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VCMPLT VT0, VI4, VI0
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vbitsel.v VI0, VI0, VI4, VT0
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.align 3
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.L29:
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#endif
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MTG i0, $f20
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.align 3
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.L21: //N<8
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andi I, N, 7
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bge $r0, I, .L999
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srai.d i1, N, 3
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slli.d i1, i1, 3
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addi.d i1, i1, 1 //current index
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movgr2fr.d $f21, i1
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movgr2fr.d $f20, i0
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.align 3
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.L22:
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fld.d $f9, X, 0
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addi.d I, I, -1
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CMPLT $fcc0, $f9, $f15
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add.d X, X, INCX
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fsel $f15, $f15, $f9, $fcc0
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fsel $f20, $f20, $f21, $fcc0
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addi.d i1, i1, 1
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movgr2fr.d $f21, i1
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blt $r0, I, .L22
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MTG i0, $f20
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.align 3
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.L999:
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move $r4, $r17
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jirl $r0, $r1, 0x0
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.align 3
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EPILOGUE
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