286 lines
8.9 KiB
ArmAsm
286 lines
8.9 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#include "loongarch64_asm.S"
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/* Function parameters */
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#define M $r4 // param 1: m
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#define N $r5 // param 2: n
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#define SRC $r6 // param 3: src
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#define LDA $r7 // param 4: lda
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#define DST $r8 // param 5: dst
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#define I $r9
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#define J $r10
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#define S1 $r12
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#define S2 $r13
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#define S3 $r14
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#define S4 $r15
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#define S5 $r16
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#define S6 $r17
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#define S7 $r18
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#define S8 $r19
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#define TD $r20
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#define TS $r21
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#define TL $r7
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#define T0 $r6
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#define ZERO $r0
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#define F0 $f0
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#define F1 $f1
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#define F2 $f2
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#define F3 $f3
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#define F4 $f4
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#define F5 $f5
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#define F6 $f6
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#define F7 $f7
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/* LSX vectors */
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#define U0 $vr0
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#define U1 $vr1
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#define U2 $vr2
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#define U3 $vr3
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#define U4 $vr4
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#define U5 $vr5
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#define U6 $vr6
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#define U7 $vr7
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#define D0 $vr8
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#define D1 $vr9
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#define D2 $vr10
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#define D3 $vr11
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#define D4 $vr12
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#define D5 $vr13
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#define D6 $vr14
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#define D7 $vr15
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PROLOGUE
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push_if_used 0, 0
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move TD, DST
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move TS, SRC
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slli.d TL, LDA, 0x03
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slli.d T0, TL, 0x01
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srai.d J, N, 0x03
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beq J, ZERO, .L_N4
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.L_J1:
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move S1, TS
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add.d S2, TS, TL
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srai.d I, M, 0x03
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add.d S3, S2, TL
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addi.d J, J, -1
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add.d S4, S3, TL
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add.d S5, S3, T0
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add.d S6, S4, T0
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add.d S7, S5, T0
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add.d S8, S6, T0
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add.d TS, S7, T0
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beq I, ZERO, .L_I7
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.L_I1:
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GLD v, , U0, S1, 0x00, U1, S2, 0x00, U2, S3, 0x00, U3, S4, 0x00, \
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U4, S5, 0x00, U5, S6, 0x00, U6, S7, 0x00, U7, S8, 0x00
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GINTERLACE v, d, D0, D4, U1, U0
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GINTERLACE v, d, D1, D5, U3, U2
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GINTERLACE v, d, D2, D6, U5, U4
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GINTERLACE v, d, D3, D7, U7, U6
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GST v, , D0, TD, 0x00, D1, TD, 0x10, D2, TD, 0x20, D3, TD, 0x30, \
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D4, TD, 0x40, D5, TD, 0x50, D6, TD, 0x60, D7, TD, 0x70
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addi.d TD, TD, 0x80
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GLD v, , U0, S1, 0x10, U1, S2, 0x10, U2, S3, 0x10, U3, S4, 0x10, \
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U4, S5, 0x10, U5, S6, 0x10, U6, S7, 0x10, U7, S8, 0x10
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GINTERLACE v, d, D0, D4, U1, U0
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GINTERLACE v, d, D1, D5, U3, U2
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GINTERLACE v, d, D2, D6, U5, U4
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GINTERLACE v, d, D3, D7, U7, U6
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GST v, , D0, TD, 0x00, D1, TD, 0x10, D2, TD, 0x20, D3, TD, 0x30, \
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D4, TD, 0x40, D5, TD, 0x50, D6, TD, 0x60, D7, TD, 0x70
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addi.d TD, TD, 0x80
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GLD v, , U0, S1, 0x20, U1, S2, 0x20, U2, S3, 0x20, U3, S4, 0x20, \
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U4, S5, 0x20, U5, S6, 0x20, U6, S7, 0x20, U7, S8, 0x20
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GINTERLACE v, d, D0, D4, U1, U0
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GINTERLACE v, d, D1, D5, U3, U2
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GINTERLACE v, d, D2, D6, U5, U4
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GINTERLACE v, d, D3, D7, U7, U6
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GST v, , D0, TD, 0x00, D1, TD, 0x10, D2, TD, 0x20, D3, TD, 0x30, \
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D4, TD, 0x40, D5, TD, 0x50, D6, TD, 0x60, D7, TD, 0x70
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addi.d TD, TD, 0x80
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GLD v, , U0, S1, 0x30, U1, S2, 0x30, U2, S3, 0x30, U3, S4, 0x30, \
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U4, S5, 0x30, U5, S6, 0x30, U6, S7, 0x30, U7, S8, 0x30
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GINTERLACE v, d, D0, D4, U1, U0
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GINTERLACE v, d, D1, D5, U3, U2
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GINTERLACE v, d, D2, D6, U5, U4
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GINTERLACE v, d, D3, D7, U7, U6
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GST v, , D0, TD, 0x00, D1, TD, 0x10, D2, TD, 0x20, D3, TD, 0x30, \
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D4, TD, 0x40, D5, TD, 0x50, D6, TD, 0x60, D7, TD, 0x70
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addi.d TD, TD, 0x80
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addi.d S1, S1, 0x40
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addi.d S2, S2, 0x40
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addi.d S3, S3, 0x40
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addi.d S4, S4, 0x40
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addi.d S5, S5, 0x40
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addi.d S6, S6, 0x40
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addi.d S7, S7, 0x40
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addi.d S8, S8, 0x40
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addi.d I, I, -1
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blt ZERO, I, .L_I1
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.L_I7:
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andi I, M, 0x07
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beq I, ZERO, .L_I0
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.L_II1: /* I-- */
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fld.d F0, S1, 0x00
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fld.d F1, S2, 0x00
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fld.d F2, S3, 0x00
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fld.d F3, S4, 0x00
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fld.d F4, S5, 0x00
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fld.d F5, S6, 0x00
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fld.d F6, S7, 0x00
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fld.d F7, S8, 0x00
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fst.d F0, TD, 0x00
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addi.d S1, S1, 0x08
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fst.d F1, TD, 0x08
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addi.d S2, S2, 0x08
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fst.d F2, TD, 0x10
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addi.d S3, S3, 0x08
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fst.d F3, TD, 0x18
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addi.d S4, S4, 0x08
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fst.d F4, TD, 0x20
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addi.d S5, S5, 0x08
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fst.d F5, TD, 0x28
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addi.d S6, S6, 0x08
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fst.d F6, TD, 0x30
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addi.d S7, S7, 0x08
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fst.d F7, TD, 0x38
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addi.d S8, S8, 0x08
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addi.d TD, TD, 0x40
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addi.d I, I, -1
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blt ZERO, I, .L_II1
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.L_I0:
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blt ZERO, J, .L_J1
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.L_N4:
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andi J, N, 0x04
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beq ZERO, J, .L_N2
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move S1, TS
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add.d S2, TS, TL
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srai.d I, M, 0x02
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add.d S3, S2, TL
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add.d S4, S2, T0
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add.d TS, S3, T0
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beq I, ZERO, .L_I3
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.L_4I1: /* I-- */
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GLD v, , U0, S1, 0x00, U1, S2, 0x00, U2, S3, 0x00, U3, S4, 0x00
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GINTERLACE v, d, D0, D2, U1, U0
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GINTERLACE v, d, D1, D3, U3, U2
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GST v, , D0, TD, 0x00, D1, TD, 0x10, D2, TD, 0x20, D3, TD, 0x30
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addi.d TD, TD, 0x40
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GLD v, , U0, S1, 0x10, U1, S2, 0x10, U2, S3, 0x10, U3, S4, 0x10
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GINTERLACE v, d, D0, D2, U1, U0
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GINTERLACE v, d, D1, D3, U3, U2
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GST v, , D0, TD, 0x00, D1, TD, 0x10, D2, TD, 0x20, D3, TD, 0x30
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addi.d S1, S1, 0x20
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addi.d S2, S2, 0x20
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addi.d S3, S3, 0x20
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addi.d S4, S4, 0x20
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addi.d TD, TD, 0x40
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addi.d I, I, -1
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blt ZERO, I, .L_4I1
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.L_I3:
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andi I, M, 0x03
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beq I, ZERO, .L_N2
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.L_4II1:
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fld.d F0, S1, 0x00
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fld.d F1, S2, 0x00
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fld.d F2, S3, 0x00
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fld.d F3, S4, 0x00
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fst.d F0, TD, 0x00
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addi.d S1, S1, 0x08
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fst.d F1, TD, 0x08
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addi.d S2, S2, 0x08
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fst.d F2, TD, 0x10
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addi.d S3, S3, 0x08
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fst.d F3, TD, 0x18
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addi.d S4, S4, 0x08
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addi.d TD, TD, 0x20
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addi.d I, I, -1
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blt ZERO, I, .L_4II1
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.L_N2:
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andi J, N, 0x02
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beq ZERO, J, .L_N1
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move S1, TS
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add.d S2, TS, TL
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srai.d I, M, 0x01
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add.d TS, S2, TL
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beq I, ZERO, .L_NI1
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.L_2I1: /* I-- */
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GLD v, , U0, S1, 0x00, U1, S2, 0x00
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GINTERLACE v, d, D0, D1, U1, U0
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GST v, , D0, TD, 0x00, D1, TD, 0x10
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addi.d S1, S1, 0x10
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addi.d S2, S2, 0x10
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addi.d TD, TD, 0x20
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addi.d I, I, -1
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blt ZERO, I, .L_2I1
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.L_NI1:
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andi I, M, 0x01
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beq I, ZERO, .L_N1
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fld.d F0, S1, 0x00
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fld.d F1, S2, 0x00
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fst.d F0, TD, 0x00
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addi.d S1, S1, 0x08
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fst.d F1, TD, 0x08
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addi.d S2, S2, 0x08
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addi.d TD, TD, 0x10
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.L_N1:
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andi J, N, 0x01
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beq ZERO, J, .L_N0
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move S1, TS
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beq ZERO, M, .L_N0
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.L_M1:
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fld.d F0, S1, 0x00
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addi.d S1, S1, 0x08
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fst.d F0, TD, 0x00
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addi.d TD, TD, 0x08
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addi.d M, M, -1
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blt ZERO, M, .L_M1
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.L_N0:
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pop_if_used 0, 0
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jirl $r0, $r1, 0x00
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EPILOGUE
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