341 lines
8.7 KiB
ArmAsm
341 lines
8.7 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2024, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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/* Function parameters */
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#define M $r4 // param 1: m
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#define N $r5 // param 2: n
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#define SRC $r6 // param 3: src
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#define LDA $r7 // param 4: lda
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#define DST $r8 // param 5: dst
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#define I $r9
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#define J $r10
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#define S1 $r12
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#define S2 $r13
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#define S3 $r14
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#define S4 $r15
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#define S5 $r16
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#define S6 $r17
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#define S7 $r18
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#define TD $r20
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#define TS $r11
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#define TL $r19
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#define T0 $r23
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#define ZERO $r0
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#define F0 $f0
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#define F1 $f1
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#define F2 $f2
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#define F3 $f3
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#define F4 $f4
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#define F5 $f5
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#define F6 $f6
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#define F7 $f7
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/* LSX vectors */
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#define U0 $vr0
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#define U1 $vr1
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#define U2 $vr2
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#define U3 $vr3
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#define U4 $vr4
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#define U5 $vr5
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#define U6 $vr6
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#define U7 $vr7
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#define D0 $vr8
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#define D1 $vr9
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#define D2 $vr10
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#define D3 $vr11
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#define D4 $vr12
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#define D5 $vr13
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#define D6 $vr14
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#define D7 $vr15
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#define D8 $vr16
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PROLOGUE
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addi.d $sp, $sp, -8
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SDARG $r23, $sp, 0
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move TD, DST //boffset
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move TS, SRC //aoffset
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slli.d TL, LDA, 0x02
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slli.d TL, TL, 0x01
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srai.d J, N, 0x02
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beq J, ZERO, .L_N0
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.L_J1: /* J-- */
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move S1, TS
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add.d S2, S1, TL
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add.d S3, S2, TL
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add.d S4, S3, TL
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slli.d T0, TL, 0x02
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add.d TS, TS, T0
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srai.d I, M, 0x02
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beq I, ZERO, .L_I3
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.L_I1: /* I-- */
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vld U0, S1, 0x00
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vld U1, S1, 0x10
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vld U2, S2, 0x00
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vld U3, S2, 0x10
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vld U4, S3, 0x00
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vld U5, S3, 0x10
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vld U6, S4, 0x00
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vld U7, S4, 0x10
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vand.v D0, U2, U2
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vand.v D1, U3, U3
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vand.v D2, U2, U2
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vand.v D3, U3, U3
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vand.v D4, U6, U6
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vand.v D5, U7, U7
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vand.v D6, U6, U6
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vand.v D7, U7, U7
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vpermi.w D0, U0, 0x44
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vpermi.w D4, U4, 0x44
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vpermi.w D2, U0, 0xee
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vpermi.w D6, U4, 0xee
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vpermi.w D1, U1, 0x44
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vpermi.w D5, U5, 0x44
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vpermi.w D3, U1, 0xee
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vpermi.w D7, U5, 0xee
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vst D0, TD, 0x00
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vst D4, TD, 0x10
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vst D2, TD, 0x20
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vst D6, TD, 0x30
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vst D1, TD, 0x40
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vst D5, TD, 0x50
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vst D3, TD, 0x60
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vst D7, TD, 0x70
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addi.d S1, S1, 0x20 // a_offset
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addi.d S2, S2, 0x20
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addi.d S3, S3, 0x20
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addi.d S4, S4, 0x20
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addi.d TD, TD, 0x80 // b_offset
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addi.d I, I, -1
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blt ZERO, I, .L_I1
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.L_I3: /* if(m&2) */
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andi I, M, 0x02
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beq I, ZERO, .L_II20
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vld U0, S1, 0x00
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vld U1, S2, 0x00
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vld U2, S3, 0x00
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vld U3, S4, 0x00
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vand.v D0, U1, U1
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vand.v D1, U1, U1
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vand.v D2, U3, U3
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vand.v D3, U3, U3
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vpermi.w D0, U0, 0x44
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vpermi.w D2, U2, 0x44
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vpermi.w D1, U0, 0xee
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vpermi.w D3, U2, 0xee
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vst D0, TD, 0x00
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vst D2, TD, 0x10
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vst D1, TD, 0x20
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vst D3, TD, 0x30
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addi.d S1, S1, 0x10
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addi.d S2, S2, 0x10
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addi.d S3, S3, 0x10
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addi.d S4, S4, 0x10
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addi.d TD, TD, 0x40
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.L_II20: /* if(m&1) */
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andi I, M, 0x01
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beq I, ZERO, .L_J0
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fld.s F0, S1, 0x00
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fld.s F1, S1, 0x04
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fld.s F2, S2, 0x00
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fld.s F3, S2, 0x04
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fld.s F4, S3, 0x00
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fld.s F5, S3, 0x04
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fld.s F6, S4, 0x00
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fld.s F7, S4, 0x04
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fst.s F0, TD, 0x00
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fst.s F1, TD, 0x04
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fst.s F2, TD, 0x08
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fst.s F3, TD, 0x0c
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fst.s F4, TD, 0x10
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fst.s F5, TD, 0x14
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fst.s F6, TD, 0x18
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fst.s F7, TD, 0x1c
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addi.d TD, TD, 0x20
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.L_J0:
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addi.d J, J, -1
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blt ZERO, J, .L_J1
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.L_N0: /* if(n&2) */
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andi I, N, 0x02
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beq ZERO, I, .L_N20
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move S1, TS
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add.d S2, S1, TL
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slli.d T0, TL, 0x01
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add.d TS, TS, T0
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srai.d I, M, 0x02
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beq ZERO, I, .L_N10
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.L_N11: /* if(i>0) */
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vld U0, S1, 0x00
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vld U1, S1, 0x10
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vld U2, S2, 0x00
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vld U3, S2, 0x10
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vand.v D0, U2, U2
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vand.v D1, U3, U3
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vand.v D2, U2, U2
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vand.v D3, U3, U3
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vpermi.w D0, U0, 0x44
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vpermi.w D2, U0, 0xee
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vpermi.w D1, U1, 0x44
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vpermi.w D3, U1, 0xee
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vst D0, TD, 0x00
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vst D2, TD, 0x10
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vst D1, TD, 0x20
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vst D3, TD, 0x30
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addi.d S1, S1, 0x20 // a_offset
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addi.d S2, S2, 0x20
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addi.d TD, TD, 0x40 // b_offset
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addi.d I, I, -1
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blt ZERO, I, .L_N11
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.L_N10: /* if(m&2) */
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andi I, M, 0x02
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beq I, ZERO, .L_N130
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vld U0, S1, 0x00
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vld U1, S2, 0x00
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vand.v D0, U1, U1
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vpermi.w D0, U0, 0x44
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vpermi.w U1, U0, 0xee
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vst D0, TD, 0x00
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vst U1, TD, 0x10
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addi.d S1, S1, 0x10 // a_offset
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addi.d S2, S2, 0x10
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addi.d TD, TD, 0x20 // b_offset
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.L_N130: /* if(m&1) */
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andi I, M, 0x01
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beq I, ZERO, .L_N20
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fld.s F0, S1, 0x00
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fld.s F1, S1, 0x04
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fld.s F2, S2, 0x00
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fld.s F3, S2, 0x04
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fst.s F0, TD, 0x00
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fst.s F1, TD, 0x04
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fst.s F2, TD, 0x08
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fst.s F3, TD, 0x0c
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addi.d TD, TD, 0x10
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.L_N20: /* if(n&1) */
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andi I, N, 0x01
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beq I, ZERO, .L_N00
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move S1, TS
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srai.d I, M, 0x02
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beq I, ZERO, .L_N30
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.L_N21: /* if(i>0) */
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vld U0, S1, 0x00
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vld U1, S1, 0x10
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vst U0, TD, 0x00
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vst U1, TD, 0x10
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addi.d S1, S1, 0x20 // aoffset1
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addi.d TD, TD, 0x20 // b_offset
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addi.d I, I, -1
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blt ZERO, I, .L_N21
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.L_N30: /* if(m&2) */
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andi I, M, 0x02
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beq I, ZERO, .L_N330
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vld U0, S1, 0x00
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vst U0, TD, 0x00
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addi.d S1, S1, 0x10 // aoffset1
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addi.d TD, TD, 0x10 // b_offset
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.L_N330: /* if(m&1) */
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andi I, M, 0x01
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beq I, ZERO, .L_N00
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fld.s F0, S1, 0x00
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fld.s F1, S1, 0x04
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fst.s F0, TD, 0x00
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fst.s F1, TD, 0x04
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.L_N00:
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LDARG $r23, $sp, 0
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addi.d $sp, $sp, 8
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jirl $r0, $r1, 0x00
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EPILOGUE |