580 lines
35 KiB
C
580 lines
35 KiB
C
/*******************************************************************************
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Copyright (c) 2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include "common.h"
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#include "macros_msa.h"
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#undef OP0
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#undef OP1
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#undef OP2
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#undef OP3
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#undef OP4
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#if ( !defined(CONJ) && !defined(XCONJ) ) || ( defined(CONJ) && defined(XCONJ) )
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#define OP0 -=
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#define OP1 +=
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#define OP2 +=
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#else
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#define OP0 +=
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#define OP1 +=
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#define OP2 -=
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#endif
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#define ZGEMV_T_8x1() \
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LD_DP4(pa0, 2, t0, t1, t2, t3); \
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LD_DP4(pa0 + 8, 2, t4, t5, t6, t7); \
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\
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PCKEVOD_D2_DP(t1, t0, src0r, src0i); \
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PCKEVOD_D2_DP(t3, t2, src1r, src1i); \
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PCKEVOD_D2_DP(t5, t4, src2r, src2i); \
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PCKEVOD_D2_DP(t7, t6, src3r, src3i); \
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\
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tp0r += src0r * x0r; \
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tp0i OP1 src0r * x0i; \
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tp0r OP0 src0i * x0i; \
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tp0i OP2 src0i * x0r; \
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\
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tp0r += src2r * x2r; \
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tp0i OP1 src2r * x2i; \
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tp0r OP0 src2i * x2i; \
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tp0i OP2 src2i * x2r; \
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\
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tp0r += src1r * x1r; \
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tp0i OP1 src1r * x1i; \
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tp0r OP0 src1i * x1i; \
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tp0i OP2 src1i * x1r; \
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\
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tp0r += src3r * x3r; \
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tp0i OP1 src3r * x3i; \
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tp0r OP0 src3i * x3i; \
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tp0i OP2 src3i * x3r; \
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#define ZGEMV_T_4x1() \
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LD_DP4(pa0, 2, t0, t1, t2, t3); \
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\
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PCKEVOD_D2_DP(t1, t0, src0r, src0i); \
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PCKEVOD_D2_DP(t3, t2, src1r, src1i); \
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\
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tp0r += src0r * x0r; \
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tp0r += src1r * x1r; \
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tp0r OP0 src0i * x0i; \
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tp0r OP0 src1i * x1i; \
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\
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tp0i OP1 src0r * x0i; \
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tp0i OP1 src1r * x1i; \
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tp0i OP2 src0i * x0r; \
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tp0i OP2 src1i * x1r; \
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#define ZGEMV_T_2x1() \
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LD_DP2(pa0, 2, t0, t1); \
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\
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PCKEVOD_D2_DP(t1, t0, src0r, src0i); \
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\
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tp0r += src0r * x0r; \
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tp0r OP0 src0i * x0i; \
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\
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tp0i OP1 src0r * x0i; \
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tp0i OP2 src0i * x0r; \
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#define ZGEMV_T_1x1() \
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temp0r += pa0[0] * x[0 * inc_x2]; \
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temp0r OP0 pa0[1] * x[0 * inc_x2 + 1]; \
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\
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temp0i OP1 pa0[0] * x[0 * inc_x2 + 1]; \
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temp0i OP2 pa0[1] * x[0 * inc_x2]; \
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#define ZSCALE_STORE_Y1_GP() \
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res0r = y[0 * inc_y2]; \
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res0i = y[0 * inc_y2 + 1]; \
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\
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res0r += alphar * temp0r; \
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res0r OP0 alphai * temp0i; \
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\
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res0i OP1 alphar * temp0i; \
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res0i OP2 alphai * temp0r; \
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\
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y[0 * inc_y2] = res0r; \
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y[0 * inc_y2 + 1] = res0i; \
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#define ZLOAD_X8_VECTOR() \
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LD_DP4(x, 2, x0, x1, x2, x3); \
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LD_DP4(x + 8, 2, x4, x5, x6, x7); \
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\
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PCKEVOD_D2_DP(x1, x0, x0r, x0i); \
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PCKEVOD_D2_DP(x3, x2, x1r, x1i); \
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PCKEVOD_D2_DP(x5, x4, x2r, x2i); \
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PCKEVOD_D2_DP(x7, x6, x3r, x3i); \
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#define ZLOAD_X4_VECTOR() \
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LD_DP4(x, 2, x0, x1, x2, x3); \
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PCKEVOD_D2_DP(x1, x0, x0r, x0i); \
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PCKEVOD_D2_DP(x3, x2, x1r, x1i); \
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#define ZLOAD_X2_VECTOR() \
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LD_DP2(x, 2, x0, x1); \
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PCKEVOD_D2_DP(x1, x0, x0r, x0i); \
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#define ZLOAD_X8_GP() \
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x0r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 0 * inc_x2))); \
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x0r = (v2f64) __msa_insert_d((v2i64) x0r, 1, *((long long *) (x + 1 * inc_x2))); \
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x1r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 2 * inc_x2))); \
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x1r = (v2f64) __msa_insert_d((v2i64) x1r, 1, *((long long *) (x + 3 * inc_x2))); \
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x2r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 4 * inc_x2))); \
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x2r = (v2f64) __msa_insert_d((v2i64) x2r, 1, *((long long *) (x + 5 * inc_x2))); \
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x3r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 6 * inc_x2))); \
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x3r = (v2f64) __msa_insert_d((v2i64) x3r, 1, *((long long *) (x + 7 * inc_x2))); \
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x0i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 0 * inc_x2 + 1))); \
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x0i = (v2f64) __msa_insert_d((v2i64) x0i, 1, *((long long *) (x + 1 * inc_x2 + 1))); \
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x1i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 2 * inc_x2 + 1))); \
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x1i = (v2f64) __msa_insert_d((v2i64) x1i, 1, *((long long *) (x + 3 * inc_x2 + 1))); \
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x2i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 4 * inc_x2 + 1))); \
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x2i = (v2f64) __msa_insert_d((v2i64) x2i, 1, *((long long *) (x + 5 * inc_x2 + 1))); \
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x3i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 6 * inc_x2 + 1))); \
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x3i = (v2f64) __msa_insert_d((v2i64) x3i, 1, *((long long *) (x + 7 * inc_x2 + 1))); \
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#define ZLOAD_X4_GP() \
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x0r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 0 * inc_x2))); \
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x0r = (v2f64) __msa_insert_d((v2i64) x0r, 1, *((long long *) (x + 1 * inc_x2))); \
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x1r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 2 * inc_x2))); \
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x1r = (v2f64) __msa_insert_d((v2i64) x1r, 1, *((long long *) (x + 3 * inc_x2))); \
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x0i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 0 * inc_x2 + 1))); \
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x0i = (v2f64) __msa_insert_d((v2i64) x0i, 1, *((long long *) (x + 1 * inc_x2 + 1))); \
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x1i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 2 * inc_x2 + 1))); \
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x1i = (v2f64) __msa_insert_d((v2i64) x1i, 1, *((long long *) (x + 3 * inc_x2 + 1))); \
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#define ZLOAD_X2_GP() \
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x0r = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 0 * inc_x2))); \
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x0r = (v2f64) __msa_insert_d((v2i64) x0r, 1, *((long long *) (x + 1 * inc_x2))); \
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x0i = (v2f64) __msa_insert_d((v2i64) tp0r, 0, *((long long *) (x + 0 * inc_x2 + 1))); \
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x0i = (v2f64) __msa_insert_d((v2i64) x0i, 1, *((long long *) (x + 1 * inc_x2 + 1))); \
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#define ZGEMV_T_MSA() \
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for (j = n; j--;) \
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{ \
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tp0r = zero; \
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tp0i = zero; \
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tp1r = zero; \
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tp1i = zero; \
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tp2r = zero; \
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tp2i = zero; \
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tp3r = zero; \
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tp3i = zero; \
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\
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pa0 = A; \
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x = srcx_org; \
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\
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if (m >> 4) \
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{ \
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x0 = LD_DP(x); \
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x1 = LD_DP(x + 1 * inc_x2); \
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t0 = LD_DP(pa0); \
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t1 = LD_DP(pa0 + 2); \
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\
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x4 = LD_DP(x + 4 * inc_x2); \
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x5 = LD_DP(x + 5 * inc_x2); \
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t4 = LD_DP(pa0 + 8); \
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t5 = LD_DP(pa0 + 10); \
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\
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for (i = (m >> 4) - 1; i--;) \
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{ \
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pa0_pref = pa0 + pref_offset; \
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\
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PREFETCH(pa0_pref + 36); \
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PREFETCH(pa0_pref + 44); \
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PREFETCH(pa0_pref + 48); \
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PREFETCH(pa0_pref + 52); \
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PREFETCH(pa0_pref + 56); \
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PREFETCH(pa0_pref + 60); \
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PREFETCH(pa0_pref + 64); \
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PREFETCH(pa0_pref + 72); \
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\
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x0r = (v2f64) __msa_pckev_d((v2i64) x1, (v2i64) x0); \
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x0i = (v2f64) __msa_pckod_d((v2i64) x1, (v2i64) x0); \
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src0r = (v2f64) __msa_pckev_d((v2i64) t1, (v2i64) t0); \
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src0i = (v2f64) __msa_pckod_d((v2i64) t1, (v2i64) t0); \
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\
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tp0r += src0r * x0r; \
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x2 = LD_DP(x + 2 * inc_x2); \
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x2r = (v2f64) __msa_pckev_d((v2i64) x5, (v2i64) x4); \
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\
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tp0i OP1 src0r * x0i; \
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x3 = LD_DP(x + 3 * inc_x2); \
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x2i = (v2f64) __msa_pckod_d((v2i64) x5, (v2i64) x4); \
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\
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tp1r OP0 src0i * x0i; \
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t2 = LD_DP(pa0 + 4); \
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src2r = (v2f64) __msa_pckev_d((v2i64) t5, (v2i64) t4); \
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\
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tp1i OP2 src0i * x0r; \
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t3 = LD_DP(pa0 + 6); \
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src2i = (v2f64) __msa_pckod_d((v2i64) t5, (v2i64) t4); \
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\
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tp2r += src2r * x2r; \
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x6 = LD_DP(x + 6 * inc_x2); \
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\
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tp2i OP1 src2r * x2i; \
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x7 = LD_DP(x + 7 * inc_x2); \
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\
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tp3r OP0 src2i * x2i; \
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t6 = LD_DP(pa0 + 12); \
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\
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tp3i OP2 src2i * x2r; \
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t7 = LD_DP(pa0 + 14); \
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\
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x1r = (v2f64) __msa_pckev_d((v2i64) x3, (v2i64) x2); \
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x1i = (v2f64) __msa_pckod_d((v2i64) x3, (v2i64) x2); \
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src1r = (v2f64) __msa_pckev_d((v2i64) t3, (v2i64) t2); \
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src1i = (v2f64) __msa_pckod_d((v2i64) t3, (v2i64) t2); \
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\
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tp0r += src1r * x1r; \
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x0 = LD_DP(x + 8 * inc_x2); \
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x3r = (v2f64) __msa_pckev_d((v2i64) x7, (v2i64) x6); \
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\
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tp0i OP1 src1r * x1i; \
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x1 = LD_DP(x + 9 * inc_x2); \
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x3i = (v2f64) __msa_pckod_d((v2i64) x7, (v2i64) x6); \
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\
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tp1r OP0 src1i * x1i; \
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t0 = LD_DP(pa0 + 16); \
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src3r = (v2f64) __msa_pckev_d((v2i64) t7, (v2i64) t6); \
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\
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tp1i OP2 src1i * x1r; \
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t1 = LD_DP(pa0 + 18); \
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src3i = (v2f64) __msa_pckod_d((v2i64) t7, (v2i64) t6); \
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\
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tp2r += src3r * x3r; \
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x4 = LD_DP(x + 12 * inc_x2); \
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\
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tp2i OP1 src3r * x3i; \
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x5 = LD_DP(x + 13 * inc_x2); \
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\
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tp3r OP0 src3i * x3i; \
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t4 = LD_DP(pa0 + 24); \
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\
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tp3i OP2 src3i * x3r; \
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t5 = LD_DP(pa0 + 26); \
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\
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x0r = (v2f64) __msa_pckev_d((v2i64) x1, (v2i64) x0); \
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x0i = (v2f64) __msa_pckod_d((v2i64) x1, (v2i64) x0); \
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src0r = (v2f64) __msa_pckev_d((v2i64) t1, (v2i64) t0); \
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src0i = (v2f64) __msa_pckod_d((v2i64) t1, (v2i64) t0); \
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\
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tp0r += src0r * x0r; \
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x2 = LD_DP(x + 10 * inc_x2); \
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x2r = (v2f64) __msa_pckev_d((v2i64) x5, (v2i64) x4); \
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\
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tp0i OP1 src0r * x0i; \
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x3 = LD_DP(x + 11 * inc_x2); \
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x2i = (v2f64) __msa_pckod_d((v2i64) x5, (v2i64) x4); \
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\
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tp1r OP0 src0i * x0i; \
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t2 = LD_DP(pa0 + 20); \
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src2r = (v2f64) __msa_pckev_d((v2i64) t5, (v2i64) t4); \
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\
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tp1i OP2 src0i * x0r; \
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t3 = LD_DP(pa0 + 22); \
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src2i = (v2f64) __msa_pckod_d((v2i64) t5, (v2i64) t4); \
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\
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tp2r += src2r * x2r; \
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x6 = LD_DP(x + 14 * inc_x2); \
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\
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tp2i OP1 src2r * x2i; \
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x7 = LD_DP(x + 15 * inc_x2); \
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\
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tp3r OP0 src2i * x2i; \
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t6 = LD_DP(pa0 + 28); \
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\
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tp3i OP2 src2i * x2r; \
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t7 = LD_DP(pa0 + 30); \
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\
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x1r = (v2f64) __msa_pckev_d((v2i64) x3, (v2i64) x2); \
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x1i = (v2f64) __msa_pckod_d((v2i64) x3, (v2i64) x2); \
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src1r = (v2f64) __msa_pckev_d((v2i64) t3, (v2i64) t2); \
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src1i = (v2f64) __msa_pckod_d((v2i64) t3, (v2i64) t2); \
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\
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tp0r += src1r * x1r; \
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x0 = LD_DP(x + inc_x2 * 16); \
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x3r = (v2f64) __msa_pckev_d((v2i64) x7, (v2i64) x6); \
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\
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tp0i OP1 src1r * x1i; \
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x1 = LD_DP(x + inc_x2 * 16 + 1 * inc_x2); \
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x3i = (v2f64) __msa_pckod_d((v2i64) x7, (v2i64) x6); \
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\
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tp1r OP0 src1i * x1i; \
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t0 = LD_DP(pa0 + 2 * 16); \
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src3r = (v2f64) __msa_pckev_d((v2i64) t7, (v2i64) t6); \
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\
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tp1i OP2 src1i * x1r; \
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t1 = LD_DP(pa0 + 2 * 16 + 2); \
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src3i = (v2f64) __msa_pckod_d((v2i64) t7, (v2i64) t6); \
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\
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tp2r += src3r * x3r; \
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x4 = LD_DP(x + inc_x2 * 16 + 4 * inc_x2); \
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\
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tp2i OP1 src3r * x3i; \
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x5 = LD_DP(x + inc_x2 * 16 + 5 * inc_x2); \
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\
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tp3r OP0 src3i * x3i; \
|
|
t4 = LD_DP(pa0 + 2 * 16 + 8); \
|
|
\
|
|
tp3i OP2 src3i * x3r; \
|
|
t5 = LD_DP(pa0 + 2 * 16 + 10); \
|
|
\
|
|
pa0 += 2 * 16; \
|
|
x += inc_x2 * 16; \
|
|
} \
|
|
\
|
|
x0r = (v2f64) __msa_pckev_d((v2i64) x1, (v2i64) x0); \
|
|
x0i = (v2f64) __msa_pckod_d((v2i64) x1, (v2i64) x0); \
|
|
src0r = (v2f64) __msa_pckev_d((v2i64) t1, (v2i64) t0); \
|
|
src0i = (v2f64) __msa_pckod_d((v2i64) t1, (v2i64) t0); \
|
|
\
|
|
tp0r += src0r * x0r; \
|
|
x2 = LD_DP(x + 2 * inc_x2); \
|
|
x2r = (v2f64) __msa_pckev_d((v2i64) x5, (v2i64) x4); \
|
|
\
|
|
tp0i OP1 src0r * x0i; \
|
|
x3 = LD_DP(x + 3 * inc_x2); \
|
|
x2i = (v2f64) __msa_pckod_d((v2i64) x5, (v2i64) x4); \
|
|
\
|
|
tp1r OP0 src0i * x0i; \
|
|
t2 = LD_DP(pa0 + 4); \
|
|
src2r = (v2f64) __msa_pckev_d((v2i64) t5, (v2i64) t4); \
|
|
\
|
|
tp1i OP2 src0i * x0r; \
|
|
t3 = LD_DP(pa0 + 6); \
|
|
src2i = (v2f64) __msa_pckod_d((v2i64) t5, (v2i64) t4); \
|
|
\
|
|
tp2r += src2r * x2r; \
|
|
x6 = LD_DP(x + 6 * inc_x2); \
|
|
\
|
|
tp2i OP1 src2r * x2i; \
|
|
x7 = LD_DP(x + 7 * inc_x2); \
|
|
\
|
|
tp3r OP0 src2i * x2i; \
|
|
t6 = LD_DP(pa0 + 12); \
|
|
\
|
|
tp3i OP2 src2i * x2r; \
|
|
t7 = LD_DP(pa0 + 14); \
|
|
\
|
|
x1r = (v2f64) __msa_pckev_d((v2i64) x3, (v2i64) x2); \
|
|
x1i = (v2f64) __msa_pckod_d((v2i64) x3, (v2i64) x2); \
|
|
src1r = (v2f64) __msa_pckev_d((v2i64) t3, (v2i64) t2); \
|
|
src1i = (v2f64) __msa_pckod_d((v2i64) t3, (v2i64) t2); \
|
|
\
|
|
tp0r += src1r * x1r; \
|
|
x0 = LD_DP(x + 8 * inc_x2); \
|
|
x3r = (v2f64) __msa_pckev_d((v2i64) x7, (v2i64) x6); \
|
|
\
|
|
tp0i OP1 src1r * x1i; \
|
|
x1 = LD_DP(x + 9 * inc_x2); \
|
|
x3i = (v2f64) __msa_pckod_d((v2i64) x7, (v2i64) x6); \
|
|
\
|
|
tp1r OP0 src1i * x1i; \
|
|
t0 = LD_DP(pa0 + 16); \
|
|
src3r = (v2f64) __msa_pckev_d((v2i64) t7, (v2i64) t6); \
|
|
\
|
|
tp1i OP2 src1i * x1r; \
|
|
t1 = LD_DP(pa0 + 18); \
|
|
src3i = (v2f64) __msa_pckod_d((v2i64) t7, (v2i64) t6); \
|
|
\
|
|
tp2r += src3r * x3r; \
|
|
x4 = LD_DP(x + 12 * inc_x2); \
|
|
\
|
|
tp2i OP1 src3r * x3i; \
|
|
x5 = LD_DP(x + 13 * inc_x2); \
|
|
\
|
|
tp3r OP0 src3i * x3i; \
|
|
t4 = LD_DP(pa0 + 24); \
|
|
\
|
|
tp3i OP2 src3i * x3r; \
|
|
t5 = LD_DP(pa0 + 26); \
|
|
\
|
|
x0r = (v2f64) __msa_pckev_d((v2i64) x1, (v2i64) x0); \
|
|
x0i = (v2f64) __msa_pckod_d((v2i64) x1, (v2i64) x0); \
|
|
src0r = (v2f64) __msa_pckev_d((v2i64) t1, (v2i64) t0); \
|
|
src0i = (v2f64) __msa_pckod_d((v2i64) t1, (v2i64) t0); \
|
|
\
|
|
tp0r += src0r * x0r; \
|
|
x2 = LD_DP(x + 10 * inc_x2); \
|
|
x2r = (v2f64) __msa_pckev_d((v2i64) x5, (v2i64) x4); \
|
|
\
|
|
tp0i OP1 src0r * x0i; \
|
|
x3 = LD_DP(x + 11 * inc_x2); \
|
|
x2i = (v2f64) __msa_pckod_d((v2i64) x5, (v2i64) x4); \
|
|
\
|
|
tp1r OP0 src0i * x0i; \
|
|
t2 = LD_DP(pa0 + 20); \
|
|
src2r = (v2f64) __msa_pckev_d((v2i64) t5, (v2i64) t4); \
|
|
\
|
|
tp1i OP2 src0i * x0r; \
|
|
t3 = LD_DP(pa0 + 22); \
|
|
src2i = (v2f64) __msa_pckod_d((v2i64) t5, (v2i64) t4); \
|
|
\
|
|
tp2r += src2r * x2r; \
|
|
x6 = LD_DP(x + 14 * inc_x2); \
|
|
\
|
|
tp2i OP1 src2r * x2i; \
|
|
x7 = LD_DP(x + 15 * inc_x2); \
|
|
\
|
|
tp3r OP0 src2i * x2i; \
|
|
t6 = LD_DP(pa0 + 28); \
|
|
\
|
|
tp3i OP2 src2i * x2r; \
|
|
t7 = LD_DP(pa0 + 30); \
|
|
\
|
|
x1r = (v2f64) __msa_pckev_d((v2i64) x3, (v2i64) x2); \
|
|
x1i = (v2f64) __msa_pckod_d((v2i64) x3, (v2i64) x2); \
|
|
src1r = (v2f64) __msa_pckev_d((v2i64) t3, (v2i64) t2); \
|
|
src1i = (v2f64) __msa_pckod_d((v2i64) t3, (v2i64) t2); \
|
|
\
|
|
tp0r += src1r * x1r; \
|
|
x3r = (v2f64) __msa_pckev_d((v2i64) x7, (v2i64) x6); \
|
|
\
|
|
tp0i OP1 src1r * x1i; \
|
|
x3i = (v2f64) __msa_pckod_d((v2i64) x7, (v2i64) x6); \
|
|
\
|
|
tp1r OP0 src1i * x1i; \
|
|
src3r = (v2f64) __msa_pckev_d((v2i64) t7, (v2i64) t6); \
|
|
\
|
|
tp1i OP2 src1i * x1r; \
|
|
src3i = (v2f64) __msa_pckod_d((v2i64) t7, (v2i64) t6); \
|
|
\
|
|
tp2r += src3r * x3r; \
|
|
tp2i OP1 src3r * x3i; \
|
|
tp3r OP0 src3i * x3i; \
|
|
tp3i OP2 src3i * x3r; \
|
|
\
|
|
pa0 += 2 * 16; \
|
|
x += inc_x2 * 16; \
|
|
\
|
|
tp0r += tp1r + tp2r + tp3r; \
|
|
tp0i += tp1i + tp2i + tp3i; \
|
|
} \
|
|
\
|
|
if (m & 8) \
|
|
{ \
|
|
ZLOAD_X8(); \
|
|
ZGEMV_T_8x1(); \
|
|
\
|
|
pa0 += 2 * 8; \
|
|
x += inc_x2 * 8; \
|
|
} \
|
|
\
|
|
if (m & 4) \
|
|
{ \
|
|
ZLOAD_X4(); \
|
|
ZGEMV_T_4x1(); \
|
|
\
|
|
pa0 += 2 * 4; \
|
|
x += inc_x2 * 4; \
|
|
} \
|
|
\
|
|
if (m & 2) \
|
|
{ \
|
|
ZLOAD_X2(); \
|
|
ZGEMV_T_2x1(); \
|
|
\
|
|
pa0 += 2 * 2; \
|
|
x += inc_x2 * 2; \
|
|
} \
|
|
\
|
|
temp0r = tp0r[0] + tp0r[1]; \
|
|
temp0i = tp0i[0] + tp0i[1]; \
|
|
\
|
|
if (m & 1) \
|
|
{ \
|
|
ZGEMV_T_1x1(); \
|
|
\
|
|
pa0 += 2; \
|
|
x += inc_x2; \
|
|
} \
|
|
\
|
|
ZSCALE_STORE_Y1_GP(); \
|
|
\
|
|
A += lda2; \
|
|
y += inc_y2; \
|
|
} \
|
|
|
|
int CNAME(BLASLONG m, BLASLONG n, BLASLONG dummy1, FLOAT alphar, FLOAT alphai,
|
|
FLOAT *A, BLASLONG lda, FLOAT *x, BLASLONG inc_x, FLOAT *y,
|
|
BLASLONG inc_y, FLOAT *buffer)
|
|
{
|
|
BLASLONG i, j, pref_offset;
|
|
BLASLONG inc_x2, inc_y2, lda2;
|
|
FLOAT *pa0, *pa0_pref;
|
|
FLOAT *srcx_org = x;
|
|
FLOAT temp0r, temp0i;
|
|
FLOAT res0r, res0i;
|
|
v2f64 zero = {0};
|
|
v2f64 x0, x1, x2, x3, x0r, x1r, x0i, x1i;
|
|
v2f64 x4, x5, x6, x7, x2r, x3r, x2i, x3i;
|
|
v2f64 t0, t1, t2, t3, t4, t5, t6, t7;
|
|
v2f64 src0r, src1r, src2r, src3r;
|
|
v2f64 src0i, src1i, src2i, src3i;
|
|
v2f64 tp0r, tp1r, tp2r, tp3r, tp0i, tp1i, tp2i, tp3i;
|
|
|
|
lda2 = 2 * lda;
|
|
|
|
inc_x2 = 2 * inc_x;
|
|
inc_y2 = 2 * inc_y;
|
|
|
|
pref_offset = (uintptr_t)A & L1_DATA_LINESIZE;
|
|
pref_offset = L1_DATA_LINESIZE - pref_offset;
|
|
pref_offset = pref_offset / sizeof(FLOAT);
|
|
|
|
if (2 == inc_x2)
|
|
{
|
|
#define ZLOAD_X8 ZLOAD_X8_VECTOR
|
|
#define ZLOAD_X4 ZLOAD_X4_VECTOR
|
|
#define ZLOAD_X2 ZLOAD_X2_VECTOR
|
|
|
|
ZGEMV_T_MSA();
|
|
|
|
#undef ZLOAD_X8
|
|
#undef ZLOAD_X4
|
|
#undef ZLOAD_X2
|
|
}
|
|
else
|
|
{
|
|
#define ZLOAD_X8 ZLOAD_X8_GP
|
|
#define ZLOAD_X4 ZLOAD_X4_GP
|
|
#define ZLOAD_X2 ZLOAD_X2_GP
|
|
|
|
ZGEMV_T_MSA();
|
|
|
|
#undef ZLOAD_X8
|
|
#undef ZLOAD_X4
|
|
#undef ZLOAD_X2
|
|
}
|
|
return(0);
|
|
}
|
|
|
|
#undef OP0
|
|
#undef OP1
|
|
#undef OP2
|