233 lines
4.6 KiB
ArmAsm
233 lines
4.6 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2015, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N x0 /* vector length */
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#define X x1 /* X vector address */
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#define INC_X x2 /* X stride */
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#define Y x3 /* Y vector address */
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#define INC_Y x4 /* Y stride */
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#define I x5 /* loop variable */
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/*******************************************************************************
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* Macro definitions
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*******************************************************************************/
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#if !defined(DOUBLE)
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#define TMPF s0
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#define TMPVF {v0.s}[0]
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#define SZ 4
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#else
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#define TMPF d0
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#define TMPVF {v0.d}[0]
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#define SZ 8
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#endif
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/******************************************************************************/
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.macro KERNEL_F1
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#if !defined(COMPLEX)
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ldr TMPF, [X], #SZ
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str TMPF, [Y], #SZ
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#else
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#if !defined(DOUBLE)
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ld1 {v0.2s}, [X], #8
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st1 {v0.2s}, [Y], #8
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#else
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ld1 {v0.2d}, [X], #16
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st1 {v0.2d}, [Y], #16
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#endif
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#endif
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.endm
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.macro KERNEL_F4
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#if !defined(COMPLEX)
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#if !defined(DOUBLE)
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ld1 {v0.4s}, [X], #16
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st1 {v0.4s}, [Y], #16
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#else // DOUBLE
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ld1 {v0.4s}, [X], #16
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ld1 {v1.4s}, [X], #16
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st1 {v0.4s}, [Y], #16
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st1 {v1.4s}, [Y], #16
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#endif
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#else // COMPLEX
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#if !defined(DOUBLE)
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ld1 {v0.4s}, [X], #16
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ld1 {v1.4s}, [X], #16
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st1 {v0.4s}, [Y], #16
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st1 {v1.4s}, [Y], #16
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#else // DOUBLE
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ld1 {v0.4s}, [X], #16
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ld1 {v1.4s}, [X], #16
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ld1 {v2.4s}, [X], #16
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ld1 {v3.4s}, [X], #16
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st1 {v0.4s}, [Y], #16
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st1 {v1.4s}, [Y], #16
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st1 {v2.4s}, [Y], #16
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st1 {v3.4s}, [Y], #16
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#endif
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#endif
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.endm
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.macro INIT_S
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#if !defined(COMPLEX)
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#if !defined(DOUBLE)
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lsl INC_X, INC_X, #2
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lsl INC_Y, INC_Y, #2
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#else
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lsl INC_X, INC_X, #3
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lsl INC_Y, INC_Y, #3
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#endif
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#else
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#if !defined(DOUBLE)
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lsl INC_X, INC_X, #3
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lsl INC_Y, INC_Y, #3
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#else
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lsl INC_X, INC_X, #4
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lsl INC_Y, INC_Y, #4
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#endif
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#endif
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.endm
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.macro KERNEL_S1
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#if !defined(COMPLEX)
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#if !defined(DOUBLE)
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ldr w10, [X]
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add X, X, INC_X
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str w10, [Y]
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add Y, Y, INC_Y
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#else
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ldr x10, [X]
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add X, X, INC_X
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str x10, [Y]
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add Y, Y, INC_Y
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#endif
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#else
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#if !defined(DOUBLE)
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ld1 {v0.2s}, [X]
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add X, X, INC_X
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st1 {v0.2s}, [Y]
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add Y, Y, INC_Y
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#else
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ld1 {v0.2d}, [X]
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add X, X, INC_X
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st1 {v0.2d}, [Y]
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add Y, Y, INC_Y
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#endif
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#endif
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.endm
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/*******************************************************************************
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* End of macro definitions
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*******************************************************************************/
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PROLOGUE
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cmp N, xzr
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ble copy_kernel_L999
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cmp INC_X, #1
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bne copy_kernel_S_BEGIN
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cmp INC_Y, #1
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bne copy_kernel_S_BEGIN
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copy_kernel_F_BEGIN:
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asr I, N, #2
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cmp I, xzr
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beq copy_kernel_F1
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copy_kernel_F4:
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KERNEL_F4
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subs I, I, #1
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bne copy_kernel_F4
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copy_kernel_F1:
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ands I, N, #3
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ble copy_kernel_L999
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copy_kernel_F10:
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KERNEL_F1
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subs I, I, #1
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bne copy_kernel_F10
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mov w0, wzr
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ret
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copy_kernel_S_BEGIN:
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INIT_S
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asr I, N, #2
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cmp I, xzr
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ble copy_kernel_S1
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copy_kernel_S4:
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KERNEL_S1
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KERNEL_S1
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KERNEL_S1
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KERNEL_S1
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subs I, I, #1
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bne copy_kernel_S4
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copy_kernel_S1:
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ands I, N, #3
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ble copy_kernel_L999
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copy_kernel_S10:
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KERNEL_S1
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subs I, I, #1
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bne copy_kernel_S10
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copy_kernel_L999:
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mov w0, wzr
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ret
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EPILOGUE
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