359 lines
9.0 KiB
ArmAsm
359 lines
9.0 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N $r4
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#define X $r5
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#define INCX $r6
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#define I $r17
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#define TEMP $r18
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#define t1 $r15
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#define t2 $r12
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#define t3 $r13
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#define t4 $r14
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#define a1 $f12
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#define a2 $f13
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#define a3 $f14
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#define a4 $f15
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#define s1 $f16
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#define VX0 $vr12
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#define VX1 $vr13
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#define VX2 $vr14
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#define VX3 $vr15
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#define res1 $vr16
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#define res2 $vr17
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#define res3 $vr18
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#define res0 $vr19
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#define neg1 $vr20
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#define VT0 $vr21
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#define VT1 $vr22
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PROLOGUE
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vxor.v res1, res1, res1
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vxor.v res2, res2, res2
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vxor.v res0, res0, res0
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bge $r0, N, .L999
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bge $r0, INCX, .L999
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#ifdef DOUBLE
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li.d t1, -1
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vreplgr2vr.d neg1, t1
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vffint.d.l neg1, neg1
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#else
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li.w t1, -1
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vreplgr2vr.w neg1, t1
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vffint.s.w neg1, neg1
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#endif
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li.d TEMP, 1
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slli.d TEMP, TEMP, ZBASE_SHIFT
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slli.d INCX, INCX, ZBASE_SHIFT
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srai.d I, N, 3
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bne INCX, TEMP, .L20
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bge $r0, I, .L13
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.align 3
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.L11:
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#ifdef DOUBLE
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vld VX0, X, 0 * SIZE
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vld VX1, X, 2 * SIZE
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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vld VX2, X, 4 * SIZE
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vld VX3, X, 6 * SIZE
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vfmul.d VX0, neg1, VX2
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vfmul.d VX1, neg1, VX3
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vfcmp.clt.d VT0, VX2, res0
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vfcmp.clt.d VT1, VX3, res0
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vbitsel.v VX2, VX2, VX0, VT0
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vbitsel.v VX3, VX3, VX1, VT1
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vfadd.d res2, VX2, VX3
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vfadd.d res1, res1, res2
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vld VX0, X, 8 * SIZE
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vld VX1, X, 10 * SIZE
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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vld VX2, X, 12 * SIZE
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vld VX3, X, 14 * SIZE
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vfmul.d VX0, neg1, VX2
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vfmul.d VX1, neg1, VX3
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vfcmp.clt.d VT0, VX2, res0
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vfcmp.clt.d VT1, VX3, res0
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vbitsel.v VX2, VX2, VX0, VT0
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vbitsel.v VX3, VX3, VX1, VT1
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vfadd.d res2, VX2, VX3
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vfadd.d res1, res1, res2
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addi.d I, I, -1
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#else
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vld VX0, X, 0 * SIZE
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vld VX1, X, 4 * SIZE
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vfmul.s VX2, neg1, VX0
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vfmul.s VX3, neg1, VX1
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vfcmp.clt.s VT0, VX0, res0
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vfcmp.clt.s VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.s res2, VX0, VX1
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vld VX0, X, 8 * SIZE
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vld VX1, X, 12 * SIZE
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addi.d I, I, -1
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vfmul.s VX2, neg1, VX0
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vfmul.s VX3, neg1, VX1
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vfcmp.clt.s VT0, VX0, res0
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vfcmp.clt.s VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.s res3, VX1, VX0
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vfadd.s res2, res3, res2
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vfadd.s res1, res1, res2
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#endif
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addi.d X, X, 16 * SIZE
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blt $r0, I, .L11
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.align 3
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.L12:
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#ifdef DOUBLE
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vreplvei.d VX1, res1, 1
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vfadd.d res1, VX1, res1
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#else
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vreplvei.w VX1, res1, 1
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vreplvei.w VX2, res1, 2
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vreplvei.w VX3, res1, 3
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vfadd.s res1, VX1, res1
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vfadd.s res1, VX2, res1
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vfadd.s res1, VX3, res1
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#endif
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.align 3
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.L13:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L14:
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LD a1, X, 0 * SIZE
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LD a2, X, 1 * SIZE
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FABS a1, a1
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FABS a2, a2
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addi.d I, I, -1
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ADD a1, a1, a2
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ADD s1, a1, s1
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addi.d X, X, 2 * SIZE
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blt $r0, I, .L14
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b .L999
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.align 3
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.L20:
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bge $r0, I, .L23
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.align 3
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.L21:
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#ifdef DOUBLE
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ld.d t1, X, 0 * SIZE
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ld.d t2, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX0, t1, 0
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vinsgr2vr.d VX0, t2, 1
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ld.d t1, X, 0 * SIZE
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ld.d t2, X, 1 * SIZE
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vinsgr2vr.d VX1, t1, 0
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vinsgr2vr.d VX1, t2, 1
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add.d X, X, INCX
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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ld.d t3, X, 0 * SIZE
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ld.d t4, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX0, t3, 0
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vinsgr2vr.d VX0, t4, 1
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ld.d t3, X, 0 * SIZE
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ld.d t4, X, 1 * SIZE
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vinsgr2vr.d VX1, t3, 0
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vinsgr2vr.d VX1, t4, 1
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add.d X, X, INCX
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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ld.d t1, X, 0 * SIZE
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ld.d t2, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX0, t1, 0
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vinsgr2vr.d VX0, t2, 1
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ld.d t1, X, 0 * SIZE
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ld.d t2, X, 1 * SIZE
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vinsgr2vr.d VX1, t1, 0
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vinsgr2vr.d VX1, t2, 1
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add.d X, X, INCX
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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ld.d t3, X, 0 * SIZE
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ld.d t4, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.d VX0, t3, 0
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vinsgr2vr.d VX0, t4, 1
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ld.d t3, X, 0 * SIZE
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ld.d t4, X, 1 * SIZE
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vinsgr2vr.d VX1, t3, 0
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vinsgr2vr.d VX1, t4, 1
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add.d X, X, INCX
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vfmul.d VX2, neg1, VX0
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vfmul.d VX3, neg1, VX1
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vfcmp.clt.d VT0, VX0, res0
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vfcmp.clt.d VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.d res2, VX0, VX1
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vfadd.d res1, res1, res2
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#else
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ld.w t1, X, 0 * SIZE
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ld.w t2, X, 1 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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ld.w t4, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.w VX0, t1, 0
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vinsgr2vr.w VX0, t2, 1
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vinsgr2vr.w VX0, t3, 2
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vinsgr2vr.w VX0, t4, 3
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ld.w t1, X, 0 * SIZE
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ld.w t2, X, 1 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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ld.w t4, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.w VX1, t1, 0
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vinsgr2vr.w VX1, t2, 1
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vinsgr2vr.w VX1, t3, 2
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vinsgr2vr.w VX1, t4, 3
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vfmul.s VX2, neg1, VX0
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vfmul.s VX3, neg1, VX1
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vfcmp.clt.s VT0, VX0, res0
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vfcmp.clt.s VT1, VX1, res0
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vbitsel.v VX0, VX0, VX2, VT0
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vbitsel.v VX1, VX1, VX3, VT1
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vfadd.s res2, VX0, VX1
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ld.w t1, X, 0 * SIZE
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ld.w t2, X, 1 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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ld.w t4, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.w VX2, t1, 0
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vinsgr2vr.w VX2, t2, 1
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vinsgr2vr.w VX2, t3, 2
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vinsgr2vr.w VX2, t4, 3
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ld.w t1, X, 0 * SIZE
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ld.w t2, X, 1 * SIZE
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add.d X, X, INCX
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ld.w t3, X, 0 * SIZE
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ld.w t4, X, 1 * SIZE
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add.d X, X, INCX
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vinsgr2vr.w VX3, t1, 0
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vinsgr2vr.w VX3, t2, 1
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vinsgr2vr.w VX3, t3, 2
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vinsgr2vr.w VX3, t4, 3
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vfmul.s VX0, neg1, VX2
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vfmul.s VX1, neg1, VX3
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vfcmp.clt.s VT0, VX2, res0
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vfcmp.clt.s VT1, VX3, res0
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vbitsel.v VX2, VX2, VX0, VT0
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vbitsel.v VX3, VX3, VX1, VT1
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vfadd.s res3, VX2, VX3
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vfadd.s res2, res3, res2
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vfadd.s res1, res1, res2
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#endif
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addi.d I, I, -1
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blt $r0, I, .L21
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.align 3
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.L22:
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#ifdef DOUBLE
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vreplvei.d VX1, res1, 1
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vfadd.d res1, VX1, res1
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#else
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vreplvei.w VX1, res1, 1
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vreplvei.w VX2, res1, 2
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vreplvei.w VX3, res1, 3
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vfadd.s res1, VX1, res1
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vfadd.s res1, VX2, res1
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vfadd.s res1, VX3, res1
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#endif
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.align 3
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.L23:
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andi I, N, 7
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bge $r0, I, .L999
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.align 3
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.L24:
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LD a1, X, 0 * SIZE
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LD a2, X, 1 * SIZE
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FABS a1, a1
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FABS a2, a2
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addi.d I, I, -1
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ADD a1, a1, a2
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ADD s1, a1, s1
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add.d X, X, INCX
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blt $r0, I, .L24
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.align 3
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.L999:
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MOV $f0, $f16
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jirl $r0, $r1, 0x0
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.align 3
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EPILOGUE
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