519 lines
10 KiB
ArmAsm
519 lines
10 KiB
ArmAsm
/*********************************************************************/
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/* Copyright 2009, 2010 The University of Texas at Austin. */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or */
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/* without modification, are permitted provided that the following */
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/* conditions are met: */
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/* */
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/* 1. Redistributions of source code must retain the above */
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/* copyright notice, this list of conditions and the following */
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/* disclaimer. */
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/* */
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/* 2. Redistributions in binary form must reproduce the above */
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/* copyright notice, this list of conditions and the following */
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/* disclaimer in the documentation and/or other materials */
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/* provided with the distribution. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
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/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
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/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
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/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
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/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
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/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
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/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
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/* POSSIBILITY OF SUCH DAMAGE. */
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/* */
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/* The views and conclusions contained in the software and */
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/* documentation are those of the authors and should not be */
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/* interpreted as representing official policies, either expressed */
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/* or implied, of The University of Texas at Austin. */
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/*********************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define N %i0
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#if defined(DOUBLE) && !defined(__64BIT__)
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#define X %i3
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#define INCX %i4
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#else
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#define X %i5
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#define INCX %i3
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#endif
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#define I %i1
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#define XX %i2
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#ifdef DOUBLE
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#define c1 %f0
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#define c2 %f2
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#define c3 %f4
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#define c4 %f6
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#define c5 %f8
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#define c6 %f10
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#define c7 %f12
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#define c8 %f14
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#define t1 %f16
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#define t2 %f18
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#define t3 %f20
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#define t4 %f22
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#define t5 %f24
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#define t6 %f26
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#define t7 %f28
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#define t8 %f30
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#define c9 %f32
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#define c10 %f34
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#define c11 %f36
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#define c12 %f38
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#define c13 %f40
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#define c14 %f42
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#define c15 %f44
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#define c16 %f46
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#define s1 %f32
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#define s2 %f34
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#define s3 %f36
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#define s4 %f38
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#define s5 %f40
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#define s6 %f42
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#define s7 %f44
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#define s8 %f46
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#define FZERO %f48
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#define ALPHA_R %f50
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#define ALPHA_I %f52
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#else
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#define c1 %f0
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#define c2 %f1
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#define c3 %f2
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#define c4 %f3
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#define c5 %f4
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#define c6 %f5
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#define c7 %f6
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#define c8 %f7
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#define c9 %f8
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#define c10 %f9
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#define c11 %f10
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#define c12 %f11
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#define c13 %f12
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#define c14 %f13
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#define c15 %f14
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#define c16 %f15
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#define s1 %f8
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#define s2 %f9
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#define s3 %f10
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#define s4 %f11
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#define s5 %f12
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#define s6 %f13
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#define s7 %f14
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#define s8 %f15
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#define t1 %f16
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#define t2 %f17
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#define t3 %f18
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#define t4 %f19
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#define t5 %f20
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#define t6 %f21
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#define t7 %f22
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#define t8 %f23
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#define FZERO %f24
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#define ALPHA_R %f25
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#define ALPHA_I %f26
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#endif
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#define PREFETCHSIZE 128
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PROLOGUE
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SAVESP
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#ifndef __64BIT__
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#ifdef DOUBLE
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st %i3, [%sp + STACK_START + 16]
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st %i4, [%sp + STACK_START + 20]
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st %i5, [%sp + STACK_START + 24]
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ld [%sp+ STACK_START + 32], X
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ld [%sp+ STACK_START + 36], INCX
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#else
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st %i3, [%sp + STACK_START + 16]
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st %i4, [%sp + STACK_START + 24]
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ld [%sp+ STACK_START + 28], INCX
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#endif
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LDF [%sp + STACK_START + 16], ALPHA_R
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LDF [%sp + STACK_START + 24], ALPHA_I
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#else
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ldx [%sp + STACK_START + 56], INCX
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#ifdef DOUBLE
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FMOV %f6, ALPHA_R
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FMOV %f8, ALPHA_I
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#else
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FMOV %f7, ALPHA_R
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FMOV %f9, ALPHA_I
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#endif
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#endif
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#ifdef DOUBLE
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FCLR(17)
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#else
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FCLR(24)
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#endif
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FCMP ALPHA_R, FZERO
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fbne .LL100
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sll INCX, ZBASE_SHIFT, INCX
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FCMP ALPHA_I, FZERO
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fbne .LL100
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nop
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cmp INCX, 2 * SIZE
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bne .LL50
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nop
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sra N, 2, I
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cmp I, 0
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ble,pn %icc, .LL15
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nop
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.LL11:
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prefetch [X + PREFETCHSIZE * SIZE], 0
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STF FZERO, [X + 0 * SIZE]
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add I, -1, I
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STF FZERO, [X + 1 * SIZE]
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cmp I, 0
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STF FZERO, [X + 2 * SIZE]
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STF FZERO, [X + 3 * SIZE]
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STF FZERO, [X + 4 * SIZE]
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STF FZERO, [X + 5 * SIZE]
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add X, 8 * SIZE, X
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STF FZERO, [X - 2 * SIZE]
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bg,pt %icc, .LL11
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STF FZERO, [X - 1 * SIZE]
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.LL15:
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and N, 3, I
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cmp I, 0
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ble,a,pn %icc, .LL19
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nop
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.LL16:
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STF FZERO, [X + 0 * SIZE]
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STF FZERO, [X + 1 * SIZE]
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add I, -1, I
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cmp I, 0
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bg,pt %icc, .LL16
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add X, 2 * SIZE, X
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.LL19:
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return %i7 + 8
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clr %o0
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.LL50:
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sra N, 2, I
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cmp I, 0
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ble,pn %icc, .LL55
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nop
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.LL51:
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STF FZERO, [X + 0 * SIZE]
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add I, -1, I
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STF FZERO, [X + 1 * SIZE]
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add X, INCX, X
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STF FZERO, [X + 0 * SIZE]
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cmp I, 0
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STF FZERO, [X + 1 * SIZE]
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add X, INCX, X
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STF FZERO, [X + 0 * SIZE]
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STF FZERO, [X + 1 * SIZE]
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add X, INCX, X
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STF FZERO, [X + 0 * SIZE]
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STF FZERO, [X + 1 * SIZE]
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bg,pt %icc, .LL51
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add X, INCX, X
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.LL55:
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and N, 3, I
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cmp I, 0
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ble,a,pn %icc, .LL59
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nop
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.LL56:
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STF FZERO, [X + 0 * SIZE]
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add I, -1, I
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STF FZERO, [X + 1 * SIZE]
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cmp I, 0
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bg,pt %icc, .LL56
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add X, INCX, X
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.LL59:
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return %i7 + 8
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clr %o0
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.LL100:
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cmp INCX, 2 * SIZE
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bne .LL150
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sra N, 2, I
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cmp I, 0
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ble,pn %icc, .LL115
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nop
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LDF [X + 0 * SIZE], c1
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LDF [X + 1 * SIZE], c2
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LDF [X + 2 * SIZE], c3
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LDF [X + 3 * SIZE], c4
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LDF [X + 4 * SIZE], c5
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LDF [X + 5 * SIZE], c6
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LDF [X + 6 * SIZE], c7
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LDF [X + 7 * SIZE], c8
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FMUL ALPHA_R, c1, t1
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FMUL ALPHA_I, c2, t3
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FMUL ALPHA_I, c1, t2
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LDF [X + 8 * SIZE], c1
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FMUL ALPHA_R, c2, t4
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LDF [X + 9 * SIZE], c2
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FMUL ALPHA_R, c3, t5
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deccc I
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FMUL ALPHA_I, c4, t7
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FSUB t1, t3, s1
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FMUL ALPHA_I, c3, t6
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LDF [X + 10 * SIZE], c3
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FMUL ALPHA_R, c4, t8
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LDF [X + 11 * SIZE], c4
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FADD t4, t2, s2
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ble,pn %icc, .LL112
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nop
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.LL111:
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prefetch [X + PREFETCHSIZE * SIZE], 0
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FMUL ALPHA_R, c5, t1
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FMUL ALPHA_I, c6, t3
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FSUB t5, t7, s3
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STF s1, [X + 0 * SIZE]
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FMUL ALPHA_I, c5, t2
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LDF [X + 12 * SIZE], c5
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FMUL ALPHA_R, c6, t4
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LDF [X + 13 * SIZE], c6
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FADD t8, t6, s4
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STF s2, [X + 1 * SIZE]
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FMUL ALPHA_R, c7, t5
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FMUL ALPHA_I, c8, t7
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FSUB t1, t3, s5
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STF s3, [X + 2 * SIZE]
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FMUL ALPHA_I, c7, t6
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LDF [X + 14 * SIZE], c7
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FMUL ALPHA_R, c8, t8
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LDF [X + 15 * SIZE], c8
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FADD t4, t2, s6
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STF s4, [X + 3 * SIZE]
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FMUL ALPHA_R, c1, t1
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FMUL ALPHA_I, c2, t3
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FSUB t5, t7, s7
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STF s5, [X + 4 * SIZE]
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FMUL ALPHA_I, c1, t2
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LDF [X + 16 * SIZE], c1
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FMUL ALPHA_R, c2, t4
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LDF [X + 17 * SIZE], c2
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FADD t8, t6, s8
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STF s6, [X + 5 * SIZE]
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FMUL ALPHA_R, c3, t5
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deccc I
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FMUL ALPHA_I, c4, t7
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FSUB t1, t3, s1
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STF s7, [X + 6 * SIZE]
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FMUL ALPHA_I, c3, t6
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LDF [X + 18 * SIZE], c3
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FMUL ALPHA_R, c4, t8
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LDF [X + 19 * SIZE], c4
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FADD t4, t2, s2
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STF s8, [X + 7 * SIZE]
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bg,pt %icc, .LL111
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add X, 8 * SIZE, X
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.LL112:
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FMUL ALPHA_R, c5, t1
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FMUL ALPHA_I, c6, t3
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FSUB t5, t7, s3
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STF s1, [X + 0 * SIZE]
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FMUL ALPHA_I, c5, t2
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FMUL ALPHA_R, c6, t4
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FADD t8, t6, s4
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STF s2, [X + 1 * SIZE]
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FMUL ALPHA_R, c7, t5
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FMUL ALPHA_I, c8, t7
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FSUB t1, t3, s5
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STF s3, [X + 2 * SIZE]
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FMUL ALPHA_I, c7, t6
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FMUL ALPHA_R, c8, t8
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FADD t4, t2, s6
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STF s4, [X + 3 * SIZE]
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FSUB t5, t7, s7
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FADD t8, t6, s8
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STF s5, [X + 4 * SIZE]
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STF s6, [X + 5 * SIZE]
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STF s7, [X + 6 * SIZE]
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STF s8, [X + 7 * SIZE]
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add X, 8 * SIZE, X
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.LL115:
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and N, 3, I
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cmp I, 0
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ble,a,pn %icc, .LL119
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nop
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.LL116:
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LDF [X + 0 * SIZE], c1
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LDF [X + 1 * SIZE], c2
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FMUL ALPHA_R, c1, c3
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FMUL ALPHA_I, c1, c4
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FMUL ALPHA_I, c2, c1
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FMUL ALPHA_R, c2, c2
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FSUB c3, c1, c1
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FADD c2, c4, c2
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STF c1, [X + 0 * SIZE]
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STF c2, [X + 1 * SIZE]
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add I, -1, I
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cmp I, 0
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bg,pt %icc, .LL116
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add X, 2 * SIZE, X
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.LL119:
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return %i7 + 8
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clr %o0
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.LL150:
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sra N, 2, I
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cmp I, 0
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ble,pn %icc, .LL155
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mov X, XX
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.LL151:
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LDF [X + 0 * SIZE], c1
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LDF [X + 1 * SIZE], c2
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add X, INCX, X
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LDF [X + 0 * SIZE], c3
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FMUL ALPHA_R, c1, c9
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LDF [X + 1 * SIZE], c4
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FMUL ALPHA_I, c1, c10
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add X, INCX, X
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LDF [X + 0 * SIZE], c5
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FMUL ALPHA_I, c2, c1
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LDF [X + 1 * SIZE], c6
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FMUL ALPHA_R, c2, c2
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add X, INCX, X
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LDF [X + 0 * SIZE], c7
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FMUL ALPHA_R, c3, c11
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LDF [X + 1 * SIZE], c8
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FMUL ALPHA_I, c3, c12
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add X, INCX, X
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FMUL ALPHA_I, c4, c3
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FMUL ALPHA_R, c4, c4
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FMUL ALPHA_R, c5, c13
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FMUL ALPHA_I, c5, c14
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FMUL ALPHA_I, c6, c5
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FMUL ALPHA_R, c6, c6
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FMUL ALPHA_R, c7, c15
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FSUB c9, c1, c1
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FMUL ALPHA_I, c7, c16
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FADD c2, c10, c2
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FMUL ALPHA_I, c8, c7
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FSUB c11, c3, c3
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FMUL ALPHA_R, c8, c8
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FADD c4, c12, c4
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STF c1, [XX + 0 * SIZE]
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FSUB c13, c5, c5
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add I, -1, I
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STF c2, [XX + 1 * SIZE]
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FADD c6, c14, c6
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add XX, INCX, XX
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STF c3, [XX + 0 * SIZE]
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FSUB c15, c7, c7
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cmp I, 0
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STF c4, [XX + 1 * SIZE]
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FADD c8, c16, c8
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add XX, INCX, XX
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STF c5, [XX + 0 * SIZE]
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STF c6, [XX + 1 * SIZE]
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add XX, INCX, XX
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STF c7, [XX + 0 * SIZE]
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STF c8, [XX + 1 * SIZE]
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bg,pt %icc, .LL151
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add XX, INCX, XX
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.LL155:
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and N, 3, I
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cmp I, 0
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ble,a,pn %icc, .LL159
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nop
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.LL156:
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LDF [X + 0 * SIZE], c1
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LDF [X + 1 * SIZE], c2
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FMUL ALPHA_R, c1, c3
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FMUL ALPHA_I, c1, c4
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FMUL ALPHA_I, c2, c1
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FMUL ALPHA_R, c2, c2
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FSUB c3, c1, c1
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FADD c2, c4, c2
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STF c1, [X + 0 * SIZE]
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STF c2, [X + 1 * SIZE]
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add I, -1, I
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cmp I, 0
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bg,pt %icc, .LL156
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add X, INCX, X
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.LL159:
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return %i7 + 8
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clr %o0
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EPILOGUE
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