310ea55f29
ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
334 lines
8.3 KiB
C
334 lines
8.3 KiB
C
/**************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#include <string.h>
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#define CPU_UNKNOWN 0
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#define CPU_ARMV8 1
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// Arm
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#define CPU_CORTEXA53 2
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#define CPU_CORTEXA57 3
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#define CPU_CORTEXA72 4
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#define CPU_CORTEXA73 5
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// Qualcomm
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#define CPU_FALKOR 6
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// Cavium
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#define CPU_THUNDERX 7
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#define CPU_THUNDERX2T99 8
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static char *cpuname[] = {
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"UNKNOWN",
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"ARMV8" ,
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"CORTEXA53",
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"CORTEXA57",
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"CORTEXA72",
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"CORTEXA73",
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"FALKOR",
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"THUNDERX",
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"THUNDERX2T99"
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};
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static char *cpuname_lower[] = {
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"unknown",
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"armv8",
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"cortexa53",
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"cortexa57",
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"cortexa72",
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"cortexa73",
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"falkor",
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"thunderx",
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"thunderx2t99"
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};
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int get_feature(char *search)
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{
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#ifdef linux
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FILE *infile;
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char buffer[2048], *p,*t;
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p = (char *) NULL ;
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infile = fopen("/proc/cpuinfo", "r");
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while (fgets(buffer, sizeof(buffer), infile))
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{
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if (!strncmp("Features", buffer, 8))
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{
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p = strchr(buffer, ':') + 2;
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break;
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}
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}
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fclose(infile);
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if( p == NULL ) return 0;
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t = strtok(p," ");
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while( t = strtok(NULL," "))
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{
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if (!strcmp(t, search)) { return(1); }
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}
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#endif
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return(0);
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}
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int detect(void)
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{
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#ifdef linux
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FILE *infile;
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char buffer[512], *p, *cpu_part = NULL, *cpu_implementer = NULL;
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p = (char *) NULL ;
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infile = fopen("/proc/cpuinfo", "r");
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while (fgets(buffer, sizeof(buffer), infile)) {
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if ((cpu_part != NULL) && (cpu_implementer != NULL)) {
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break;
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}
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if ((cpu_part == NULL) && !strncmp("CPU part", buffer, 8)) {
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cpu_part = strchr(buffer, ':') + 2;
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cpu_part = strdup(cpu_part);
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} else if ((cpu_implementer == NULL) && !strncmp("CPU implementer", buffer, 15)) {
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cpu_implementer = strchr(buffer, ':') + 2;
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cpu_implementer = strdup(cpu_implementer);
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}
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}
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fclose(infile);
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if(cpu_part != NULL && cpu_implementer != NULL) {
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// Arm
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if (strstr(cpu_implementer, "0x41")) {
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if (strstr(cpu_part, "0xd03"))
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return CPU_CORTEXA53;
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else if (strstr(cpu_part, "0xd07"))
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return CPU_CORTEXA57;
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else if (strstr(cpu_part, "0xd08"))
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return CPU_CORTEXA72;
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else if (strstr(cpu_part, "0xd09"))
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return CPU_CORTEXA73;
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}
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// Qualcomm
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else if (strstr(cpu_implementer, "0x51") && strstr(cpu_part, "0xc00"))
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return CPU_FALKOR;
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// Cavium
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else if (strstr(cpu_implementer, "0x43") && strstr(cpu_part, "0x0a1"))
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return CPU_THUNDERX;
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else if (strstr(cpu_implementer, "0x43") && strstr(cpu_part, "0x0af"))
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return CPU_THUNDERX2T99;
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}
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p = (char *) NULL ;
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infile = fopen("/proc/cpuinfo", "r");
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while (fgets(buffer, sizeof(buffer), infile))
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{
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if ((!strncmp("model name", buffer, 10)) || (!strncmp("Processor", buffer, 9)) ||
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(!strncmp("CPU architecture", buffer, 16)))
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{
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p = strchr(buffer, ':') + 2;
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break;
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}
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}
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fclose(infile);
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if(p != NULL)
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{
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if ((strstr(p, "AArch64")) || (strstr(p, "8")))
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{
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return CPU_ARMV8;
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}
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}
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#endif
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return CPU_UNKNOWN;
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}
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char *get_corename(void)
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{
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return cpuname[detect()];
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}
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void get_architecture(void)
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{
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printf("ARM64");
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}
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void get_subarchitecture(void)
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{
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int d = detect();
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printf("%s", cpuname[d]);
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}
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void get_subdirname(void)
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{
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printf("arm64");
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}
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void get_cpuconfig(void)
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{
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// All arches should define ARMv8
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printf("#define ARMV8\n");
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printf("#define HAVE_NEON\n"); // This shouldn't be necessary
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printf("#define HAVE_VFPV4\n"); // This shouldn't be necessary
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int d = detect();
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switch (d)
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{
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case CPU_CORTEXA53:
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printf("#define %s\n", cpuname[d]);
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// Fall-through
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case CPU_ARMV8:
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// Minimum parameters for ARMv8 (based on A53)
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printf("#define L1_DATA_SIZE 32768\n");
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printf("#define L1_DATA_LINESIZE 64\n");
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printf("#define L2_SIZE 262144\n");
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printf("#define L2_LINESIZE 64\n");
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printf("#define DTB_DEFAULT_ENTRIES 64\n");
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printf("#define DTB_SIZE 4096\n");
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printf("#define L2_ASSOCIATIVE 4\n");
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break;
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case CPU_CORTEXA57:
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case CPU_CORTEXA72:
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case CPU_CORTEXA73:
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// Common minimum settings for these Arm cores
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// Can change a lot, but we need to be conservative
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// TODO: detect info from /sys if possible
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printf("#define %s\n", cpuname[d]);
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printf("#define L1_CODE_SIZE 49152\n");
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printf("#define L1_CODE_LINESIZE 64\n");
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printf("#define L1_CODE_ASSOCIATIVE 3\n");
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printf("#define L1_DATA_SIZE 32768\n");
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printf("#define L1_DATA_LINESIZE 64\n");
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printf("#define L1_DATA_ASSOCIATIVE 2\n");
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printf("#define L2_SIZE 524288\n");
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printf("#define L2_LINESIZE 64\n");
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printf("#define L2_ASSOCIATIVE 16\n");
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printf("#define DTB_DEFAULT_ENTRIES 64\n");
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printf("#define DTB_SIZE 4096\n");
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break;
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case CPU_FALKOR:
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printf("#define FALKOR\n");
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printf("#define L1_CODE_SIZE 65536\n");
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printf("#define L1_CODE_LINESIZE 64\n");
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printf("#define L1_DATA_SIZE 32768\n");
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printf("#define L1_DATA_LINESIZE 128\n");
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printf("#define L2_SIZE 524288\n");
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printf("#define L2_LINESIZE 64\n");
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printf("#define DTB_DEFAULT_ENTRIES 64\n");
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printf("#define DTB_SIZE 4096\n");
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printf("#define L2_ASSOCIATIVE 16\n");
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break;
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case CPU_THUNDERX:
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printf("#define THUNDERX\n");
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printf("#define L1_DATA_SIZE 32768\n");
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printf("#define L1_DATA_LINESIZE 128\n");
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printf("#define L2_SIZE 16777216\n");
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printf("#define L2_LINESIZE 128\n");
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printf("#define DTB_DEFAULT_ENTRIES 64\n");
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printf("#define DTB_SIZE 4096\n");
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printf("#define L2_ASSOCIATIVE 16\n");
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break;
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case CPU_THUNDERX2T99:
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printf("#define VULCAN \n");
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printf("#define L1_CODE_SIZE 32768 \n");
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printf("#define L1_CODE_LINESIZE 64 \n");
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printf("#define L1_CODE_ASSOCIATIVE 8 \n");
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printf("#define L1_DATA_SIZE 32768 \n");
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printf("#define L1_DATA_LINESIZE 64 \n");
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printf("#define L1_DATA_ASSOCIATIVE 8 \n");
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printf("#define L2_SIZE 262144 \n");
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printf("#define L2_LINESIZE 64 \n");
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printf("#define L2_ASSOCIATIVE 8 \n");
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printf("#define L3_SIZE 33554432 \n");
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printf("#define L3_LINESIZE 64 \n");
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printf("#define L3_ASSOCIATIVE 32 \n");
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printf("#define DTB_DEFAULT_ENTRIES 64 \n");
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printf("#define DTB_SIZE 4096 \n");
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break;
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}
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}
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void get_libname(void)
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{
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int d = detect();
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printf("%s", cpuname_lower[d]);
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}
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void get_features(void)
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{
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#ifdef linux
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FILE *infile;
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char buffer[2048], *p,*t;
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p = (char *) NULL ;
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infile = fopen("/proc/cpuinfo", "r");
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while (fgets(buffer, sizeof(buffer), infile))
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{
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if (!strncmp("Features", buffer, 8))
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{
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p = strchr(buffer, ':') + 2;
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break;
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}
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}
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fclose(infile);
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if( p == NULL ) return;
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t = strtok(p," ");
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while( t = strtok(NULL," "))
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{
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}
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#endif
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return;
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}
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