321 lines
6.9 KiB
ArmAsm
321 lines
6.9 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2015, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define M x0 /* Y vector length */
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#define N x1 /* X vector length */
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#define A x3 /* A vector address */
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#define LDA x4 /* A stride */
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#define X x5 /* X vector address */
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#define INC_X x6 /* X stride */
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#define Y x7 /* Y vector address */
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#define INC_Y x2 /* Y stride */
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#define A_PTR x9 /* loop A vector address */
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#define Y_IPTR x10 /* loop Y vector address */
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#define J x11 /* loop variable */
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#define I x12 /* loop variable */
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#define Y_OPTR x13 /* loop Y vector address */
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/*******************************************************************************
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* Macro definitions
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*******************************************************************************/
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#if !defined(DOUBLE)
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#define ALPHA s0
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#define TEMP s1
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#define TEMPV {v1.s}[0]
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#define TMP1 s2
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#define TMPV1 {v2.s}[0]
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#define TMP2 s3
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#define TMPV2 {v3.s}[0]
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#define SZ 4
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#define SHZ 2
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#else
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#define ALPHA d0
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#define TEMP d1
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#define TEMPV {v1.d}[0]
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#define TMP1 d2
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#define TMPV1 {v2.d}[0]
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#define TMP2 d3
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#define TMPV2 {v3.d}[0]
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#define SZ 8
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#define SHZ 3
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#endif
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/******************************************************************************/
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.macro SAVE_REGS
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add sp, sp, #-(11 * 16)
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stp d8, d9, [sp, #(0 * 16)]
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stp d10, d11, [sp, #(1 * 16)]
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stp d12, d13, [sp, #(2 * 16)]
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stp d14, d15, [sp, #(3 * 16)]
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stp d16, d17, [sp, #(4 * 16)]
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stp x18, x19, [sp, #(5 * 16)]
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stp x20, x21, [sp, #(6 * 16)]
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stp x22, x23, [sp, #(7 * 16)]
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stp x24, x25, [sp, #(8 * 16)]
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stp x26, x27, [sp, #(9 * 16)]
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str x28, [sp, #(10 * 16)]
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.endm
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.macro RESTORE_REGS
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ldp d8, d9, [sp, #(0 * 16)]
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ldp d10, d11, [sp, #(1 * 16)]
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ldp d12, d13, [sp, #(2 * 16)]
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ldp d14, d15, [sp, #(3 * 16)]
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ldp d16, d17, [sp, #(4 * 16)]
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ldp x18, x19, [sp, #(5 * 16)]
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ldp x20, x21, [sp, #(6 * 16)]
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ldp x22, x23, [sp, #(7 * 16)]
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ldp x24, x25, [sp, #(8 * 16)]
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ldp x26, x27, [sp, #(9 * 16)]
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ldr x28, [sp, #(10 * 16)]
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add sp, sp, #(11*16)
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.endm
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.macro KERNEL_F16
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#if !defined(DOUBLE)
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ld1 {v2.4s, v3.4s}, [A_PTR], #32
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ld1 {v4.4s, v5.4s}, [Y_IPTR], #32
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fmla v4.4s, v1.4s, v2.4s
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fmla v5.4s, v1.4s, v3.4s
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st1 {v4.4s, v5.4s}, [Y_OPTR], #32
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ld1 {v6.4s, v7.4s}, [A_PTR], #32
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ld1 {v8.4s, v9.4s}, [Y_IPTR], #32
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fmla v8.4s, v1.4s, v6.4s
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fmla v9.4s, v1.4s, v7.4s
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st1 {v8.4s, v9.4s}, [Y_OPTR], #32
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#else //DOUBLE
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ld1 {v2.2d, v3.2d}, [A_PTR], #32
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ld1 {v4.2d, v5.2d}, [Y_IPTR], #32
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fmla v4.2d, v1.2d, v2.2d
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fmla v5.2d, v1.2d, v3.2d
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st1 {v4.2d, v5.2d}, [Y_OPTR], #32
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ld1 {v6.2d, v7.2d}, [A_PTR], #32
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ld1 {v8.2d, v9.2d}, [Y_IPTR], #32
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fmla v8.2d, v1.2d, v6.2d
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fmla v9.2d, v1.2d, v7.2d
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st1 {v8.2d, v9.2d}, [Y_OPTR], #32
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ld1 {v10.2d, v11.2d}, [A_PTR], #32
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ld1 {v12.2d, v13.2d}, [Y_IPTR], #32
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fmla v12.2d, v1.2d, v10.2d
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fmla v13.2d, v1.2d, v11.2d
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st1 {v12.2d, v13.2d}, [Y_OPTR], #32
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ld1 {v14.2d, v15.2d}, [A_PTR], #32
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ld1 {v16.2d, v17.2d}, [Y_IPTR], #32
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fmla v16.2d, v1.2d, v14.2d
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fmla v17.2d, v1.2d, v15.2d
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st1 {v16.2d, v17.2d}, [Y_OPTR], #32
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#endif
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.endm
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.macro KERNEL_F4
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#if !defined(DOUBLE)
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ld1 {v2.4s}, [A_PTR], #16
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ld1 {v3.4s}, [Y_IPTR], #16
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fmla v3.4s, v1.4s, v2.4s
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st1 {v3.4s}, [Y_OPTR], #16
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#else
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ld1 {v2.2d}, [A_PTR], #16
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ld1 {v3.2d}, [Y_IPTR], #16
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fmla v3.2d, v1.2d, v2.2d
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st1 {v3.2d}, [Y_OPTR], #16
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ld1 {v4.2d}, [A_PTR], #16
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ld1 {v5.2d}, [Y_IPTR], #16
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fmla v5.2d, v1.2d, v4.2d
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st1 {v5.2d}, [Y_OPTR], #16
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#endif
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.endm
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.macro KERNEL_F1
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ld1 TMPV1, [A_PTR], #SZ
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ld1 TMPV2, [Y_IPTR]
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fmadd TMP2, TEMP, TMP1, TMP2
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st1 TMPV2, [Y_IPTR], #SZ
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.endm
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.macro INIT_S
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lsl INC_Y, INC_Y, #SHZ
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.endm
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.macro KERNEL_S1
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ld1 TMPV1, [A_PTR], #SZ
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ld1 TMPV2, [Y_IPTR]
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fmadd TMP2, TEMP, TMP1, TMP2
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st1 TMPV2, [Y_IPTR], INC_Y
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.endm
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/*******************************************************************************
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* End of macro definitions
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*******************************************************************************/
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PROLOGUE
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ldr INC_Y, [sp]
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SAVE_REGS
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cmp N, xzr
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ble gemv_n_kernel_L999
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cmp M, xzr
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ble gemv_n_kernel_L999
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lsl LDA, LDA, #SHZ
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lsl INC_X, INC_X, #SHZ
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mov J, N
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cmp INC_Y, #1
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bne gemv_n_kernel_S_BEGIN
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gemv_n_kernel_F_LOOP:
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ld1 TEMPV, [X], INC_X
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fmul TEMP, ALPHA, TEMP
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#if !defined(DOUBLE)
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ins v1.s[1], v1.s[0]
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ins v1.s[2], v1.s[0]
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ins v1.s[3], v1.s[0]
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#else
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ins v1.d[1], v1.d[0]
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#endif
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mov A_PTR, A
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mov Y_IPTR, Y
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mov Y_OPTR, Y
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gemv_n_kernel_F32:
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asr I, M, #5
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cmp I, xzr
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beq gemv_n_kernel_F4
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gemv_n_kernel_F320:
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KERNEL_F16
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KERNEL_F16
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subs I, I, #1
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bne gemv_n_kernel_F320
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gemv_n_kernel_F4:
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ands I, M, #31
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asr I, I, #2
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cmp I, xzr
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beq gemv_n_kernel_F1
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gemv_n_kernel_F40:
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KERNEL_F4
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subs I, I, #1
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bne gemv_n_kernel_F40
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gemv_n_kernel_F1:
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ands I, M, #3
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ble gemv_n_kernel_F_END
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gemv_n_kernel_F10:
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KERNEL_F1
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subs I, I, #1
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bne gemv_n_kernel_F10
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gemv_n_kernel_F_END:
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add A, A, LDA
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subs J, J, #1
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bne gemv_n_kernel_F_LOOP
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b gemv_n_kernel_L999
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gemv_n_kernel_S_BEGIN:
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INIT_S
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gemv_n_kernel_S_LOOP:
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ld1 TEMPV, [X], INC_X
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fmul TEMP, ALPHA, TEMP
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mov A_PTR, A
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mov Y_IPTR, Y
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asr I, M, #2
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cmp I, xzr
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ble gemv_n_kernel_S1
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gemv_n_kernel_S4:
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KERNEL_S1
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KERNEL_S1
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KERNEL_S1
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KERNEL_S1
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subs I, I, #1
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bne gemv_n_kernel_S4
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gemv_n_kernel_S1:
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ands I, M, #3
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ble gemv_n_kernel_S_END
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gemv_n_kernel_S10:
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KERNEL_S1
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subs I, I, #1
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bne gemv_n_kernel_S10
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gemv_n_kernel_S_END:
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add A, A, LDA
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subs J, J, #1
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bne gemv_n_kernel_S_LOOP
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gemv_n_kernel_L999:
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mov w0, wzr
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RESTORE_REGS
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ret
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EPILOGUE
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