407 lines
12 KiB
ArmAsm
407 lines
12 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2023, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#include "loongarch64_asm.S"
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/*********************************************************************
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* 2023/08/23 guxiwei
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* UTEST : OK
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* CTEST : OK
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* TEST : OK
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*********************************************************************/
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/* Function parameters */
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#define M $r4 // param 1: m
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#define N $r5 // param 2: n
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#define SRC $r6 // param 3: src
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#define LDA $r7 // param 4: lda
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#define DST $r8 // param 5: dst
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#define I $r9
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#define J $r10
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#define S0 $r11
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#define S1 $r12
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#define S2 $r13
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#define S3 $r14
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#define S4 $r15
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#define S5 $r16
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#define S6 $r17
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#define S7 $r18
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#define S8 $r19
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#define P0 $r20
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#define P1 $r23
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#define P2 $r24
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#define P3 $r25
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#define P4 $r26
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#define T0 $r27
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#define T1 $r28
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#define TL $r7
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#undef ZERO
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#define ZERO $r0
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/* LASX vectors */
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#define U0 $xr0
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#define U1 $xr1
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#define U2 $xr2
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#define U3 $xr3
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#define U4 $xr4
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#define U5 $xr5
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#define U6 $xr6
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#define U7 $xr7
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// Loops outline
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//.L_M8 <-------------------
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//| .L_N8: |
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//| .L_N7: | Main Loop
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//| .L_N4: |
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//| .L_N3: |
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//| .L_N2: |
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//| .L_N1: |
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//| .L_N0: ---------------
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//.L_M7
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//.L_M4
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//| .L_M4_N8:
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//| .L_M4_N7:
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//| .L_M4_N4:
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//| .L_M4_N3:
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//| .L_M4_N2:
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//| .L_M4_N1:
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//.L_M3
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//.L_M2
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//| .L_M2_N8:
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//| .L_M2_N7:
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//| .L_M2_N4:
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//| .L_M2_N3:
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//| .L_M2_N2:
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//| .L_M2_N1:
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//.L_M1
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//| .L_M1_N8:
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//| .L_M1_N7:
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//| .L_M1_N4:
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//| .L_M1_N3:
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//| .L_M1_N2:
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//| .L_M1_N1:
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//.L_M0
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PROLOGUE
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push_if_used 23, 8
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move S0, SRC
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move P0, DST
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PTR_SRAI T0, N, 0x04
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PTR_SRAI T1, N, 0x03
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PTR_SLLI T0, T0, 0x04
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PTR_SLLI T1, T1, 0x03
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PTR_MUL P2, M, T1
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PTR_SLLI P2, P2, 0x02
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PTR_ADD P2, DST, P2
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PTR_SRAI T0, N, 0x02
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PTR_SRAI T1, N, 0x01
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PTR_SLLI T0, T0, 0x02
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PTR_SLLI T1, T1, 0x01
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PTR_MUL P3, M, T0
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PTR_MUL P4, M, T1
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PTR_SLLI P3, P3, 0x02
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PTR_SLLI P4, P4, 0x02
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PTR_ADD P3, DST, P3
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PTR_ADD P4, DST, P4
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PTR_SLLI TL, LDA, 0x02
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PTR_SRAI J, M, 0x03
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PTR_SLLI T0, TL, 0x01
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PTR_SLLI T1, M, 0x05
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beq ZERO, J, .L_M7
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.align 5
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.L_M8:
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move S1, S0
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PTR_ADD S2, S0, TL
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PTR_ADD S3, S1, T0
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PTR_ADD S4, S2, T0
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PTR_ADD S5, S3, T0
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PTR_ADD S6, S4, T0
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PTR_ADD S7, S5, T0
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PTR_ADD S8, S6, T0
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PTR_ADD S0, S7, T0
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move P1, P0
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PTR_ADDI P0, P0, 0x100
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PTR_SRAI I, N, 0x03
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PTR_ADDI J, J, -1
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beq ZERO, I, .L_N7
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.L_N8:
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xvld U0, S1, 0x00
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xvld U1, S2, 0x00
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xvld U2, S3, 0x00
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xvld U3, S4, 0x00
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xvld U4, S5, 0x00
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xvld U5, S6, 0x00
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xvld U6, S7, 0x00
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xvld U7, S8, 0x00
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GST xv, , U0, P1, 0x00, U1, P1, 0x20, U2, P1, 0x40, U3, P1, 0x60, \
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U4, P1, 0x80, U5, P1, 0xA0, U6, P1, 0xC0, U7, P1, 0xE0
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PTR_ADDI S1, S1, 0x20
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PTR_ADDI S2, S2, 0x20
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PTR_ADDI S3, S3, 0x20
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PTR_ADDI S4, S4, 0x20
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PTR_ADDI S5, S5, 0x20
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PTR_ADDI S6, S6, 0x20
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PTR_ADDI S7, S7, 0x20
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PTR_ADDI S8, S8, 0x20
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PTR_ADDI I, I, -1
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PTR_ADD P1, P1, T1
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blt ZERO, I, .L_N8
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.L_N7:
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andi I, N, 0x04
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beq ZERO, I, .L_N3
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.L_N4:
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GLD v, , $vr0, S1, 0x00, $vr1, S2, 0x00, $vr2, S3, 0x00, $vr3, S4, 0x00, \
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$vr4, S5, 0x00, $vr5, S6, 0x00, $vr6, S7, 0x00, $vr7, S8, 0x00
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GST v, , $vr0, P2, 0x00, $vr1, P2, 0x10, $vr2, P2, 0x20, $vr3, P2, 0x30, \
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$vr4, P2, 0x40, $vr5, P2, 0x50, $vr6, P2, 0x60, $vr7, P2, 0x70
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PTR_ADDI S1, S1, 0x10
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PTR_ADDI S2, S2, 0x10
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PTR_ADDI S3, S3, 0x10
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PTR_ADDI S4, S4, 0x10
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PTR_ADDI S5, S5, 0x10
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PTR_ADDI S6, S6, 0x10
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PTR_ADDI S7, S7, 0x10
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PTR_ADDI S8, S8, 0x10
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PTR_ADDI P2, P2, 0x80
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.L_N3:
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andi I, N, 0x02
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beq ZERO, I, .L_N1
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.L_N2:
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GLD f, d, $f0, S1, 0x00, $f1, S2, 0x00, $f2, S3, 0x00, $f3, S4, 0x00, \
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$f4, S5, 0x00, $f5, S6, 0x00, $f6, S7, 0x00, $f7, S8, 0x00
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GST f, d, $f0, P3, 0x00, $f1, P3, 0x08, $f2, P3, 0x10, $f3, P3, 0x18, \
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$f4, P3, 0x20, $f5, P3, 0x28, $f6, P3, 0x30, $f7, P3, 0x38
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PTR_ADDI S1, S1, 0x08
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PTR_ADDI S2, S2, 0x08
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PTR_ADDI S3, S3, 0x08
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PTR_ADDI S4, S4, 0x08
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PTR_ADDI S5, S5, 0x08
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PTR_ADDI S6, S6, 0x08
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PTR_ADDI S7, S7, 0x08
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PTR_ADDI S8, S8, 0x08
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PTR_ADDI P3, P3, 0x40
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.L_N1:
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andi I, N, 0x01
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beq ZERO, I, .L_N0
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GLD f, s, $f0, S1, 0x00, $f1, S2, 0x00, $f2, S3, 0x00, $f3, S4, 0x00, \
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$f4, S5, 0x00, $f5, S6, 0x00, $f6, S7, 0x00, $f7, S8, 0x00
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GST f, s, $f0, P4, 0x00, $f1, P4, 0x04, $f2, P4, 0x08, $f3, P4, 0x0C, \
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$f4, P4, 0x10, $f5, P4, 0x14, $f6, P4, 0x18, $f7, P4, 0x1C
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PTR_ADDI S1, S1, 0x04
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PTR_ADDI S2, S2, 0x04
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PTR_ADDI S3, S3, 0x04
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PTR_ADDI S4, S4, 0x04
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PTR_ADDI S5, S5, 0x04
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PTR_ADDI S6, S6, 0x04
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PTR_ADDI S7, S7, 0x04
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PTR_ADDI S8, S8, 0x04
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PTR_ADDI P4, P4, 0x20
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.L_N0:
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blt ZERO, J, .L_M8
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.L_M7:
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andi J, M, 0x04
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beq ZERO, J, .L_M3
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.L_M4:
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move S1, S0
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PTR_ADD S2, S0, TL
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PTR_ADD S3, S1, T0
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PTR_ADD S4, S2, T0
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PTR_ADD S0, S3, T0
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move P1, P0
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PTR_ADDI P0, P0, 0x80
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PTR_SRAI I, N, 0x03
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beq ZERO, I, .L_M4_N7
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.align 5
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.L_M4_N8:
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xvld U0, S1, 0x00
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xvld U1, S2, 0x00
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xvld U2, S3, 0x00
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xvld U3, S4, 0x00
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GST xv, , U0, P1, 0x00, U1, P1, 0x20, U2, P1, 0x40, U3, P1, 0x60
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PTR_ADDI S1, S1, 0x20
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PTR_ADDI S2, S2, 0x20
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PTR_ADDI S3, S3, 0x20
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PTR_ADDI S4, S4, 0x20
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PTR_ADDI I, I, -1
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PTR_ADD P1, P1, T1
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blt ZERO, I, .L_M4_N8
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.L_M4_N7:
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andi I, N, 0x04
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beq ZERO, I, .L_M4_N3
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.L_M4_N4:
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GLD v, , $vr0, S1, 0x00, $vr1, S2, 0x00, $vr2, S3, 0x00, $vr3, S4, 0x00
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GST v, , $vr0, P2, 0x00, $vr1, P2, 0x10, $vr2, P2, 0x20, $vr3, P2, 0x30
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PTR_ADDI S1, S1, 0x10
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PTR_ADDI S2, S2, 0x10
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PTR_ADDI S3, S3, 0x10
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PTR_ADDI S4, S4, 0x10
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PTR_ADDI P2, P2, 0x40
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.L_M4_N3:
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andi I, N, 0x02
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beq ZERO, I, .L_M4_N1
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.L_M4_N2:
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GLD f, d, $f0, S1, 0x00, $f1, S2, 0x00, $f2, S3, 0x00, $f3, S4, 0x00
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GST f, d, $f0, P3, 0x00, $f1, P3, 0x08, $f2, P3, 0x10, $f3, P3, 0x18
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PTR_ADDI S1, S1, 0x08
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PTR_ADDI S2, S2, 0x08
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PTR_ADDI S3, S3, 0x08
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PTR_ADDI S4, S4, 0x08
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PTR_ADDI P3, P3, 0x20
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.L_M4_N1:
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andi I, N, 0x01
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beq ZERO, I, .L_M3
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GLD f, s, $f0, S1, 0x00, $f1, S2, 0x00, $f2, S3, 0x00, $f3, S4, 0x00
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GST f, s, $f0, P4, 0x00, $f1, P4, 0x04, $f2, P4, 0x08, $f3, P4, 0x0C
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PTR_ADDI S1, S1, 0x04
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PTR_ADDI S2, S2, 0x04
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PTR_ADDI S3, S3, 0x04
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PTR_ADDI S4, S4, 0x04
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PTR_ADDI P4, P4, 0x10
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.L_M3:
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andi J, M, 0x02
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beq ZERO, J, .L_M1
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.L_M2:
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move S1, S0
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PTR_ADD S2, S0, TL
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PTR_ADD S0, S0, T0
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move P1, P0
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PTR_ADDI P0, P0, 0x40
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PTR_SRAI I, N, 0x03
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beq ZERO, I, .L_M2_N7
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.align 5
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.L_M2_N8:
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xvld U0, S1, 0x00
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xvld U1, S2, 0x00
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GST xv, , U0, P1, 0x00, U1, P1, 0x20
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PTR_ADDI S1, S1, 0x20
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PTR_ADDI S2, S2, 0x20
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PTR_ADDI I, I, -1
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PTR_ADD P1, P1, T1
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blt ZERO, I, .L_M2_N8
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.L_M2_N7:
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andi I, N, 0x04
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beq ZERO, I, .L_M2_N3
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.L_M2_N4:
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GLD v, , $vr0, S1, 0x00, $vr1, S2, 0x00
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GST v, , $vr0, P2, 0x00, $vr1, P2, 0x10
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PTR_ADDI S1, S1, 0x10
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PTR_ADDI S2, S2, 0x10
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PTR_ADDI P2, P2, 0x20
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.L_M2_N3:
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andi I, N, 0x02
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beq ZERO, I, .L_M2_N1
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.L_M2_N2:
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GLD f, d, $f0, S1, 0x00, $f1, S2, 0x00
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GST f, d, $f0, P3, 0x00, $f1, P3, 0x08
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PTR_ADDI S1, S1, 0x08
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PTR_ADDI S2, S2, 0x08
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PTR_ADDI P3, P3, 0x10
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.L_M2_N1:
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andi I, N, 0x01
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beq ZERO, I, .L_M1
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GLD f, s, $f0, S1, 0x00, $f1, S2, 0x00
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GST f, s, $f0, P4, 0x00, $f1, P4, 0x04
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PTR_ADDI S1, S1, 0x04
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PTR_ADDI S2, S2, 0x04
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PTR_ADDI P4, P4, 0x08
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.L_M1:
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andi J, M, 0x01
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beq ZERO, J, .L_M0
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move S1, S0
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PTR_ADD S2, S0, TL
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move P1, P0
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PTR_ADDI P0, P0, 0x20
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PTR_SRAI I, N, 0x03
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beq ZERO, I, .L_M1_N7
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.align 5
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.L_M1_N8:
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xvld U0, S1, 0x00
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GST xv, , U0, P1, 0x00
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PTR_ADDI S1, S1, 0x20
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PTR_ADDI I, I, -1
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PTR_ADD P1, P1, T1
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blt ZERO, I, .L_M1_N8
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.L_M1_N7:
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andi I, N, 0x04
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beq ZERO, I, .L_M1_N3
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.L_M1_N4:
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GLD v, , $vr0, S1, 0x00
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GST v, , $vr0, P2, 0x00
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PTR_ADDI S1, S1, 0x10
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PTR_ADDI P2, P2, 0x10
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.L_M1_N3:
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andi I, N, 0x02
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beq ZERO, I, .L_M1_N1
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.L_M1_N2:
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GLD f, d, $f0, S1, 0x00
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GST f, d, $f0, P3, 0x00
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PTR_ADDI S1, S1, 0x08
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PTR_ADDI P3, P3, 0x08
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.L_M1_N1:
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andi I, N, 0x01
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beq ZERO, I, .L_M0
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GLD f, s, $f0, S1, 0x00
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GST f, s, $f0, P4, 0x00
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PTR_ADDI S1, S1, 0x04
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PTR_ADDI P4, P4, 0x04
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.L_M0:
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pop_if_used 23, 8
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jirl $r0, $r1, 0x00
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EPILOGUE
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