804 lines
14 KiB
ArmAsm
804 lines
14 KiB
ArmAsm
/*********************************************************************/
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/* Copyright 2009, 2010 The University of Texas at Austin. */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or */
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/* without modification, are permitted provided that the following */
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/* conditions are met: */
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/* */
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/* 1. Redistributions of source code must retain the above */
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/* copyright notice, this list of conditions and the following */
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/* disclaimer. */
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/* */
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/* 2. Redistributions in binary form must reproduce the above */
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/* copyright notice, this list of conditions and the following */
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/* disclaimer in the documentation and/or other materials */
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/* provided with the distribution. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
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/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
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/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
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/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
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/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
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/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
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/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
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/* POSSIBILITY OF SUCH DAMAGE. */
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/* */
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/* The views and conclusions contained in the software and */
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/* documentation are those of the authors and should not be */
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/* interpreted as representing official policies, either expressed */
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/* or implied, of The University of Texas at Austin. */
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/*********************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define RET r3
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#define X r4
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#define INCX r5
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#define N r6
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#define NN r7
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#define XX r8
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#define PREA r9
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#define FZERO f1
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#define STACKSIZE 160
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PROLOGUE
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PROFCODE
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addi SP, SP, -STACKSIZE
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li r0, 0
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stfd f14, 0(SP)
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stfd f15, 8(SP)
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stfd f16, 16(SP)
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stfd f17, 24(SP)
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stfd f18, 32(SP)
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stfd f19, 40(SP)
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stfd f20, 48(SP)
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stfd f21, 56(SP)
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stfd f22, 64(SP)
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stfd f23, 72(SP)
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stfd f24, 80(SP)
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stfd f25, 88(SP)
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stfd f26, 96(SP)
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stfd f27, 104(SP)
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stfd f28, 112(SP)
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stfd f29, 120(SP)
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stfd f30, 128(SP)
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stfd f31, 136(SP)
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stw r0, 144(SP)
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lfs FZERO,144(SP)
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#ifdef F_INTERFACE
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LDINT N, 0(r3)
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LDINT INCX, 0(INCX)
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#else
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mr N, r3
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#endif
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li RET, 0
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mr NN, N
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mr XX, X
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slwi INCX, INCX, BASE_SHIFT
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li PREA, L1_PREFETCHSIZE
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cmpwi cr0, N, 0
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ble- LL(9999)
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cmpwi cr0, INCX, 0
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ble- LL(9999)
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LFD f1, 0 * SIZE(X)
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add X, X, INCX
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fabs f0, f1
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fabs f2, f1
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fabs f3, f1
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fabs f4, f1
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fabs f5, f1
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fabs f6, f1
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fabs f7, f1
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fabs f1, f1
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subi N, N, 1
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cmpwi cr0, INCX, SIZE
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bne- cr0, LL(100)
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srawi. r0, N, 4
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mtspr CTR, r0
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beq- cr0, LL(50)
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LFD f24, 0 * SIZE(X)
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LFD f25, 1 * SIZE(X)
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LFD f26, 2 * SIZE(X)
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LFD f27, 3 * SIZE(X)
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LFD f28, 4 * SIZE(X)
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LFD f29, 5 * SIZE(X)
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LFD f30, 6 * SIZE(X)
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LFD f31, 7 * SIZE(X)
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fabs f8, f24
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fabs f9, f25
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fabs f10, f26
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fabs f11, f27
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LFD f24, 8 * SIZE(X)
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LFD f25, 9 * SIZE(X)
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LFD f26, 10 * SIZE(X)
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LFD f27, 11 * SIZE(X)
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fabs f12, f28
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fabs f13, f29
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fabs f14, f30
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fabs f15, f31
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LFD f28, 12 * SIZE(X)
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LFD f29, 13 * SIZE(X)
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LFD f30, 14 * SIZE(X)
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LFD f31, 15 * SIZE(X)
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bdz LL(20)
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.align 4
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LL(10):
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fabs f8, f24
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fsel f1, f17, f9, f1
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fabs f9, f25
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fsel f2, f18, f10, f2
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fabs f10, f26
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fsel f3, f19, f11, f3
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fabs f11, f27
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LFD f24, 16 * SIZE(X)
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LFD f25, 17 * SIZE(X)
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LFD f26, 18 * SIZE(X)
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LFD f27, 19 * SIZE(X)
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fsel f4, f20, f12, f4
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fabs f12, f28
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fsel f5, f21, f13, f5
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fabs f13, f29
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fsel f6, f22, f14, f6
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fabs f14, f30
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fsel f7, f23, f15, f7
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fabs f15, f31
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LFD f28, 20 * SIZE(X)
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LFD f29, 21 * SIZE(X)
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LFD f30, 22 * SIZE(X)
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LFD f31, 23 * SIZE(X)
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fabs f8, f24
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fsel f1, f17, f9, f1
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fabs f9, f25
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fsel f2, f18, f10, f2
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fabs f10, f26
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fsel f3, f19, f11, f3
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fabs f11, f27
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LFD f24, 24 * SIZE(X)
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LFD f25, 25 * SIZE(X)
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LFD f26, 26 * SIZE(X)
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LFD f27, 27 * SIZE(X)
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fsel f4, f20, f12, f4
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fabs f12, f28
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fsel f5, f21, f13, f5
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fabs f13, f29
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fsel f6, f22, f14, f6
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fabs f14, f30
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fsel f7, f23, f15, f7
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fabs f15, f31
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LFD f28, 28 * SIZE(X)
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LFD f29, 29 * SIZE(X)
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LFD f30, 30 * SIZE(X)
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LFD f31, 31 * SIZE(X)
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#ifndef POWER6
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L1_PREFETCH X, PREA
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#endif
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addi X, X, 16 * SIZE
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#ifdef POWER6
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L1_PREFETCH X, PREA
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#endif
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bdnz LL(10)
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.align 4
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LL(20):
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fabs f8, f24
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fsel f1, f17, f9, f1
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fabs f9, f25
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fsel f2, f18, f10, f2
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fabs f10, f26
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fsel f3, f19, f11, f3
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fabs f11, f27
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fsel f4, f20, f12, f4
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fabs f12, f28
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fsel f5, f21, f13, f5
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fabs f13, f29
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fsel f6, f22, f14, f6
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fabs f14, f30
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fsel f7, f23, f15, f7
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fabs f15, f31
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fsel f1, f17, f9, f1
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fsel f2, f18, f10, f2
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fsel f3, f19, f11, f3
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fsel f4, f20, f12, f4
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fsel f5, f21, f13, f5
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fsel f6, f22, f14, f6
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fsel f7, f23, f15, f7
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addi X, X, 16 * SIZE
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.align 4
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LL(50):
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andi. r0, N, 15
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mtspr CTR, r0
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beq LL(999)
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.align 4
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LL(60):
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LFD f8, 0 * SIZE(X)
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addi X, X, 1 * SIZE
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fabs f8, f8
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fsub f16, f1, f8
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fsel f1, f16, f8, f1
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bdnz LL(60)
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b LL(999)
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.align 4
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LL(100):
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sub X, X, INCX
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srawi. r0, N, 4
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mtspr CTR, r0
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beq- LL(150)
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LFDUX f24, X, INCX
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LFDUX f25, X, INCX
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LFDUX f26, X, INCX
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LFDUX f27, X, INCX
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LFDUX f28, X, INCX
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LFDUX f29, X, INCX
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LFDUX f30, X, INCX
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LFDUX f31, X, INCX
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fabs f8, f24
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fabs f9, f25
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fabs f10, f26
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fabs f11, f27
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LFDUX f24, X, INCX
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LFDUX f25, X, INCX
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LFDUX f26, X, INCX
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LFDUX f27, X, INCX
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fabs f12, f28
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fabs f13, f29
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fabs f14, f30
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fabs f15, f31
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LFDUX f28, X, INCX
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LFDUX f29, X, INCX
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LFDUX f30, X, INCX
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LFDUX f31, X, INCX
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bdz LL(120)
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.align 4
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LL(110):
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fabs f8, f24
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fsel f1, f17, f9, f1
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fabs f9, f25
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fsel f2, f18, f10, f2
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fabs f10, f26
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fsel f3, f19, f11, f3
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fabs f11, f27
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LFDUX f24, X, INCX
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LFDUX f25, X, INCX
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LFDUX f26, X, INCX
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LFDUX f27, X, INCX
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fsel f4, f20, f12, f4
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fabs f12, f28
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fsel f5, f21, f13, f5
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fabs f13, f29
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fsel f6, f22, f14, f6
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fabs f14, f30
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fsel f7, f23, f15, f7
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fabs f15, f31
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LFDUX f28, X, INCX
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LFDUX f29, X, INCX
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LFDUX f30, X, INCX
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LFDUX f31, X, INCX
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fabs f8, f24
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fsel f1, f17, f9, f1
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fabs f9, f25
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fsel f2, f18, f10, f2
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fabs f10, f26
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fsel f3, f19, f11, f3
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fabs f11, f27
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LFDUX f24, X, INCX
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LFDUX f25, X, INCX
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LFDUX f26, X, INCX
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LFDUX f27, X, INCX
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fsel f4, f20, f12, f4
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fabs f12, f28
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fsel f5, f21, f13, f5
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fabs f13, f29
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fsel f6, f22, f14, f6
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fabs f14, f30
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fsel f7, f23, f15, f7
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fabs f15, f31
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LFDUX f28, X, INCX
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LFDUX f29, X, INCX
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LFDUX f30, X, INCX
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LFDUX f31, X, INCX
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bdnz LL(110)
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.align 4
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LL(120):
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fabs f8, f24
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fsel f1, f17, f9, f1
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fabs f9, f25
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fsel f2, f18, f10, f2
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fabs f10, f26
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fsel f3, f19, f11, f3
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fabs f11, f27
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fsel f4, f20, f12, f4
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fabs f12, f28
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fsel f5, f21, f13, f5
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fabs f13, f29
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fsel f6, f22, f14, f6
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fabs f14, f30
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fsel f7, f23, f15, f7
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fabs f15, f31
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fsub f16, f0, f8
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fsub f17, f1, f9
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fsub f18, f2, f10
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fsub f19, f3, f11
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fsub f20, f4, f12
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fsub f21, f5, f13
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fsub f22, f6, f14
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fsub f23, f7, f15
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fsel f0, f16, f8, f0
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fsel f1, f17, f9, f1
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fsel f2, f18, f10, f2
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fsel f3, f19, f11, f3
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fsel f4, f20, f12, f4
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fsel f5, f21, f13, f5
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fsel f6, f22, f14, f6
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fsel f7, f23, f15, f7
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.align 4
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LL(150):
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andi. r0, N, 15
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mtspr CTR, r0
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beq LL(999)
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.align 4
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LL(160):
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LFDUX f8, X, INCX
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fabs f8, f8
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fsub f16, f1, f8
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fsel f1, f16, f8, f1
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bdnz LL(160)
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.align 4
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LL(999):
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fsub f8, f0, f1
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fsub f9, f2, f3
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fsub f10, f4, f5
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fsub f11, f6, f7
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fsel f0, f8, f1, f0
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fsel f2, f9, f3, f2
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fsel f4, f10, f5, f4
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fsel f6, f11, f7, f6
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fsub f8, f0, f2
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fsub f9, f4, f6
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fsel f0, f8, f2, f0
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fsel f4, f9, f6, f4
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fsub f8, f0, f4
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fsel f1, f8, f4, f0
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.align 4
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LL(1000):
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cmpwi cr0, INCX, SIZE
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bne- cr0, LL(1100)
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srawi. r0, NN, 3
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mtspr CTR, r0
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beq- cr0, LL(1050)
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LFD f24, 0 * SIZE(XX)
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LFD f25, 1 * SIZE(XX)
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LFD f26, 2 * SIZE(XX)
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LFD f27, 3 * SIZE(XX)
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LFD f28, 4 * SIZE(XX)
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LFD f29, 5 * SIZE(XX)
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LFD f30, 6 * SIZE(XX)
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LFD f31, 7 * SIZE(XX)
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bdz LL(1020)
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.align 4
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LL(1010):
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fabs f8, f24
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fabs f9, f25
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fabs f10, f26
|
|
fabs f11, f27
|
|
|
|
LFD f24, 8 * SIZE(XX)
|
|
LFD f25, 9 * SIZE(XX)
|
|
LFD f26, 10 * SIZE(XX)
|
|
LFD f27, 11 * SIZE(XX)
|
|
|
|
fabs f12, f28
|
|
fabs f13, f29
|
|
fabs f14, f30
|
|
fabs f15, f31
|
|
|
|
LFD f28, 12 * SIZE(XX)
|
|
LFD f29, 13 * SIZE(XX)
|
|
LFD f30, 14 * SIZE(XX)
|
|
LFD f31, 15 * SIZE(XX)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f8
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f9
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f10
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f11
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f12
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f13
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f14
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f15
|
|
beq cr0, LL(9999)
|
|
|
|
addi XX, XX, 8 * SIZE
|
|
bdnz LL(1010)
|
|
.align 4
|
|
|
|
LL(1020):
|
|
fabs f8, f24
|
|
fabs f9, f25
|
|
fabs f10, f26
|
|
fabs f11, f27
|
|
|
|
fabs f12, f28
|
|
fabs f13, f29
|
|
fabs f14, f30
|
|
fabs f15, f31
|
|
|
|
addi XX, XX, 8 * SIZE
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f8
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f9
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f10
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f11
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f12
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f13
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f14
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f15
|
|
beq cr0, LL(9999)
|
|
.align 4
|
|
|
|
LL(1050):
|
|
andi. r0, NN, 7
|
|
mtspr CTR, r0
|
|
beq LL(9999)
|
|
.align 4
|
|
|
|
LL(1060):
|
|
LFD f8, 0 * SIZE(XX)
|
|
addi XX, XX, 1 * SIZE
|
|
fabs f8, f8
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f8
|
|
beq cr0, LL(9999)
|
|
bdnz LL(1060)
|
|
b LL(9999)
|
|
.align 4
|
|
|
|
LL(1100):
|
|
sub XX, XX, INCX
|
|
|
|
srawi. r0, NN, 3
|
|
mtspr CTR, r0
|
|
beq- LL(1150)
|
|
|
|
LFDUX f24, XX, INCX
|
|
LFDUX f25, XX, INCX
|
|
LFDUX f26, XX, INCX
|
|
LFDUX f27, XX, INCX
|
|
LFDUX f28, XX, INCX
|
|
LFDUX f29, XX, INCX
|
|
LFDUX f30, XX, INCX
|
|
LFDUX f31, XX, INCX
|
|
bdz LL(1120)
|
|
.align 4
|
|
|
|
LL(1110):
|
|
fabs f8, f24
|
|
fabs f9, f25
|
|
fabs f10, f26
|
|
fabs f11, f27
|
|
|
|
LFDUX f24, XX, INCX
|
|
LFDUX f25, XX, INCX
|
|
LFDUX f26, XX, INCX
|
|
LFDUX f27, XX, INCX
|
|
|
|
fabs f12, f28
|
|
fabs f13, f29
|
|
fabs f14, f30
|
|
fabs f15, f31
|
|
|
|
LFDUX f28, XX, INCX
|
|
LFDUX f29, XX, INCX
|
|
LFDUX f30, XX, INCX
|
|
LFDUX f31, XX, INCX
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f8
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f9
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f10
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f11
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f12
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f13
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f14
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f15
|
|
beq cr0, LL(9999)
|
|
|
|
bdnz LL(1110)
|
|
.align 4
|
|
|
|
LL(1120):
|
|
fabs f8, f24
|
|
fabs f9, f25
|
|
fabs f10, f26
|
|
fabs f11, f27
|
|
|
|
fabs f12, f28
|
|
fabs f13, f29
|
|
fabs f14, f30
|
|
fabs f15, f31
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f8
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f9
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f10
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f11
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f12
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f13
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f14
|
|
beq cr0, LL(9999)
|
|
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f15
|
|
beq cr0, LL(9999)
|
|
.align 4
|
|
|
|
LL(1150):
|
|
andi. r0, NN, 7
|
|
mtspr CTR, r0
|
|
beq LL(9999)
|
|
.align 4
|
|
|
|
LL(1160):
|
|
LFDUX f8, XX, INCX
|
|
fabs f8, f8
|
|
addi RET, RET, 1
|
|
fcmpu cr0, f1, f8
|
|
beq cr0, LL(9999)
|
|
bdnz LL(1160)
|
|
.align 4
|
|
|
|
LL(9999):
|
|
lfd f14, 0(SP)
|
|
lfd f15, 8(SP)
|
|
lfd f16, 16(SP)
|
|
lfd f17, 24(SP)
|
|
|
|
lfd f18, 32(SP)
|
|
lfd f19, 40(SP)
|
|
lfd f20, 48(SP)
|
|
lfd f21, 56(SP)
|
|
|
|
lfd f22, 64(SP)
|
|
lfd f23, 72(SP)
|
|
lfd f24, 80(SP)
|
|
lfd f25, 88(SP)
|
|
|
|
lfd f26, 96(SP)
|
|
lfd f27, 104(SP)
|
|
lfd f28, 112(SP)
|
|
lfd f29, 120(SP)
|
|
|
|
lfd f30, 128(SP)
|
|
lfd f31, 136(SP)
|
|
|
|
addi SP, SP, STACKSIZE
|
|
blr
|
|
|
|
EPILOGUE
|