9e2f316ede
Quoting patch author amodra from #1078 Lots of issues here. - The vsx regs weren't listed as clobbered. - Poor choice of vsx regs, which along with the lack of clobbers led to trashing v0..v21 and fr14..fr23. Ideally you'd let gcc choose all temp vsx regs, but asms currently have a limit of 30 i/o parms. - Other regs were clobbered unnecessarily, seemingly in an attempt to clobber inputs, with gcc-7 complaining about the clobber of r2. (Changed inputs should be also listed as outputs or as an i/o.) - "r" constraint used instead of "b" for gprs used in insns where the r0 encoding means zero rather than r0. - There were unused asm inputs too. - All memory was clobbered rather than hooking up memory outputs with proper memory constraints, and that and the lack of proper memory input constraints meant the asms needed to be volatile and their containing function noinline. - Some parameters were being passed unnecessarily via memory. - When a copy of a
260 lines
8.4 KiB
C
260 lines
8.4 KiB
C
/***************************************************************************
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Copyright (c) 2013-2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2016/03/23 Werner Saar (wernsaar@googlemail.com)
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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* LAPACK-TEST : OK
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**************************************************************************************/
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#define HAVE_KERNEL_4 1
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static void zaxpy_kernel_4 (long n, double *x, double *y,
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double alpha_r, double alpha_i)
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{
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#if !defined(CONJ)
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static const double mvec[2] = { -1.0, 1.0 };
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#else
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static const double mvec[2] = { 1.0, -1.0 };
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#endif
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const double *mvecp = mvec;
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__vector double t0;
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__vector double t1;
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__vector double t2;
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__vector double t3;
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__vector double t4;
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__vector double t5;
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__vector double t6;
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__vector double t7;
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__vector double t8;
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__vector double t9;
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__vector double t10;
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__vector double t11;
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long ytmp;
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__asm__
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(
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"xxspltd 32, %x19, 0 \n\t" // alpha_r
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"xxspltd 33, %x20, 0 \n\t" // alpha_i
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"lxvd2x 36, 0, %21 \n\t" // mvec
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#if !defined(CONJ)
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"xvmuldp 33, 33, 36 \n\t" // alpha_i * mvec
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#else
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"xvmuldp 32, 32, 36 \n\t" // alpha_r * mvec
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#endif
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"mr %16, %3 \n\t"
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"dcbt 0, %2 \n\t"
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"dcbt 0, %3 \n\t"
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"lxvd2x 40, 0, %2 \n\t" // x0
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"lxvd2x 41, %22, %2 \n\t" // x1
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"lxvd2x 42, %23, %2 \n\t" // x2
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"lxvd2x 43, %24, %2 \n\t" // x3
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"lxvd2x 48, 0, %3 \n\t" // y0
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"lxvd2x 49, %22, %3 \n\t" // y1
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"lxvd2x 50, %23, %3 \n\t" // y2
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"lxvd2x 51, %24, %3 \n\t" // y3
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"xxswapd %x8, 40 \n\t" // exchange real and imag part
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"xxswapd %x9, 41 \n\t" // exchange real and imag part
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"xxswapd %x10, 42 \n\t" // exchange real and imag part
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"xxswapd %x11, 43 \n\t" // exchange real and imag part
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"addi %2, %2, 64 \n\t"
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"addi %3, %3, 64 \n\t"
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"lxvd2x 44, 0, %2 \n\t" // x4
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"lxvd2x 45, %22, %2 \n\t" // x5
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"lxvd2x 46, %23, %2 \n\t" // x6
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"lxvd2x 47, %24, %2 \n\t" // x7
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"lxvd2x %x4, 0, %3 \n\t" // y4
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"lxvd2x %x5, %22, %3 \n\t" // y5
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"lxvd2x %x6, %23, %3 \n\t" // y6
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"lxvd2x %x7, %24, %3 \n\t" // y7
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"xxswapd %x12, 44 \n\t" // exchange real and imag part
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"xxswapd %x13, 45 \n\t" // exchange real and imag part
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"xxswapd %x14, 46 \n\t" // exchange real and imag part
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"xxswapd %x15, 47 \n\t" // exchange real and imag part
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"addi %2, %2, 64 \n\t"
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"addi %3, %3, 64 \n\t"
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"addic. %1, %1, -8 \n\t"
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"ble 2f \n\t"
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".p2align 5 \n"
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"1: \n\t"
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"xvmaddadp 48, 40, 32 \n\t" // alpha_r * x0_r , alpha_r * x0_i
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"xvmaddadp 49, 41, 32 \n\t"
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"lxvd2x 40, 0, %2 \n\t" // x0
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"lxvd2x 41, %22, %2 \n\t" // x1
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"xvmaddadp 50, 42, 32 \n\t"
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"xvmaddadp 51, 43, 32 \n\t"
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"lxvd2x 42, %23, %2 \n\t" // x2
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"lxvd2x 43, %24, %2 \n\t" // x3
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"xvmaddadp %x4, 44, 32 \n\t"
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"addi %2, %2, 64 \n\t"
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"xvmaddadp %x5, 45, 32 \n\t"
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"lxvd2x 44, 0, %2 \n\t" // x4
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"lxvd2x 45, %22, %2 \n\t" // x5
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"xvmaddadp %x6, 46, 32 \n\t"
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"xvmaddadp %x7, 47, 32 \n\t"
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"lxvd2x 46, %23, %2 \n\t" // x6
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"lxvd2x 47, %24, %2 \n\t" // x7
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"xvmaddadp 48, %x8, 33 \n\t" // alpha_i * x0_i , alpha_i * x0_r
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"addi %2, %2, 64 \n\t"
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"xvmaddadp 49, %x9, 33 \n\t"
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"xvmaddadp 50, %x10, 33 \n\t"
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"xvmaddadp 51, %x11, 33 \n\t"
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"xvmaddadp %x4, %x12, 33 \n\t"
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"xvmaddadp %x5, %x13, 33 \n\t"
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"xvmaddadp %x6, %x14, 33 \n\t"
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"xvmaddadp %x7, %x15, 33 \n\t"
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"stxvd2x 48, 0, %16 \n\t"
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"stxvd2x 49, %22, %16 \n\t"
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"stxvd2x 50, %23, %16 \n\t"
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"stxvd2x 51, %24, %16 \n\t"
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"addi %16, %16, 64 \n\t"
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"stxvd2x %x4, 0, %16 \n\t"
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"stxvd2x %x5, %22, %16 \n\t"
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"stxvd2x %x6, %23, %16 \n\t"
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"stxvd2x %x7, %24, %16 \n\t"
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"addi %16, %16, 64 \n\t"
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"xxswapd %x8, 40 \n\t" // exchange real and imag part
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"xxswapd %x9, 41 \n\t" // exchange real and imag part
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"lxvd2x 48, 0, %3 \n\t" // y0
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"lxvd2x 49, %22, %3 \n\t" // y1
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"xxswapd %x10, 42 \n\t" // exchange real and imag part
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"xxswapd %x11, 43 \n\t" // exchange real and imag part
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"lxvd2x 50, %23, %3 \n\t" // y2
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"lxvd2x 51, %24, %3 \n\t" // y3
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"xxswapd %x12, 44 \n\t" // exchange real and imag part
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"addi %3, %3, 64 \n\t"
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"xxswapd %x13, 45 \n\t" // exchange real and imag part
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"lxvd2x %x4, 0, %3 \n\t" // y4
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"lxvd2x %x5, %22, %3 \n\t" // y5
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"xxswapd %x14, 46 \n\t" // exchange real and imag part
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"xxswapd %x15, 47 \n\t" // exchange real and imag part
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"lxvd2x %x6, %23, %3 \n\t" // y6
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"lxvd2x %x7, %24, %3 \n\t" // y7
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"addi %3, %3, 64 \n\t"
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"addic. %1, %1, -8 \n\t"
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"bgt 1b \n"
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"2: \n\t"
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"xvmaddadp 48, 40, 32 \n\t" // alpha_r * x0_r , alpha_r * x0_i
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"xvmaddadp 49, 41, 32 \n\t"
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"xvmaddadp 50, 42, 32 \n\t"
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"xvmaddadp 51, 43, 32 \n\t"
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"xvmaddadp %x4, 44, 32 \n\t"
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"xvmaddadp %x5, 45, 32 \n\t"
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"xvmaddadp %x6, 46, 32 \n\t"
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"xvmaddadp %x7, 47, 32 \n\t"
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"xvmaddadp 48, %x8, 33 \n\t" // alpha_i * x0_i , alpha_i * x0_r
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"xvmaddadp 49, %x9, 33 \n\t"
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"xvmaddadp 50, %x10, 33 \n\t"
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"xvmaddadp 51, %x11, 33 \n\t"
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"xvmaddadp %x4, %x12, 33 \n\t"
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"xvmaddadp %x5, %x13, 33 \n\t"
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"xvmaddadp %x6, %x14, 33 \n\t"
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"xvmaddadp %x7, %x15, 33 \n\t"
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"stxvd2x 48, 0, %16 \n\t"
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"stxvd2x 49, %22, %16 \n\t"
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"stxvd2x 50, %23, %16 \n\t"
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"stxvd2x 51, %24, %16 \n\t"
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"addi %16, %16, 64 \n\t"
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"stxvd2x %x4, 0, %16 \n\t"
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"stxvd2x %x5, %22, %16 \n\t"
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"stxvd2x %x6, %23, %16 \n\t"
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"stxvd2x %x7, %24, %16 \n"
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"#n=%1 x=%17=%2 y=%0=%3 alpha=(%19,%20) mvecp=%18=%16 o16=%22 o32=%23 o48=%24 ytmp=%16\n"
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"#t0=%x4 t1=%x5 t2=%x6 t3=%x7 t4=%x8 t5=%x9 t6=%x10 t7=%x11 t8=%x12 t9=%x13 t10=%x14 t11=%x15"
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:
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"+m" (*y),
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"+r" (n), // 1
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"+b" (x), // 2
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"+b" (y), // 3
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"=wa" (t0), // 4
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"=wa" (t1), // 5
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"=wa" (t2), // 6
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"=wa" (t3), // 7
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"=wa" (t4), // 8
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"=wa" (t5), // 9
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"=wa" (t6), // 10
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"=wa" (t7), // 11
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"=wa" (t8), // 12
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"=wa" (t9), // 13
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"=wa" (t10), // 14
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"=wa" (t11), // 15
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"=b" (ytmp) // 16
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:
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"m" (*x),
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"m" (*mvecp),
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"d" (alpha_r), // 19
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"d" (alpha_i), // 20
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"16" (mvecp), // 21
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"b" (16), // 22
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"b" (32), // 23
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"b" (48) // 24
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:
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"cr0",
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"vs32","vs33","vs34","vs35","vs36","vs37","vs38","vs39",
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"vs40","vs41","vs42","vs43","vs44","vs45","vs46","vs47",
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"vs48","vs49","vs50","vs51"
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);
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}
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