348 lines
6.5 KiB
ArmAsm
348 lines
6.5 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2013/11/11 Saar
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* BLASTEST : OK
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* CTEST : OK (no test for dsdot)
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* TEST : OK (no test for dsdot)
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*
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**************************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define STACKSIZE 256
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#define N r0
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#define X r1
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#define INC_X r2
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#define OLD_Y r3
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/******************************************************
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* [fp, #-128] - [fp, #-64] is reserved
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* for store and restore of floating point
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* registers
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*******************************************************/
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#define OLD_INC_Y [fp, #4 ]
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#define I r5
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#define Y r6
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#define INC_Y r7
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#define X_PRE 512
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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#if defined(DSDOT)
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.macro KERNEL_F4
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fldmias X!, { s14 }
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fldmias Y!, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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fldmias X!, { s14 }
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fldmias Y!, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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fldmias X!, { s14 }
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fldmias Y!, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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fldmias X!, { s14 }
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fldmias Y!, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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.endm
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.macro KERNEL_F1
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fldmias X!, { s14 }
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fldmias Y!, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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.endm
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.macro KERNEL_S4
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nop
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fldmias X, { s14 }
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fldmias Y, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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add X, X, INC_X
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add Y, Y, INC_Y
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fldmias X, { s14 }
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fldmias Y, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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add X, X, INC_X
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add Y, Y, INC_Y
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fldmias X, { s14 }
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fldmias Y, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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add X, X, INC_X
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add Y, Y, INC_Y
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fldmias X, { s14 }
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fldmias Y, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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add X, X, INC_X
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add Y, Y, INC_Y
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.endm
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.macro KERNEL_S1
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fldmias X, { s14 }
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fldmias Y, { s15 }
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vmul.f32 s15, s14, s15
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vcvt.f64.f32 d4, s15
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vadd.f64 d0 , d0, d4
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add X, X, INC_X
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add Y, Y, INC_Y
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.endm
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#else
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.macro KERNEL_F4
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fldmias X!, { s8 - s9 }
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fldmias Y!, { s4 - s5}
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fmacs s0 , s4, s8
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fldmias X!, { s10 - s11 }
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fmacs s1 , s5, s9
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fldmias Y!, { s6 - s7 }
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fmacs s0 , s6, s10
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fmacs s1 , s7, s11
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.endm
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.macro KERNEL_F1
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fldmias X!, { s4 }
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fldmias Y!, { s8 }
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fmacs s0 , s4, s8
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.endm
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.macro KERNEL_S4
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nop
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fldmias X, { s4 }
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fldmias Y, { s8 }
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add X, X, INC_X
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add Y, Y, INC_Y
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fmacs s0 , s4, s8
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fldmias X, { s5 }
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fldmias Y, { s9 }
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add X, X, INC_X
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add Y, Y, INC_Y
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fmacs s1 , s5, s9
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fldmias X, { s6 }
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fldmias Y, { s10 }
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add X, X, INC_X
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add Y, Y, INC_Y
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fmacs s0 , s6, s10
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fldmias X, { s7 }
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fldmias Y, { s11 }
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add X, X, INC_X
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add Y, Y, INC_Y
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fmacs s1 , s7, s11
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.endm
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.macro KERNEL_S1
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fldmias X, { s4 }
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fldmias Y, { s8 }
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add X, X, INC_X
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fmacs s0 , s4, s8
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add Y, Y, INC_Y
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.endm
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#endif
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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push {r4 - r9, fp}
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add fp, sp, #24
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sub sp, sp, #STACKSIZE // reserve stack
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sub r4, fp, #128
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vstm r4, { s8 - s15 } // store floating point registers
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mov Y, OLD_Y
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ldr INC_Y, OLD_INC_Y
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#if defined(DSDOT)
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vsub.f64 d0 , d0 , d0
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vsub.f64 d1 , d1 , d1
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#else
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vsub.f32 s0 , s0 , s0
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vsub.f32 s1 , s1 , s1
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#endif
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cmp N, #0
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ble sdot_kernel_L999
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cmp INC_X, #0
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beq sdot_kernel_L999
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cmp INC_Y, #0
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beq sdot_kernel_L999
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cmp INC_X, #1
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bne sdot_kernel_S_BEGIN
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cmp INC_Y, #1
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bne sdot_kernel_S_BEGIN
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sdot_kernel_F_BEGIN:
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asrs I, N, #2 // I = N / 4
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ble sdot_kernel_F1
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sdot_kernel_F4:
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KERNEL_F4
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subs I, I, #1
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bne sdot_kernel_F4
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sdot_kernel_F1:
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ands I, N, #3
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ble sdot_kernel_L999
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sdot_kernel_F10:
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KERNEL_F1
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subs I, I, #1
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bne sdot_kernel_F10
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b sdot_kernel_L999
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sdot_kernel_S_BEGIN:
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lsl INC_X, INC_X, #2 // INC_X * SIZE
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lsl INC_Y, INC_Y, #2 // INC_Y * SIZE
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asrs I, N, #2 // I = N / 4
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ble sdot_kernel_S1
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sdot_kernel_S4:
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KERNEL_S4
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subs I, I, #1
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bne sdot_kernel_S4
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sdot_kernel_S1:
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ands I, N, #3
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ble sdot_kernel_L999
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sdot_kernel_S10:
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KERNEL_S1
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subs I, I, #1
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bne sdot_kernel_S10
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sdot_kernel_L999:
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sub r3, fp, #128
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vldm r3, { s8 - s15} // restore floating point registers
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#if defined(DSDOT)
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vadd.f64 d0 , d0, d1 // set return value
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#else
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vadd.f32 s0 , s0, s1 // set return value
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#endif
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sub sp, fp, #24
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pop {r4 - r9, fp}
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bx lr
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EPILOGUE
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