635 lines
11 KiB
ArmAsm
635 lines
11 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2013/11/29 Saar
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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*
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**************************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define STACKSIZE 256
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#if !defined(__ARM_PCS_VFP)
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#define OLD_ALPHAR [fp, #0 ]
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#define OLD_ALPHAI [fp, #8 ]
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#define OLD_A_SOFTFP [fp, #16]
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#define OLD_LDA [fp, #20]
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#define X [fp, #24]
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#define OLD_INC_X [fp, #28]
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#define Y [fp, #32]
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#define OLD_INC_Y [fp, #36]
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#else
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#define OLD_LDA [fp, #0 ]
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#define X [fp, #4 ]
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#define OLD_INC_X [fp, #8 ]
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#define Y [fp, #12 ]
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#define OLD_INC_Y [fp, #16 ]
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#endif
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#define OLD_A r3
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#define OLD_N r1
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#define M r0
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#define AO1 r1
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#define J r2
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#define AO2 r4
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#define XO r5
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#define YO r6
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#define LDA r7
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#define INC_X r8
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#define INC_Y r9
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#define I r12
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#define FP_ZERO [fp, #-228]
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#define FP_ZERO_0 [fp, #-228]
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#define FP_ZERO_1 [fp, #-224]
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#define N [fp, #-252 ]
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#define A [fp, #-256 ]
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#define X_PRE 512
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#define A_PRE 512
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#define Y_PRE 32
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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#if !defined(CONJ) && !defined(XCONJ)
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#define KMAC_R vmls.f64
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#define KMAC_I fmacd
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#define FMAC_R1 fmacd
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#define FMAC_R2 vmls.f64
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#define FMAC_I1 fmacd
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#define FMAC_I2 fmacd
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#elif defined(CONJ) && !defined(XCONJ)
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#define KMAC_R fmacd
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#define KMAC_I vmls.f64
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#define FMAC_R1 fmacd
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#define FMAC_R2 vmls.f64
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#define FMAC_I1 fmacd
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#define FMAC_I2 fmacd
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#elif !defined(CONJ) && defined(XCONJ)
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#define KMAC_R fmacd
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#define KMAC_I vmls.f64
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#define FMAC_R1 fmacd
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#define FMAC_R2 fmacd
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#define FMAC_I1 vmls.f64
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#define FMAC_I2 fmacd
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#else
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#define KMAC_R vmls.f64
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#define KMAC_I fmacd
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#define FMAC_R1 fmacd
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#define FMAC_R2 fmacd
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#define FMAC_I1 vmls.f64
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#define FMAC_I2 fmacd
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#endif
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.macro INIT_F2
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fldd d12, FP_ZERO
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vmov.f64 d13, d12
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vmov.f64 d14, d12
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vmov.f64 d15, d12
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.endm
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.macro KERNEL_F2X4
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KERNEL_F2X1
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KERNEL_F2X1
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KERNEL_F2X1
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KERNEL_F2X1
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.endm
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.macro KERNEL_F2X1
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vldmia.f64 XO! , { d2 - d3 }
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vldmia.f64 AO1!, { d4 - d5 }
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fmacd d12 , d4 , d2
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fmacd d13 , d4 , d3
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vldmia.f64 AO2!, { d8 - d9 }
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KMAC_R d12 , d5 , d3
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KMAC_I d13 , d5 , d2
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fmacd d14 , d8 , d2
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fmacd d15 , d8 , d3
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KMAC_R d14 , d9 , d3
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KMAC_I d15 , d9 , d2
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.endm
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.macro SAVE_F2
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vldmia.f64 YO, { d4 - d7 }
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FMAC_R1 d4 , d0 , d12
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FMAC_I1 d5 , d0 , d13
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FMAC_R2 d4 , d1 , d13
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FMAC_I2 d5 , d1 , d12
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FMAC_R1 d6 , d0 , d14
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FMAC_I1 d7 , d0 , d15
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FMAC_R2 d6 , d1 , d15
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FMAC_I2 d7 , d1 , d14
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vstmia.f64 YO!, { d4 - d7 }
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.endm
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/************************************************************************************************/
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.macro INIT_F1
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fldd d12, FP_ZERO
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vmov.f64 d13, d12
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.endm
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.macro KERNEL_F1X4
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KERNEL_F1X1
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KERNEL_F1X1
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KERNEL_F1X1
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KERNEL_F1X1
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.endm
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.macro KERNEL_F1X1
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vldmia.f64 XO! , { d2 - d3 }
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vldmia.f64 AO1!, { d4 - d5 }
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fmacd d12 , d4 , d2
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fmacd d13 , d4 , d3
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KMAC_R d12 , d5 , d3
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KMAC_I d13 , d5 , d2
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.endm
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.macro SAVE_F1
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d12
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FMAC_I1 d5 , d0 , d13
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FMAC_R2 d4 , d1 , d13
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FMAC_I2 d5 , d1 , d12
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vstmia.f64 YO!, { d4 - d5 }
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.endm
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/************************************************************************************************/
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.macro INIT_S2
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fldd d12, FP_ZERO
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vmov.f64 d13, d12
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vmov.f64 d14, d12
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vmov.f64 d15, d12
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.endm
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.macro KERNEL_S2X4
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KERNEL_S2X1
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KERNEL_S2X1
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KERNEL_S2X1
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KERNEL_S2X1
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.endm
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.macro KERNEL_S2X1
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vldmia.f64 XO , { d2 - d3 }
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vldmia.f64 AO1!, { d4 - d5 }
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vldmia.f64 AO2!, { d8 - d9 }
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fmacd d12 , d4 , d2
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fmacd d13 , d4 , d3
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KMAC_R d12 , d5 , d3
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KMAC_I d13 , d5 , d2
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fmacd d14 , d8 , d2
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fmacd d15 , d8 , d3
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KMAC_R d14 , d9 , d3
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KMAC_I d15 , d9 , d2
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add XO, XO, INC_X
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.endm
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.macro SAVE_S2
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d12
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FMAC_I1 d5 , d0 , d13
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FMAC_R2 d4 , d1 , d13
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FMAC_I2 d5 , d1 , d12
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vstmia.f64 YO, { d4 - d5 }
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add YO, YO, INC_Y
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vldmia.f64 YO, { d6 - d7 }
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FMAC_R1 d6 , d0 , d14
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FMAC_I1 d7 , d0 , d15
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FMAC_R2 d6 , d1 , d15
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FMAC_I2 d7 , d1 , d14
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vstmia.f64 YO, { d6 - d7 }
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add YO, YO, INC_Y
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.endm
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/************************************************************************************************/
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.macro INIT_S1
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fldd d12, FP_ZERO
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vmov.f64 d13, d12
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.endm
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.macro KERNEL_S1X4
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KERNEL_S1X1
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KERNEL_S1X1
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KERNEL_S1X1
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KERNEL_S1X1
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.endm
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.macro KERNEL_S1X1
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vldmia.f64 XO , { d2 - d3 }
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vldmia.f64 AO1!, { d4 - d5 }
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fmacd d12 , d4 , d2
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fmacd d13 , d4 , d3
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KMAC_R d12 , d5 , d3
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KMAC_I d13 , d5 , d2
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add XO, XO, INC_X
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.endm
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.macro SAVE_S1
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vldmia.f64 YO, { d4 - d5 }
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FMAC_R1 d4 , d0 , d12
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FMAC_I1 d5 , d0 , d13
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FMAC_R2 d4 , d1 , d13
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FMAC_I2 d5 , d1 , d12
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vstmia.f64 YO, { d4 - d5 }
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add YO, YO, INC_Y
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.endm
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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push {r4 - r9 , fp}
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add fp, sp, #28
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sub sp, sp, #STACKSIZE // reserve stack
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sub r12, fp, #192
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#if defined(DOUBLE)
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vstm r12, { d8 - d15 } // store floating point registers
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#else
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vstm r12, { s8 - s15 } // store floating point registers
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#endif
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movs r12, #0
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str r12, FP_ZERO
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str r12, FP_ZERO_1
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cmp M, #0
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ble zgemvt_kernel_L999
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cmp OLD_N, #0
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ble zgemvt_kernel_L999
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#if !defined(__ARM_PCS_VFP)
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vldr d0, OLD_ALPHAR
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vldr d1, OLD_ALPHAI
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ldr OLD_A, OLD_A_SOFTFP
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#endif
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str OLD_A, A
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str OLD_N, N
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ldr INC_X , OLD_INC_X
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ldr INC_Y , OLD_INC_Y
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cmp INC_X, #0
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beq zgemvt_kernel_L999
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cmp INC_Y, #0
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beq zgemvt_kernel_L999
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ldr LDA, OLD_LDA
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#if defined(DOUBLE)
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lsl LDA, LDA, #4 // LDA * SIZE
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#else
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lsl LDA, LDA, #3 // LDA * SIZE
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#endif
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cmp INC_X, #1
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bne zgemvt_kernel_S2_BEGIN
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cmp INC_Y, #1
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bne zgemvt_kernel_S2_BEGIN
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zgemvt_kernel_F2_BEGIN:
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ldr YO , Y
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ldr J, N
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asrs J, J, #1 // J = N / 2
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ble zgemvt_kernel_F1_BEGIN
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zgemvt_kernel_F2X4:
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ldr AO1, A
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add AO2, AO1, LDA
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add r3 , AO2, LDA
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str r3 , A
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ldr XO , X
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INIT_F2
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asrs I, M, #2 // I = M / 4
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ble zgemvt_kernel_F2X1
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zgemvt_kernel_F2X4_10:
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KERNEL_F2X4
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subs I, I, #1
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bne zgemvt_kernel_F2X4_10
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zgemvt_kernel_F2X1:
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ands I, M , #3
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ble zgemvt_kernel_F2_END
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zgemvt_kernel_F2X1_10:
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KERNEL_F2X1
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subs I, I, #1
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bne zgemvt_kernel_F2X1_10
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zgemvt_kernel_F2_END:
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SAVE_F2
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subs J , J , #1
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bne zgemvt_kernel_F2X4
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zgemvt_kernel_F1_BEGIN:
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ldr J, N
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ands J, J, #1
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ble zgemvt_kernel_L999
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zgemvt_kernel_F1X4:
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ldr AO1, A
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ldr XO , X
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INIT_F1
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asrs I, M, #2 // I = M / 4
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ble zgemvt_kernel_F1X1
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zgemvt_kernel_F1X4_10:
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KERNEL_F1X4
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subs I, I, #1
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bne zgemvt_kernel_F1X4_10
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zgemvt_kernel_F1X1:
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ands I, M , #3
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ble zgemvt_kernel_F1_END
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zgemvt_kernel_F1X1_10:
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KERNEL_F1X1
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subs I, I, #1
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bne zgemvt_kernel_F1X1_10
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zgemvt_kernel_F1_END:
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SAVE_F1
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b zgemvt_kernel_L999
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/*************************************************************************************************************/
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zgemvt_kernel_S2_BEGIN:
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#if defined(DOUBLE)
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lsl INC_X, INC_X, #4 // INC_X * SIZE
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lsl INC_Y, INC_Y, #4 // INC_Y * SIZE
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#else
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lsl INC_X, INC_X, #3 // INC_X * SIZE
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lsl INC_Y, INC_Y, #3 // INC_Y * SIZE
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#endif
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ldr YO , Y
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ldr J, N
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asrs J, J, #1 // J = N / 2
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ble zgemvt_kernel_S1_BEGIN
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zgemvt_kernel_S2X4:
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ldr AO1, A
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add AO2, AO1, LDA
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add r3 , AO2, LDA
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str r3 , A
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ldr XO , X
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INIT_S2
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asrs I, M, #2 // I = M / 4
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ble zgemvt_kernel_S2X1
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zgemvt_kernel_S2X4_10:
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KERNEL_S2X4
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subs I, I, #1
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bne zgemvt_kernel_S2X4_10
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zgemvt_kernel_S2X1:
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ands I, M , #3
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ble zgemvt_kernel_S2_END
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zgemvt_kernel_S2X1_10:
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KERNEL_S2X1
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subs I, I, #1
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bne zgemvt_kernel_S2X1_10
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zgemvt_kernel_S2_END:
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SAVE_S2
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subs J , J , #1
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bne zgemvt_kernel_S2X4
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zgemvt_kernel_S1_BEGIN:
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ldr J, N
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ands J, J, #1
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ble zgemvt_kernel_L999
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zgemvt_kernel_S1X4:
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ldr AO1, A
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ldr XO , X
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INIT_S1
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asrs I, M, #2 // I = M / 4
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ble zgemvt_kernel_S1X1
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zgemvt_kernel_S1X4_10:
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KERNEL_S1X4
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subs I, I, #1
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bne zgemvt_kernel_S1X4_10
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zgemvt_kernel_S1X1:
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ands I, M , #3
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ble zgemvt_kernel_S1_END
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zgemvt_kernel_S1X1_10:
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KERNEL_S1X1
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subs I, I, #1
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bne zgemvt_kernel_S1X1_10
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zgemvt_kernel_S1_END:
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SAVE_S1
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/*************************************************************************************************************/
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zgemvt_kernel_L999:
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sub r3, fp, #192
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#if defined(DOUBLE)
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vldm r3, { d8 - d15 } // restore floating point registers
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#else
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vldm r3, { s8 - s15 } // restore floating point registers
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#endif
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mov r0, #0 // set return value
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sub sp, fp, #28
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pop {r4 -r9 ,fp}
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bx lr
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EPILOGUE
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