807 lines
12 KiB
ArmAsm
807 lines
12 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2013, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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/**************************************************************************************
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* 2013/11/27 Saar
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* BLASTEST : OK
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* CTEST : OK
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* TEST : OK
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*
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**************************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define STACKSIZE 256
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#define OLD_M r0
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#define OLD_N r1
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#define OLD_K r2
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#define OLD_A r3
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#define OLD_ALPHA d0
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/******************************************************
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* [fp, #-128] - [fp, #-64] is reserved
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* for store and restore of floating point
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* registers
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*******************************************************/
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#define LDC [fp, #-252 ]
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#define M [fp, #-256 ]
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#define N [fp, #-260 ]
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#define K [fp, #-264 ]
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#define A [fp, #-268 ]
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#define ALPHA [fp, #-280]
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#define B [fp, #4 ]
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#define C [fp, #8 ]
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#define OLD_LDC [fp, #12 ]
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#define I r0
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#define J r1
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#define L r2
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#define AO r5
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#define BO r6
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#define CO1 r8
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#define CO2 r9
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#define K1 r7
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#define BC r12
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#define A_PRE 96
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#define B_PRE 96
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#define C_PRE 32
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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.macro INIT4x2
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vsub.f64 d8 , d8 , d8
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vmov.f64 d9, d8
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vmov.f64 d10, d8
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vmov.f64 d11, d8
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vmov.f64 d12, d8
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vmov.f64 d13, d8
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vmov.f64 d14, d8
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vmov.f64 d15, d8
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.endm
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.macro KERNEL4x2_SUB
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pld [ AO, #A_PRE ]
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fldd d4 , [ BO ]
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fldd d0 , [ AO ]
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fldd d1 , [ AO, #8 ]
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fmacd d8 , d0, d4
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fldd d2 , [ AO, #16 ]
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fmacd d9 , d1, d4
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fldd d3 , [ AO, #24 ]
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fmacd d10 , d2, d4
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fldd d5 , [ BO, #8 ]
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fmacd d11 , d3, d4
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fmacd d12 , d0, d5
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fmacd d13 , d1, d5
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add AO , AO, #32
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fmacd d14 , d2, d5
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add BO , BO, #16
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fmacd d15 , d3, d5
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.endm
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.macro SAVE4x2
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ldr r3 , LDC
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add CO2 , CO1, r3
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fldd d0, ALPHA
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fldd d4 , [CO1]
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fldd d5 , [CO1, #8 ]
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pld [ CO1, #C_PRE ]
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fmacd d4 , d0 , d8
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fldd d6 , [CO1, #16 ]
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fmacd d5 , d0 , d9
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fldd d7 , [CO1, #24 ]
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fmacd d6 , d0 , d10
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fstd d4 , [CO1]
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fmacd d7 , d0 , d11
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fstd d5 , [CO1, #8 ]
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fstd d6 , [CO1, #16 ]
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fstd d7 , [CO1, #24 ]
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fldd d4 , [CO2]
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fldd d5 , [CO2, #8 ]
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pld [ CO2, #C_PRE ]
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fmacd d4 , d0 , d12
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fldd d6 , [CO2, #16 ]
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fmacd d5 , d0 , d13
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fldd d7 , [CO2, #24 ]
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fmacd d6 , d0 , d14
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fstd d4 , [CO2]
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fmacd d7 , d0 , d15
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add CO1, CO1, #32
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fstd d5 , [CO2, #8 ]
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fstd d6 , [CO2, #16 ]
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fstd d7 , [CO2, #24 ]
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.endm
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/******************************************************************************/
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.macro INIT2x2
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vsub.f64 d8 , d8 , d8
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vmov.f64 d9, d8
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vmov.f64 d12, d8
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vmov.f64 d13, d8
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.endm
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.macro KERNEL2x2_SUB
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fldd d4 , [ BO ]
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fldd d5 , [ BO, #8 ]
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fldd d0 , [ AO ]
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fldd d1 , [ AO, #8 ]
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fmacd d8 , d0, d4
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fmacd d9 , d1, d4
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fmacd d12 , d0, d5
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fmacd d13 , d1, d5
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add AO , AO, #16
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add BO , BO, #16
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.endm
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.macro SAVE2x2
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ldr r3 , LDC
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add CO2 , CO1, r3
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fldd d0, ALPHA
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fldd d4 , [CO1]
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fldd d5 , [CO1, #8 ]
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fmacd d4 , d0 , d8
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fmacd d5 , d0 , d9
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fstd d4 , [CO1]
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fstd d5 , [CO1, #8 ]
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fldd d4 , [CO2]
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fldd d5 , [CO2, #8 ]
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fmacd d4 , d0 , d12
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fmacd d5 , d0 , d13
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fstd d4 , [CO2]
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fstd d5 , [CO2, #8 ]
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add CO1, CO1, #16
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.endm
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/******************************************************************************/
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.macro INIT1x2
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vsub.f64 d8 , d8 , d8
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vmov.f64 d12, d8
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.endm
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.macro KERNEL1x2_SUB
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fldd d4 , [ BO ]
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fldd d5 , [ BO, #8 ]
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fldd d0 , [ AO ]
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fmacd d8 , d0, d4
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fmacd d12 , d0, d5
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add AO , AO, #8
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add BO , BO, #16
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.endm
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.macro SAVE1x2
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ldr r3 , LDC
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add CO2 , CO1, r3
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fldd d0, ALPHA
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fldd d4 , [CO1]
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fmacd d4 , d0 , d8
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fstd d4 , [CO1]
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fldd d4 , [CO2]
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fmacd d4 , d0 , d12
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fstd d4 , [CO2]
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add CO1, CO1, #8
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.endm
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/******************************************************************************/
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.macro INIT4x1
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vsub.f64 d8 , d8 , d8
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vmov.f64 d9, d8
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vmov.f64 d10, d8
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vmov.f64 d11, d8
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.endm
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.macro KERNEL4x1_SUB
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fldd d4 , [ BO ]
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fldd d0 , [ AO ]
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fldd d1 , [ AO, #8 ]
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fldd d2 , [ AO, #16 ]
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fldd d3 , [ AO, #24 ]
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fmacd d8 , d0, d4
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fmacd d9 , d1, d4
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fmacd d10 , d2, d4
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fmacd d11 , d3, d4
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add AO , AO, #32
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add BO , BO, #8
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.endm
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.macro SAVE4x1
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fldd d0, ALPHA
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fldd d4 , [CO1]
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fldd d5 , [CO1, #8 ]
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fldd d6 , [CO1, #16 ]
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fldd d7 , [CO1, #24 ]
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fmacd d4 , d0 , d8
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fmacd d5 , d0 , d9
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fmacd d6 , d0 , d10
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fmacd d7 , d0 , d11
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fstd d4 , [CO1]
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fstd d5 , [CO1, #8 ]
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fstd d6 , [CO1, #16 ]
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fstd d7 , [CO1, #24 ]
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add CO1, CO1, #32
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.endm
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/******************************************************************************/
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.macro INIT2x1
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vsub.f64 d8 , d8 , d8
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vmov.f64 d9 , d8
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.endm
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.macro KERNEL2x1_SUB
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fldd d4 , [ BO ]
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fldd d0 , [ AO ]
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fldd d1 , [ AO, #8 ]
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fmacd d8 , d0, d4
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fmacd d9 , d1, d4
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add AO , AO, #16
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add BO , BO, #8
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.endm
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.macro SAVE2x1
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fldd d0, ALPHA
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fldd d4 , [CO1]
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fldd d5 , [CO1, #8 ]
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fmacd d4 , d0 , d8
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fmacd d5 , d0 , d9
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fstd d4 , [CO1]
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fstd d5 , [CO1, #8 ]
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add CO1, CO1, #16
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.endm
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/******************************************************************************/
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.macro INIT1x1
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vsub.f64 d8 , d8 , d8
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.endm
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.macro KERNEL1x1_SUB
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fldd d4 , [ BO ]
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fldd d0 , [ AO ]
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fmacd d8 , d0, d4
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add AO , AO, #8
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add BO , BO, #8
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.endm
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.macro SAVE1x1
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fldd d0, ALPHA
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fldd d4 , [CO1]
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fmacd d4 , d0 , d8
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fstd d4 , [CO1]
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add CO1, CO1, #8
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.endm
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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push {r4 - r9, fp}
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add fp, sp, #24
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sub sp, sp, #STACKSIZE // reserve stack
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str OLD_M, M
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str OLD_N, N
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str OLD_K, K
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str OLD_A, A
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vstr OLD_ALPHA, ALPHA
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sub r3, fp, #128
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vstm r3, { d8 - d15} // store floating point registers
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ldr r3, OLD_LDC
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lsl r3, r3, #3 // ldc = ldc * 8
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str r3, LDC
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ldr K1, K
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ldr BC, B
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ldr J, N
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asrs J, J, #1 // J = J / 2
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ble dgemm_kernel_L1_BEGIN
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/*********************************************************************************************/
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dgemm_kernel_L2_BEGIN:
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ldr CO1, C // CO1 = C
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ldr r4 , LDC
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lsl r4 , r4 , #1 // LDC * 2
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add r3 , r4, CO1
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str r3 , C // store C
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ldr AO, A // AO = A
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dgemm_kernel_L2_M4_BEGIN:
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ldr I, M
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asrs I, I, #2 // I = I / 4
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ble dgemm_kernel_L2_M2_BEGIN
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dgemm_kernel_L2_M4_20:
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INIT4x2
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mov BO, BC
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asrs L , K1, #3 // L = L / 8
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ble dgemm_kernel_L2_M4_40
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.align 5
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dgemm_kernel_L2_M4_22:
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pld [ BO, #B_PRE ]
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KERNEL4x2_SUB
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KERNEL4x2_SUB
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pld [ BO, #B_PRE ]
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KERNEL4x2_SUB
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KERNEL4x2_SUB
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pld [ BO, #B_PRE ]
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KERNEL4x2_SUB
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KERNEL4x2_SUB
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pld [ BO, #B_PRE ]
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KERNEL4x2_SUB
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KERNEL4x2_SUB
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subs L, L, #1
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bgt dgemm_kernel_L2_M4_22
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dgemm_kernel_L2_M4_40:
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ands L , K1, #7 // L = L % 8
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ble dgemm_kernel_L2_M4_100
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dgemm_kernel_L2_M4_42:
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KERNEL4x2_SUB
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subs L, L, #1
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bgt dgemm_kernel_L2_M4_42
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dgemm_kernel_L2_M4_100:
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SAVE4x2
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dgemm_kernel_L2_M4_END:
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subs I, I, #1
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bgt dgemm_kernel_L2_M4_20
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dgemm_kernel_L2_M2_BEGIN:
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ldr I, M
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tst I , #3
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ble dgemm_kernel_L2_END
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tst I, #2 // I = I / 2
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ble dgemm_kernel_L2_M1_BEGIN
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dgemm_kernel_L2_M2_20:
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INIT2x2
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mov BO, BC
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asrs L , K1, #3 // L = L / 8
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ble dgemm_kernel_L2_M2_40
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dgemm_kernel_L2_M2_22:
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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KERNEL2x2_SUB
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subs L, L, #1
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bgt dgemm_kernel_L2_M2_22
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dgemm_kernel_L2_M2_40:
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ands L , K1, #7 // L = L % 8
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ble dgemm_kernel_L2_M2_100
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dgemm_kernel_L2_M2_42:
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KERNEL2x2_SUB
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subs L, L, #1
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bgt dgemm_kernel_L2_M2_42
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dgemm_kernel_L2_M2_100:
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SAVE2x2
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dgemm_kernel_L2_M2_END:
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dgemm_kernel_L2_M1_BEGIN:
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tst I, #1 // I = I % 2
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ble dgemm_kernel_L2_END
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dgemm_kernel_L2_M1_20:
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INIT1x2
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mov BO, BC
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asrs L , K1, #3 // L = L / 8
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ble dgemm_kernel_L2_M1_40
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dgemm_kernel_L2_M1_22:
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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KERNEL1x2_SUB
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subs L, L, #1
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bgt dgemm_kernel_L2_M1_22
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dgemm_kernel_L2_M1_40:
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ands L , K1, #7 // L = L % 8
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ble dgemm_kernel_L2_M1_100
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dgemm_kernel_L2_M1_42:
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KERNEL1x2_SUB
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subs L, L, #1
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bgt dgemm_kernel_L2_M1_42
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dgemm_kernel_L2_M1_100:
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SAVE1x2
|
|
|
|
|
|
dgemm_kernel_L2_END:
|
|
|
|
mov r3, BC
|
|
mov r4, K1
|
|
lsl r4, r4, #4 // k * 2 * 8
|
|
add r3, r3, r4 // B = B + K * 2 * 8
|
|
mov BC, r3
|
|
|
|
subs J , #1 // j--
|
|
bgt dgemm_kernel_L2_BEGIN
|
|
|
|
/*********************************************************************************************/
|
|
|
|
dgemm_kernel_L1_BEGIN:
|
|
|
|
ldr J , N
|
|
tst J , #1
|
|
ble dgemm_kernel_L999
|
|
|
|
|
|
ldr CO1, C // CO1 = C
|
|
ldr r4 , LDC
|
|
add r3 , r4, CO1
|
|
str r3 , C // store C
|
|
|
|
ldr AO, A // AO = A
|
|
|
|
|
|
|
|
dgemm_kernel_L1_M4_BEGIN:
|
|
|
|
ldr I, M
|
|
asrs I, I, #2 // I = I / 4
|
|
ble dgemm_kernel_L1_M2_BEGIN
|
|
|
|
dgemm_kernel_L1_M4_20:
|
|
|
|
INIT4x1
|
|
|
|
mov BO, BC
|
|
asrs L , K1, #3 // L = L / 8
|
|
ble dgemm_kernel_L1_M4_40
|
|
.align 5
|
|
|
|
dgemm_kernel_L1_M4_22:
|
|
KERNEL4x1_SUB
|
|
KERNEL4x1_SUB
|
|
KERNEL4x1_SUB
|
|
KERNEL4x1_SUB
|
|
|
|
KERNEL4x1_SUB
|
|
KERNEL4x1_SUB
|
|
KERNEL4x1_SUB
|
|
KERNEL4x1_SUB
|
|
|
|
subs L, L, #1
|
|
bgt dgemm_kernel_L1_M4_22
|
|
|
|
|
|
dgemm_kernel_L1_M4_40:
|
|
|
|
ands L , K1, #7 // L = L % 8
|
|
ble dgemm_kernel_L1_M4_100
|
|
|
|
dgemm_kernel_L1_M4_42:
|
|
|
|
KERNEL4x1_SUB
|
|
|
|
subs L, L, #1
|
|
bgt dgemm_kernel_L1_M4_42
|
|
|
|
dgemm_kernel_L1_M4_100:
|
|
|
|
SAVE4x1
|
|
|
|
dgemm_kernel_L1_M4_END:
|
|
|
|
subs I, I, #1
|
|
bgt dgemm_kernel_L1_M4_20
|
|
|
|
|
|
dgemm_kernel_L1_M2_BEGIN:
|
|
|
|
ldr I, M
|
|
tst I , #3
|
|
ble dgemm_kernel_L1_END
|
|
|
|
tst I, #2 // I = I / 2
|
|
ble dgemm_kernel_L1_M1_BEGIN
|
|
|
|
dgemm_kernel_L1_M2_20:
|
|
|
|
INIT2x1
|
|
|
|
mov BO, BC
|
|
asrs L , K1, #3 // L = L / 8
|
|
ble dgemm_kernel_L1_M2_40
|
|
|
|
dgemm_kernel_L1_M2_22:
|
|
|
|
KERNEL2x1_SUB
|
|
KERNEL2x1_SUB
|
|
KERNEL2x1_SUB
|
|
KERNEL2x1_SUB
|
|
|
|
KERNEL2x1_SUB
|
|
KERNEL2x1_SUB
|
|
KERNEL2x1_SUB
|
|
KERNEL2x1_SUB
|
|
|
|
subs L, L, #1
|
|
bgt dgemm_kernel_L1_M2_22
|
|
|
|
|
|
dgemm_kernel_L1_M2_40:
|
|
|
|
ands L , K1, #7 // L = L % 8
|
|
ble dgemm_kernel_L1_M2_100
|
|
|
|
dgemm_kernel_L1_M2_42:
|
|
|
|
KERNEL2x1_SUB
|
|
|
|
subs L, L, #1
|
|
bgt dgemm_kernel_L1_M2_42
|
|
|
|
dgemm_kernel_L1_M2_100:
|
|
|
|
SAVE2x1
|
|
|
|
dgemm_kernel_L1_M2_END:
|
|
|
|
|
|
dgemm_kernel_L1_M1_BEGIN:
|
|
|
|
tst I, #1 // I = I % 2
|
|
ble dgemm_kernel_L1_END
|
|
|
|
dgemm_kernel_L1_M1_20:
|
|
|
|
INIT1x1
|
|
|
|
mov BO, BC
|
|
asrs L , K1, #3 // L = L / 8
|
|
ble dgemm_kernel_L1_M1_40
|
|
|
|
dgemm_kernel_L1_M1_22:
|
|
KERNEL1x1_SUB
|
|
KERNEL1x1_SUB
|
|
KERNEL1x1_SUB
|
|
KERNEL1x1_SUB
|
|
|
|
KERNEL1x1_SUB
|
|
KERNEL1x1_SUB
|
|
KERNEL1x1_SUB
|
|
KERNEL1x1_SUB
|
|
|
|
subs L, L, #1
|
|
bgt dgemm_kernel_L1_M1_22
|
|
|
|
|
|
dgemm_kernel_L1_M1_40:
|
|
|
|
ands L , K1, #7 // L = L % 8
|
|
ble dgemm_kernel_L1_M1_100
|
|
|
|
dgemm_kernel_L1_M1_42:
|
|
|
|
KERNEL1x1_SUB
|
|
|
|
subs L, L, #1
|
|
bgt dgemm_kernel_L1_M1_42
|
|
|
|
dgemm_kernel_L1_M1_100:
|
|
|
|
SAVE1x1
|
|
|
|
|
|
dgemm_kernel_L1_END:
|
|
|
|
|
|
dgemm_kernel_L999:
|
|
|
|
sub r3, fp, #128
|
|
vldm r3, { d8 - d15} // restore floating point registers
|
|
|
|
movs r0, #0 // set return value
|
|
sub sp, fp, #24
|
|
pop {r4 - r9, fp}
|
|
bx lr
|
|
|
|
EPILOGUE
|
|
|