403 lines
7.9 KiB
ArmAsm
403 lines
7.9 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define M x0
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#define N x1
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#define A x2
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#define LDA x3
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#define B x4
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#define M4 x5
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#define A01 x6
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#define A02 x7
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#define A03 x8
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#define A04 x9
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#define B01 x10
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#define B02 x11
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#define B03 x12
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#define B04 x13
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#define I x14
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#define J x15
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#define TEMP1 x16
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#define TEMP2 x17
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#define A_PREFETCH 2560
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#define B_PREFETCH 256
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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.macro SAVE_REGS
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add sp, sp, #-(11 * 16)
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stp d8, d9, [sp, #(0 * 16)]
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stp d10, d11, [sp, #(1 * 16)]
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stp d12, d13, [sp, #(2 * 16)]
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stp d14, d15, [sp, #(3 * 16)]
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stp d16, d17, [sp, #(4 * 16)]
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stp x18, x19, [sp, #(5 * 16)]
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stp x20, x21, [sp, #(6 * 16)]
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stp x22, x23, [sp, #(7 * 16)]
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stp x24, x25, [sp, #(8 * 16)]
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stp x26, x27, [sp, #(9 * 16)]
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str x28, [sp, #(10 * 16)]
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.endm
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.macro RESTORE_REGS
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ldp d8, d9, [sp, #(0 * 16)]
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ldp d10, d11, [sp, #(1 * 16)]
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ldp d12, d13, [sp, #(2 * 16)]
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ldp d14, d15, [sp, #(3 * 16)]
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ldp d16, d17, [sp, #(4 * 16)]
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ldp x18, x19, [sp, #(5 * 16)]
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ldp x20, x21, [sp, #(6 * 16)]
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ldp x22, x23, [sp, #(7 * 16)]
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ldp x24, x25, [sp, #(8 * 16)]
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ldp x26, x27, [sp, #(9 * 16)]
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ldr x28, [sp, #(10 * 16)]
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add sp, sp, #(11*16)
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.endm
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.macro COPY4x4
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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ldp q0, q1, [A01], #32
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ldp q2, q3, [A02], #32
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////prfm PLDL1KEEP, [B01, #B_PREFETCH]
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st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [B01]
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add TEMP1, B01, #64
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ldp q4, q5, [A03], #32
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ldp q6, q7, [A04], #32
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////prfm PLDL1KEEP, [B01, #B_PREFETCH]
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st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [TEMP1]
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add B01, B01, M4
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.endm
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.macro COPY2x4
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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ldr q0, [A01], #16
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ldr q1, [A02], #16
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ldr q2, [A03], #16
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ldr q3, [A04], #16
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////prfm PLDL1KEEP, [B02, #B_PREFETCH]
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st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [B02]
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add B02, B02, #64
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.endm
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.macro COPY1x4
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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ldr d0, [A01], #8
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ldr d1, [A02], #8
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ldr d2, [A03], #8
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ldr d3, [A04], #8
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////prfm PLDL1KEEP, [B03, #B_PREFETCH]
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st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [B03]
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add B03, B03, #32
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.endm
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/*************************************************************************************************************************/
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.macro COPY4x2
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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ldp q0, q1, [A01], #32
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ldp q2, q3, [A02], #32
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////prfm PLDL1KEEP, [B01, #B_PREFETCH]
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st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [B01]
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add B01, B01, M4
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.endm
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.macro COPY2x2
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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ldr q0, [A01], #16
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ldr q1, [A02], #16
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////prfm PLDL1KEEP, [B02, #B_PREFETCH]
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stp q0, q1, [B02]
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add B02, B02, #32
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.endm
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.macro COPY1x2
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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ldr d0, [A01], #8
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ldr d1, [A02], #8
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////prfm PLDL1KEEP, [B03, #B_PREFETCH]
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stp d0, d1, [B03]
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add B03, B03, #16
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.endm
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/*************************************************************************************************************************/
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.macro COPY4x1
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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ldp q0, q1, [A01], #32
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////prfm PLDL1KEEP, [B01, #B_PREFETCH]
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stp q0, q1, [B01]
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add B01, B01, M4
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.endm
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.macro COPY2x1
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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ldr q0, [A01], #16
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////prfm PLDL1KEEP, [B02, #B_PREFETCH]
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str q0, [B02]
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add B02, B02, #16
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.endm
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.macro COPY1x1
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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ldr d0, [A01], #8
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////prfm PLDL1KEEP, [B03, #B_PREFETCH]
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str d0, [B03]
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add B03, B03, #8
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.endm
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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SAVE_REGS
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lsl LDA, LDA, #3 // LDA = LDA * SIZE
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lsl TEMP1, M, #3 // x12 = M * SIZE
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and B02 , N , #-4
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and B03 , N , #-2
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mul B02, B02, TEMP1
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mul B03, B03, TEMP1
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add B02 , B02, B
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add B03 , B03, B
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lsl M4, M, #5 // M4 = M * 4 * SIZE
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.Ldgemm_tcopy_L4_BEGIN:
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asr J, M, #2 // J = M / 4
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cmp J, #0
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ble .Ldgemm_tcopy_L2_BEGIN
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.align 5
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.Ldgemm_tcopy_L4_M4_BEGIN:
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mov A01, A
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add A02, A01, LDA
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add A03, A02, LDA
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add A04, A03, LDA
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add A, A04, LDA
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mov B01, B
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add B, B01, #128 // B = B + 16 * SIZE
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asr I, N, #2 // I = N / 4
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cmp I, #0
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ble .Ldgemm_tcopy_L4_M4_40
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.align 5
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.Ldgemm_tcopy_L4_M4_20:
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COPY4x4
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subs I , I , #1
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bne .Ldgemm_tcopy_L4_M4_20
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.Ldgemm_tcopy_L4_M4_40:
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tst N , #2
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ble .Ldgemm_tcopy_L4_M4_60
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COPY2x4
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.Ldgemm_tcopy_L4_M4_60:
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tst N, #1
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ble .Ldgemm_tcopy_L4_M4_END
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COPY1x4
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.Ldgemm_tcopy_L4_M4_END:
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subs J , J, #1 // j--
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bne .Ldgemm_tcopy_L4_M4_BEGIN
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/*********************************************************************************************/
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.Ldgemm_tcopy_L2_BEGIN:
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tst M, #3
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ble .Ldgemm_tcopy_L999
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tst M, #2
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ble .Ldgemm_tcopy_L1_BEGIN
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.Ldgemm_tcopy_L2_M4_BEGIN:
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mov A01, A
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add A02, A01, LDA
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add A, A02, LDA
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mov B01, B
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add B, B01, #64 // B = B + 8 * SIZE
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asr I, N, #2 // I = N / 4
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cmp I, #0
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ble .Ldgemm_tcopy_L2_M4_40
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.align 5
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.Ldgemm_tcopy_L2_M4_20:
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COPY4x2
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subs I , I , #1
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bne .Ldgemm_tcopy_L2_M4_20
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.Ldgemm_tcopy_L2_M4_40:
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tst N , #2
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ble .Ldgemm_tcopy_L2_M4_60
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COPY2x2
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.Ldgemm_tcopy_L2_M4_60:
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tst N , #1
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ble .Ldgemm_tcopy_L2_M4_END
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COPY1x2
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.Ldgemm_tcopy_L2_M4_END:
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/*********************************************************************************************/
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.Ldgemm_tcopy_L1_BEGIN:
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tst M, #1
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ble .Ldgemm_tcopy_L999
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.Ldgemm_tcopy_L1_M4_BEGIN:
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mov A01, A // A01 = A
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mov B01, B
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asr I, N, #2 // I = M / 4
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cmp I, #0
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ble .Ldgemm_tcopy_L1_M4_40
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.align 5
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.Ldgemm_tcopy_L1_M4_20:
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COPY4x1
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subs I , I , #1
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bne .Ldgemm_tcopy_L1_M4_20
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.Ldgemm_tcopy_L1_M4_40:
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tst N , #2
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ble .Ldgemm_tcopy_L1_M4_60
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COPY2x1
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.Ldgemm_tcopy_L1_M4_60:
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tst N , #1
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ble .Ldgemm_tcopy_L1_M4_END
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COPY1x1
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.Ldgemm_tcopy_L1_M4_END:
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.Ldgemm_tcopy_L999:
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mov x0, #0 // set return value
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RESTORE_REGS
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ret
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EPILOGUE
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