545 lines
11 KiB
ArmAsm
545 lines
11 KiB
ArmAsm
/***************************************************************************
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Copyright (c) 2016, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A00 PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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#define M x0
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#define N x1
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#define A00 x2
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#define LDA x3
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#define B00 x4
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#define A01 x5
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#define A02 x6
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#define A03 x7
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#define A04 x8
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#define A05 x9
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#define A06 x10
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#define A07 x11
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#define A08 x12
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#define I x13
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#define J x14
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#define TEMP1 x15
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#define TEMP2 x16
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#define A_PREFETCH 2560
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/**************************************************************************************
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* Macro definitions
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**************************************************************************************/
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.macro SAVE_REGS
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add sp, sp, #-(11 * 16)
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stp d8, d9, [sp, #(0 * 16)]
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stp d10, d11, [sp, #(1 * 16)]
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stp d12, d13, [sp, #(2 * 16)]
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stp d14, d15, [sp, #(3 * 16)]
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stp d16, d17, [sp, #(4 * 16)]
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stp x18, x19, [sp, #(5 * 16)]
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stp x20, x21, [sp, #(6 * 16)]
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stp x22, x23, [sp, #(7 * 16)]
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stp x24, x25, [sp, #(8 * 16)]
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stp x26, x27, [sp, #(9 * 16)]
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str x28, [sp, #(10 * 16)]
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.endm
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.macro RESTORE_REGS
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ldp d8, d9, [sp, #(0 * 16)]
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ldp d10, d11, [sp, #(1 * 16)]
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ldp d12, d13, [sp, #(2 * 16)]
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ldp d14, d15, [sp, #(3 * 16)]
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ldp d16, d17, [sp, #(4 * 16)]
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ldp x18, x19, [sp, #(5 * 16)]
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ldp x20, x21, [sp, #(6 * 16)]
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ldp x22, x23, [sp, #(7 * 16)]
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ldp x24, x25, [sp, #(8 * 16)]
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ldp x26, x27, [sp, #(9 * 16)]
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ldr x28, [sp, #(10 * 16)]
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add sp, sp, #(11*16)
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.endm
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/*************************************************************************************/
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.macro COPY8x8
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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//prfm PLDL1KEEP, [A05, #A_PREFETCH]
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//prfm PLDL1KEEP, [A06, #A_PREFETCH]
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//prfm PLDL1KEEP, [A07, #A_PREFETCH]
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//prfm PLDL1KEEP, [A08, #A_PREFETCH]
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COPY4x8
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COPY4x8
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.endm
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.macro COPY4x8
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ldp q0, q1, [A01], #32
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ins v16.d[0], v0.d[0]
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ins v20.d[0], v0.d[1]
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ins v24.d[0], v1.d[0]
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ins v28.d[0], v1.d[1]
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ldp q2, q3, [A02], #32
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ins v16.d[1], v2.d[0]
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ins v20.d[1], v2.d[1]
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ins v24.d[1], v3.d[0]
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ins v28.d[1], v3.d[1]
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ldp q4, q5, [A03], #32
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ins v17.d[0], v4.d[0]
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ins v21.d[0], v4.d[1]
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ins v25.d[0], v5.d[0]
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ins v29.d[0], v5.d[1]
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ldp q6, q7, [A04], #32
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ins v17.d[1], v6.d[0]
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ins v21.d[1], v6.d[1]
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ins v25.d[1], v7.d[0]
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ins v29.d[1], v7.d[1]
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ldp q8, q9, [A05], #32
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ins v18.d[0], v8.d[0]
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ins v22.d[0], v8.d[1]
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ins v26.d[0], v9.d[0]
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ins v30.d[0], v9.d[1]
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ldp q10, q11, [A06], #32
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ins v18.d[1], v10.d[0]
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ins v22.d[1], v10.d[1]
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ins v26.d[1], v11.d[0]
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ins v30.d[1], v11.d[1]
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ldp q12, q13, [A07], #32
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ins v19.d[0], v12.d[0]
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ins v23.d[0], v12.d[1]
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ins v27.d[0], v13.d[0]
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ins v31.d[0], v13.d[1]
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ldp q14, q15, [A08], #32
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ins v19.d[1], v14.d[0]
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ins v23.d[1], v14.d[1]
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ins v27.d[1], v15.d[0]
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ins v31.d[1], v15.d[1]
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st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [B00]
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add B00, B00, #64
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st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [B00]
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add B00, B00, #64
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st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [B00]
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add B00, B00, #64
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st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [B00]
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add B00, B00, #64
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.endm
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.macro COPY1x8
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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//prfm PLDL1KEEP, [A05, #A_PREFETCH]
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//prfm PLDL1KEEP, [A06, #A_PREFETCH]
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//prfm PLDL1KEEP, [A07, #A_PREFETCH]
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//prfm PLDL1KEEP, [A08, #A_PREFETCH]
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ldr d0, [A01], #8
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ldr d1, [A02], #8
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ldr d2, [A03], #8
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ldr d3, [A04], #8
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ldr d4, [A05], #8
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ldr d5, [A06], #8
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ldr d6, [A07], #8
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ldr d7, [A08], #8
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st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [B00]
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add B00, B00, #32
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st1 {v4.1d, v5.1d, v6.1d, v7.1d}, [B00]
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add B00, B00, #32
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.endm
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/*************************************************************************************/
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.macro COPY8x4
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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ldp q0, q1, [A01], #32
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ins v8.d[0], v0.d[0]
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ins v10.d[0], v0.d[1]
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ins v12.d[0], v1.d[0]
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ins v14.d[0], v1.d[1]
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ldp q2, q3, [A02], #32
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ins v8.d[1], v2.d[0]
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ins v10.d[1], v2.d[1]
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ins v12.d[1], v3.d[0]
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ins v14.d[1], v3.d[1]
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ldp q4, q5, [A03], #32
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ins v9.d[0], v4.d[0]
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ins v11.d[0], v4.d[1]
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ins v13.d[0], v5.d[0]
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ins v15.d[0], v5.d[1]
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ldp q6, q7, [A04], #32
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ins v9.d[1], v6.d[0]
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ins v11.d[1], v6.d[1]
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ins v13.d[1], v7.d[0]
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ins v15.d[1], v7.d[1]
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st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [B00]
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add B00, B00, #64
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st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [B00]
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add B00, B00, #64
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ldp q16, q17, [A01], #32
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ins v24.d[0], v16.d[0]
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ins v26.d[0], v16.d[1]
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ins v28.d[0], v17.d[0]
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ins v30.d[0], v17.d[1]
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ldp q18, q19, [A02], #32
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ins v24.d[1], v18.d[0]
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ins v26.d[1], v18.d[1]
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ins v28.d[1], v19.d[0]
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ins v30.d[1], v19.d[1]
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ldp q20, q21, [A03], #32
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ins v25.d[0], v20.d[0]
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ins v27.d[0], v20.d[1]
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ins v29.d[0], v21.d[0]
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ins v31.d[0], v21.d[1]
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ldp q22, q23, [A04], #32
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ins v25.d[1], v22.d[0]
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ins v27.d[1], v22.d[1]
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ins v29.d[1], v23.d[0]
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ins v31.d[1], v23.d[1]
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st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [B00]
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add B00, B00, #64
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st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [B00]
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add B00, B00, #64
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.endm
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.macro COPY1x4
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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//prfm PLDL1KEEP, [A03, #A_PREFETCH]
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//prfm PLDL1KEEP, [A04, #A_PREFETCH]
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ldr d0, [A01], #8
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ldr d1, [A02], #8
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ldr d2, [A03], #8
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ldr d3, [A04], #8
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st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [B00]
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add B00, B00, #32
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.endm
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/*************************************************************************************/
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.macro COPY8x2
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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ldp q0, q1, [A01], #32
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ldp q2, q3, [A01], #32
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ins v8.d[0], v0.d[0]
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ins v9.d[0], v0.d[1]
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ins v10.d[0], v1.d[0]
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ins v11.d[0], v1.d[1]
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ins v12.d[0], v2.d[0]
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ins v13.d[0], v2.d[1]
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ins v14.d[0], v3.d[0]
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ins v15.d[0], v3.d[1]
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ldp q4, q5, [A02], #32
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ldp q6, q7, [A02], #32
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ins v8.d[1], v4.d[0]
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ins v9.d[1], v4.d[1]
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ins v10.d[1], v5.d[0]
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ins v11.d[1], v5.d[1]
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ins v12.d[1], v6.d[0]
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ins v13.d[1], v6.d[1]
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ins v14.d[1], v7.d[0]
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ins v15.d[1], v7.d[1]
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st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [B00]
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add B00, B00, #64
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st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [B00]
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add B00, B00, #64
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.endm
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.macro COPY1x2
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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//prfm PLDL1KEEP, [A02, #A_PREFETCH]
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ldr d0, [A01], #8
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ldr d1, [A02], #8
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stp d0, d1, [B00]
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add B00, B00, #16
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.endm
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/*************************************************************************************/
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.macro COPY8x1
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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ldp q0, q1, [A01], #32
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ldp q2, q3, [A01], #32
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stp q0, q1, [B00], #32
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stp q2, q3, [B00], #32
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.endm
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.macro COPY1x1
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//prfm PLDL1KEEP, [A01, #A_PREFETCH]
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ldr d0, [A01], #8
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str d0, [B00], #8
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.endm
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/**************************************************************************************
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* End of macro definitions
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**************************************************************************************/
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PROLOGUE
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.align 5
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SAVE_REGS
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lsl LDA, LDA, #3 // LDA = LDA * SIZE
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.Ldgemm_ncopy_L8_BEGIN:
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asr J, N, #3 // J = N / 8
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cmp J, #0
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ble .Ldgemm_ncopy_L4_BEGIN
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.Ldgemm_ncopy_L8_M8_BEGIN:
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mov A01, A00
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add A02, A01, LDA
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add A03, A02, LDA
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add A04, A03, LDA
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add A05, A04, LDA
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add A06, A05, LDA
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add A07, A06, LDA
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add A08, A07, LDA
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add A00, A08, LDA
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asr I, M, #3 // I = M / 8
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cmp I, #0
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ble .Ldgemm_ncopy_L8_M8_40
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.Ldgemm_ncopy_L8_M8_20:
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COPY8x8
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subs I , I , #1
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bne .Ldgemm_ncopy_L8_M8_20
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.Ldgemm_ncopy_L8_M8_40:
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and I, M , #7
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cmp I, #0
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ble .Ldgemm_ncopy_L8_M8_END
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.Ldgemm_ncopy_L8_M8_60:
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COPY1x8
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subs I , I , #1
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bne .Ldgemm_ncopy_L8_M8_60
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.Ldgemm_ncopy_L8_M8_END:
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subs J , J, #1 // j--
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bne .Ldgemm_ncopy_L8_M8_BEGIN
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/*********************************************************************************************/
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.Ldgemm_ncopy_L4_BEGIN:
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tst N, #7
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ble .Ldgemm_ncopy_L999
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tst N, #4
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ble .Ldgemm_ncopy_L2_BEGIN
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.Ldgemm_ncopy_L4_M8_BEGIN:
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mov A01, A00
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add A02, A01, LDA
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add A03, A02, LDA
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add A04, A03, LDA
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add A00, A04, LDA
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asr I, M, #3 // I = M / 8
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cmp I, #0
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ble .Ldgemm_ncopy_L4_M8_40
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.Ldgemm_ncopy_L4_M8_20:
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COPY8x4
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subs I , I , #1
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bne .Ldgemm_ncopy_L4_M8_20
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.Ldgemm_ncopy_L4_M8_40:
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and I, M , #7
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cmp I, #0
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ble .Ldgemm_ncopy_L4_M8_END
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.Ldgemm_ncopy_L4_M8_60:
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COPY1x4
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subs I , I , #1
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bne .Ldgemm_ncopy_L4_M8_60
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.Ldgemm_ncopy_L4_M8_END:
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/*********************************************************************************************/
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.Ldgemm_ncopy_L2_BEGIN:
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tst N, #3
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ble .Ldgemm_ncopy_L999
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tst N, #2
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ble .Ldgemm_ncopy_L1_BEGIN
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.Ldgemm_ncopy_L2_M8_BEGIN:
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mov A01, A00
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add A02, A01, LDA
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add A00, A02, LDA
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asr I, M, #3 // I = M / 8
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cmp I, #0
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ble .Ldgemm_ncopy_L2_M8_40
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.Ldgemm_ncopy_L2_M8_20:
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|
|
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COPY8x2
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|
|
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subs I , I , #1
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|
bne .Ldgemm_ncopy_L2_M8_20
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|
|
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.Ldgemm_ncopy_L2_M8_40:
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|
|
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and I, M , #7
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|
cmp I, #0
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|
ble .Ldgemm_ncopy_L2_M8_END
|
|
|
|
.Ldgemm_ncopy_L2_M8_60:
|
|
|
|
COPY1x2
|
|
|
|
subs I , I , #1
|
|
bne .Ldgemm_ncopy_L2_M8_60
|
|
|
|
|
|
.Ldgemm_ncopy_L2_M8_END:
|
|
|
|
|
|
/*********************************************************************************************/
|
|
|
|
.Ldgemm_ncopy_L1_BEGIN:
|
|
|
|
tst N, #1
|
|
ble .Ldgemm_ncopy_L999
|
|
|
|
|
|
.Ldgemm_ncopy_L1_M8_BEGIN:
|
|
|
|
mov A01, A00
|
|
|
|
asr I, M, #3 // I = M / 8
|
|
cmp I, #0
|
|
ble .Ldgemm_ncopy_L1_M8_40
|
|
|
|
.Ldgemm_ncopy_L1_M8_20:
|
|
|
|
COPY8x1
|
|
|
|
subs I , I , #1
|
|
bne .Ldgemm_ncopy_L1_M8_20
|
|
|
|
|
|
.Ldgemm_ncopy_L1_M8_40:
|
|
|
|
and I, M , #7
|
|
cmp I, #0
|
|
ble .Ldgemm_ncopy_L1_M8_END
|
|
|
|
.Ldgemm_ncopy_L1_M8_60:
|
|
|
|
COPY1x1
|
|
|
|
subs I , I , #1
|
|
bne .Ldgemm_ncopy_L1_M8_60
|
|
|
|
|
|
.Ldgemm_ncopy_L1_M8_END:
|
|
|
|
.Ldgemm_ncopy_L999:
|
|
|
|
mov x0, #0
|
|
RESTORE_REGS
|
|
ret
|
|
|
|
EPILOGUE
|
|
|