836 lines
19 KiB
ArmAsm
836 lines
19 KiB
ArmAsm
/*******************************************************************************
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Copyright (c) 2015, The OpenBLAS Project
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the OpenBLAS project nor the names of
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its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE OPENBLAS PROJECT OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#define ASSEMBLER
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#include "common.h"
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/* X0 X1 X2 s0 X3 x4 x5 x6 */
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/*int CNAME(BLASLONG bm,BLASLONG bn,BLASLONG bk,FLOAT alpha0,FLOAT* ba,FLOAT* bb,FLOAT* C,BLASLONG ldc */
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#define origM x0
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#define origN x1
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#define origK x2
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#define origPA x3
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#define origPB x4
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#define pC x5
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#define LDC x6
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#define temp x7
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#define counterL x8
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#define counterI x9
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#define counterJ x10
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#define pB x11
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#define pCRow0 x12
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#define pCRow1 x13
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#define pCRow2 x14
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#define pCRow3 x15
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#define pA x16
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#define lanes x17
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#define alphaR w19
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#define alphaI w20
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#define alphaz_R z6.s
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#define alphaz_I z7.s
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#define alpha0_R s4
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#define alpha0_I s5
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#define A_PRE_SIZE 2560
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#define B_PRE_SIZE 448
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#define C_PRE_SIZE 128
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#if defined(NN) || defined(NT) || defined(TN) || defined(TT)
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#define OP_rr fmla
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#define OP_ii fmls
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#define OP_ri fmla
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#define OP_ir fmla
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#elif defined(NR) || defined(NC) || defined(TR) || defined(TC)
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#define OP_rr fmla
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#define OP_ii fmla
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#define OP_ri fmls
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#define OP_ir fmla
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#elif defined(RN) || defined(RT) || defined(CN) || defined(CT)
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#define OP_rr fmla
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#define OP_ii fmla
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#define OP_ri fmla
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#define OP_ir fmls
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#elif defined(RR) || defined(RC) || defined(CR) || defined(CC)
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#define OP_rr fmla
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#define OP_ii fmls
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#define OP_ri fmls
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#define OP_ir fmls
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#endif
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// 00 origM
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// 01 origN
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// 02 origK
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// 03 origPA
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// 04 origPB
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// 05 pC
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// 06 origLDC -> LDC
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// 07 offset -> temp
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// 08 counterL
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// 09 counterI
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// 10 counterJ
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// 11 pB
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// 12 pCRow0
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// 13 pCRow1
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// 14 pCRow2
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// 15 pCRow3
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// 16 pA
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// 17 alpha_save_R
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// 18 must save alpha_save_I
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// 19 must save
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// 20 must save
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// 21 must save
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// 22 must save
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// 23 must save
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// 24 must save
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// 25 must save
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// 26 must save
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// 27 must save
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// 28 must save
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// 29 frame
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// 30 link
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// 31 sp
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//v00 ALPHA_R -> pA00_R, pA01_R
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//v01 ALPHA_I -> pA00_I, pA01_I
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//v02 pA02_R, pA03_R
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//v03 pA02_I, pA03_I
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//v04 pA10_R, pA11_R
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//v05 pA10_I, pA11_I
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//v06 pA12_R, pA13_R
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//v07 pA12_I, pA13_I
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//v08 must save pB00_R, pB01_R
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//v09 must save pB00_I, pB01_I
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//v10 must save pB02_R, pB03_R OR ALPHA0_R
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//v11 must save pB02_I, pB03_I OR ALPHA0_I
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//v12 must save pB10_R, pB11_R
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//v13 must save pB10_I, pB11_I
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//v14 must save pB12_R, pB13_R OR ALPHA1_R
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//v15 must save pB12_I, pB13_I OR ALPHA1_R
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//v16 pC0R
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//v17 pC0I
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//v18 pC1R
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//v19 pC1I
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//v20 pC2R
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//v21 pC2I
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//v22 pC3R
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//v23 pC3I
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//v24 pC3R
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//v25 pC3I
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//v26 pC22_R, pC23_R
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//v27 pC22_I, pC23_I
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//v28 pC30_R, pC31_R
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//v29 pC30_I, pC31_I
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//v30 pC32_R, pC33_R
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//v31 pC32_I, pC33_I
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/*******************************************************************************
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* Macro definitions
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*******************************************************************************/
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.macro INITv1x4
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dup z16.s, #0
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dup z17.s, #0
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dup z18.s, #0
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dup z19.s, #0
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dup z20.s, #0
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dup z21.s, #0
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dup z22.s, #0
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dup z23.s, #0
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.endm
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.macro KERNELv1x4_I
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ld2w {z0.s, z1.s}, p1/z, [pA]
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add pA, pA, lanes, lsl #3 // pA += lanes*2*4
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ld2w {z2.s, z3.s}, p1/z, [pA] // next one
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add pA, pA, lanes, lsl #3 // pA += lanes*2*4
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ld1rw z8.s, p0/z, [pB]
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ld1rw z9.s, p0/z, [pB, 4]
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ld1rw z10.s, p0/z, [pB, 8]
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ld1rw z11.s, p0/z, [pB, 12]
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ld1rw z12.s, p0/z, [pB, 16]
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ld1rw z13.s, p0/z, [pB, 20]
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ld1rw z14.s, p0/z, [pB, 24]
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ld1rw z15.s, p0/z, [pB, 28]
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add pB, pB, 32
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fmla z16.s, p1/m, z0.s, z8.s
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OP_ir z17.s, p1/m, z1.s, z8.s
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ld1rw z8.s, p0/z, [pB]
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#if defined(NR) || defined(NC) || defined(TR) || defined(TC) || \
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defined(RR) || defined(RC) || defined(CR) || defined(CC)
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#eor z17.16b, z17.16b, z17.16b
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fmls z17.s, p1/m, z0.s, z9.s
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#else
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fmla z17.s, p1/m, z0.s, z9.s
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#endif
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OP_ii z16.s, p1/m, z1.s, z9.s
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ld1rw z9.s, p0/z, [pB, 4]
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fmla z18.s, p1/m, z0.s, z10.s
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OP_ir z19.s, p1/m, z1.s, z10.s
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ld1rw z10.s, p0/z, [pB, 8]
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OP_ii z18.s, p1/m, z1.s, z11.s
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#if defined(NR) || defined(NC) || defined(TR) || defined(TC) || \
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defined(RR) || defined(RC) || defined(CR) || defined(CC)
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#eor z19.16b, z21.16b, z21.16b
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fmls z19.s, p1/m, z0.s, z11.s
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#else
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fmla z19.s, p1/m, z0.s, z11.s
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#endif
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ld1rw z11.s, p0/z, [pB, 12]
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fmla z20.s, p1/m, z0.s, z12.s
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OP_ir z21.s, p1/m, z1.s, z12.s
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ld1rw z12.s, p0/z, [pB, 16]
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#if defined(NR) || defined(NC) || defined(TR) || defined(TC) || \
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defined(RR) || defined(RC) || defined(CR) || defined(CC)
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#eor z21.16b, z23.16b, z23.16b
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fmls z21.s, p1/m, z0.s, z13.s
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#else
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fmla z21.s, p1/m, z0.s, z13.s
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#endif
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OP_ii z20.s, p1/m, z1.s, z13.s
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ld1rw z13.s, p0/z, [pB, 20]
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fmla z22.s, p1/m, z0.s, z14.s
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OP_ir z23.s, p1/m, z1.s, z14.s
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ld1rw z14.s, p0/z, [pB, 24]
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#if defined(NR) || defined(NC) || defined(TR) || defined(TC) || \
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defined(RR) || defined(RC) || defined(CR) || defined(CC)
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#eor z23.16b, z19.16b, z19.16b
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fmls z23.s, p1/m, z0.s, z15.s
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#else
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fmla z23.s, p1/m, z0.s, z15.s
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#endif
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OP_ii z22.s, p1/m, z1.s, z15.s
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ld1rw z15.s, p0/z, [pB, 28]
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add pB, pB, 32
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.endm
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.macro KERNELv1x4_M1
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ld2w {z2.s, z3.s}, p1/z, [pA]
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add pA, pA, lanes, lsl #3 // pA = pA + lanes * 2 * 4
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OP_rr z16.s, p1/m, z0.s, z8.s
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OP_ir z17.s, p1/m, z1.s, z8.s
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ld1rw z8.s, p0/z, [pB]
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OP_ii z16.s, p1/m, z1.s, z9.s
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OP_ri z17.s, p1/m, z0.s, z9.s
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ld1rw z9.s, p0/z, [pB, 4]
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OP_rr z18.s, p1/m, z0.s, z10.s
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OP_ir z19.s, p1/m, z1.s, z10.s
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ld1rw z10.s, p0/z, [pB, 8]
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OP_ii z18.s, p1/m, z1.s, z11.s
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OP_ri z19.s, p1/m, z0.s, z11.s
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ld1rw z11.s, p0/z, [pB, 12]
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OP_rr z20.s, p1/m, z0.s, z12.s
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OP_ir z21.s, p1/m, z1.s, z12.s
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ld1rw z12.s, p0/z, [pB, 16]
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OP_ii z20.s, p1/m, z1.s, z13.s
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OP_ri z21.s, p1/m, z0.s, z13.s
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ld1rw z13.s, p0/z, [pB, 20]
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OP_rr z22.s, p1/m, z0.s, z14.s
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OP_ir z23.s, p1/m, z1.s, z14.s
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ld1rw z14.s, p0/z, [pB, 24]
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OP_ii z22.s, p1/m, z1.s, z15.s
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OP_ri z23.s, p1/m, z0.s, z15.s
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ld1rw z15.s, p0/z, [pB, 28]
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add pB, pB, 32
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.endm
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.macro KERNELv1x4_M2
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ld2w {z0.s, z1.s}, p1/z, [pA]
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add pA, pA, lanes, lsl #3 // pA = pA + lanes *2 * 4
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OP_rr z16.s, p1/m, z2.s, z8.s
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OP_ir z17.s, p1/m, z3.s, z8.s
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ld1rw z8.s, p0/z, [pB]
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OP_ii z16.s, p1/m, z3.s, z9.s
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OP_ri z17.s, p1/m, z2.s, z9.s
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ld1rw z9.s, p0/z, [pB, 4]
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OP_rr z18.s, p1/m, z2.s, z10.s
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OP_ir z19.s, p1/m, z3.s, z10.s
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ld1rw z10.s, p0/z, [pB, 8]
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OP_ii z18.s, p1/m, z3.s, z11.s
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OP_ri z19.s, p1/m, z2.s, z11.s
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ld1rw z11.s, p0/z, [pB, 12]
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OP_rr z20.s, p1/m, z2.s, z12.s
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OP_ir z21.s, p1/m, z3.s, z12.s
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ld1rw z12.s, p0/z, [pB, 16]
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OP_ii z20.s, p1/m, z3.s, z13.s
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OP_ri z21.s, p1/m, z2.s, z13.s
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ld1rw z13.s, p0/z, [pB, 20]
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OP_rr z22.s, p1/m, z2.s, z14.s
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OP_ir z23.s, p1/m, z3.s, z14.s
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ld1rw z14.s, p0/z, [pB, 24]
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OP_ii z22.s, p1/m, z3.s, z15.s
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OP_ri z23.s, p1/m, z2.s, z15.s
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ld1rw z15.s, p0/z, [pB, 28]
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add pB, pB, 32
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.endm
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.macro KERNELv1x4_E
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OP_rr z16.s, p1/m, z2.s, z8.s
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OP_ir z17.s, p1/m, z3.s, z8.s
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OP_ii z16.s, p1/m, z3.s, z9.s
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OP_ri z17.s, p1/m, z2.s, z9.s
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OP_rr z18.s, p1/m, z2.s, z10.s
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OP_ir z19.s, p1/m, z3.s, z10.s
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OP_ii z18.s, p1/m, z3.s, z11.s
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OP_ri z19.s, p1/m, z2.s, z11.s
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OP_rr z20.s, p1/m, z2.s, z12.s
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OP_ir z21.s, p1/m, z3.s, z12.s
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OP_ii z20.s, p1/m, z3.s, z13.s
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OP_ri z21.s, p1/m, z2.s, z13.s
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OP_rr z22.s, p1/m, z2.s, z14.s
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OP_ir z23.s, p1/m, z3.s, z14.s
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OP_ii z22.s, p1/m, z3.s, z15.s
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OP_ri z23.s, p1/m, z2.s, z15.s
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.endm
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.macro KERNELv1x4_SUB
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ld2w {z0.s, z1.s}, p1/z, [pA]
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add pA, pA, lanes, lsl #3 // pA = pA + lanes* 2 * 4
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ld1rw z8.s, p0/z, [pB]
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ld1rw z9.s, p0/z, [pB, 4]
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ld1rw z10.s, p0/z, [pB, 8]
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ld1rw z11.s, p0/z, [pB, 12]
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OP_rr z16.s, p1/m, z0.s, z8.s
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OP_ir z17.s, p1/m, z1.s, z8.s
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OP_ii z16.s, p1/m, z1.s, z9.s
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OP_ri z17.s, p1/m, z0.s, z9.s
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ld1rw z12.s, p0/z, [pB, 16]
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ld1rw z13.s, p0/z, [pB, 20]
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ld1rw z14.s, p0/z, [pB, 24]
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ld1rw z15.s, p0/z, [pB, 28]
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OP_rr z18.s, p1/m, z0.s, z10.s
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OP_ir z19.s, p1/m, z1.s, z10.s
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OP_ii z18.s, p1/m, z1.s, z11.s
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OP_ri z19.s, p1/m, z0.s, z11.s
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add pB, pB, 32
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OP_rr z20.s, p1/m, z0.s, z12.s
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OP_ir z21.s, p1/m, z1.s, z12.s
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OP_ii z20.s, p1/m, z1.s, z13.s
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OP_ri z21.s, p1/m, z0.s, z13.s
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OP_rr z22.s, p1/m, z0.s, z14.s
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OP_ir z23.s, p1/m, z1.s, z14.s
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OP_ii z22.s, p1/m, z1.s, z15.s
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OP_ri z23.s, p1/m, z0.s, z15.s
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.endm
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.macro SAVEv1x4
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ld2w {z24.s, z25.s}, p1/z, [pCRow0]
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fmla z24.s, p1/m, z16.s, alphaz_R
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fmls z24.s, p1/m, z17.s, alphaz_I
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fmla z25.s, p1/m, z16.s, alphaz_I
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fmla z25.s, p1/m, z17.s, alphaz_R
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st2w {z24.s, z25.s}, p1, [pCRow0]
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add pCRow0, pCRow0, lanes, lsl #3
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ld2w {z26.s, z27.s}, p1/z, [pCRow1]
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fmla z26.s, p1/m, z18.s, alphaz_R
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fmls z26.s, p1/m, z19.s, alphaz_I
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fmla z27.s, p1/m, z18.s, alphaz_I
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fmla z27.s, p1/m, z19.s, alphaz_R
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st2w {z26.s, z27.s}, p1, [pCRow1]
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add pCRow1, pCRow1, lanes, lsl #3
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ld2w {z28.s, z29.s}, p1/z, [pCRow2]
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fmla z28.s, p1/m, z20.s, alphaz_R
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fmls z28.s, p1/m, z21.s, alphaz_I
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fmla z29.s, p1/m, z20.s, alphaz_I
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fmla z29.s, p1/m, z21.s, alphaz_R
|
|
st2w {z28.s, z29.s}, p1, [pCRow2]
|
|
|
|
add pCRow2, pCRow2, lanes, lsl #3
|
|
|
|
ld2w {z30.s, z31.s}, p1/z, [pCRow3]
|
|
fmla z30.s, p1/m, z22.s, alphaz_R
|
|
fmls z30.s, p1/m, z23.s, alphaz_I
|
|
fmla z31.s, p1/m, z22.s, alphaz_I
|
|
fmla z31.s, p1/m, z23.s, alphaz_R
|
|
st2w {z30.s, z31.s}, p1, [pCRow3]
|
|
|
|
add pCRow3, pCRow3, lanes, lsl #3 // pC = pC + lanes * 2 *4
|
|
|
|
.endm
|
|
|
|
/******************************************************************************/
|
|
|
|
|
|
.macro INITv1x2
|
|
dup z16.s, #0
|
|
dup z17.s, #0
|
|
dup z18.s, #0
|
|
dup z19.s, #0
|
|
.endm
|
|
|
|
.macro KERNELv1x2_SUB
|
|
ld2w {z0.s, z1.s}, p1/z, [pA]
|
|
add pA, pA, lanes, lsl #3 // pA = pA + lanes* 2 * 4
|
|
|
|
ld1rw z8.s, p0/z, [pB]
|
|
ld1rw z9.s, p0/z, [pB, 4]
|
|
ld1rw z10.s, p0/z, [pB, 8]
|
|
ld1rw z11.s, p0/z, [pB, 12]
|
|
|
|
OP_rr z16.s, p1/m, z0.s, z8.s
|
|
OP_ir z17.s, p1/m, z1.s, z8.s
|
|
OP_ii z16.s, p1/m, z1.s, z9.s
|
|
OP_ri z17.s, p1/m, z0.s, z9.s
|
|
|
|
OP_rr z18.s, p1/m, z0.s, z10.s
|
|
OP_ir z19.s, p1/m, z1.s, z10.s
|
|
OP_ii z18.s, p1/m, z1.s, z11.s
|
|
OP_ri z19.s, p1/m, z0.s, z11.s
|
|
|
|
add pB, pB, 16
|
|
.endm
|
|
|
|
.macro SAVEv1x2
|
|
ld2w {z24.s, z25.s}, p1/z, [pCRow0]
|
|
fmla z24.s, p1/m, z16.s, alphaz_R
|
|
fmls z24.s, p1/m, z17.s, alphaz_I
|
|
fmla z25.s, p1/m, z16.s, alphaz_I
|
|
fmla z25.s, p1/m, z17.s, alphaz_R
|
|
st2w {z24.s, z25.s}, p1, [pCRow0]
|
|
|
|
add pCRow0, pCRow0, lanes, lsl #3
|
|
|
|
ld2w {z26.s, z27.s}, p1/z, [pCRow1]
|
|
fmla z26.s, p1/m, z18.s, alphaz_R
|
|
fmls z26.s, p1/m, z19.s, alphaz_I
|
|
fmla z27.s, p1/m, z18.s, alphaz_I
|
|
fmla z27.s, p1/m, z19.s, alphaz_R
|
|
st2w {z26.s, z27.s}, p1, [pCRow1]
|
|
|
|
add pCRow1, pCRow1, lanes, lsl #3
|
|
.endm
|
|
|
|
/******************************************************************************/
|
|
|
|
|
|
.macro INITv1x1
|
|
dup z16.s, #0
|
|
dup z17.s, #0
|
|
.endm
|
|
|
|
|
|
.macro KERNELv1x1_SUB
|
|
ld2w {z0.s, z1.s}, p1/z, [pA]
|
|
add pA, pA, lanes, lsl #3 // pA = pA + lanes* 2 * 4
|
|
|
|
ld1rw z8.s, p0/z, [pB]
|
|
ld1rw z9.s, p0/z, [pB, 4]
|
|
|
|
add pB, pB, 8
|
|
|
|
OP_rr z16.s, p1/m, z0.s, z8.s
|
|
OP_ir z17.s, p1/m, z1.s, z8.s
|
|
OP_ii z16.s, p1/m, z1.s, z9.s
|
|
OP_ri z17.s, p1/m, z0.s, z9.s
|
|
.endm
|
|
|
|
.macro SAVEv1x1
|
|
ld2w {z24.s, z25.s}, p1/z, [pCRow0]
|
|
fmla z24.s, p1/m, z16.s, alphaz_R
|
|
fmls z24.s, p1/m, z17.s, alphaz_I
|
|
fmla z25.s, p1/m, z16.s, alphaz_I
|
|
fmla z25.s, p1/m, z17.s, alphaz_R
|
|
st2w {z24.s, z25.s}, p1, [pCRow0]
|
|
|
|
add pCRow0, pCRow0, lanes, lsl #3 // pC = pC + lanes * 2 *4
|
|
|
|
.endm
|
|
|
|
/******************************************************************************/
|
|
|
|
/*******************************************************************************
|
|
* End of macro definitions
|
|
*******************************************************************************/
|
|
|
|
PROLOGUE
|
|
|
|
.align 5
|
|
add sp, sp, #-(11 * 16)
|
|
stp d8, d9, [sp, #(0 * 16)]
|
|
stp d10, d11, [sp, #(1 * 16)]
|
|
stp d12, d13, [sp, #(2 * 16)]
|
|
stp d14, d15, [sp, #(3 * 16)]
|
|
stp d16, d17, [sp, #(4 * 16)]
|
|
stp x18, x19, [sp, #(5 * 16)]
|
|
stp x20, x21, [sp, #(6 * 16)]
|
|
stp x22, x23, [sp, #(7 * 16)]
|
|
stp x24, x25, [sp, #(8 * 16)]
|
|
stp x26, x27, [sp, #(9 * 16)]
|
|
str x28, [sp, #(10 * 16)]
|
|
|
|
fmov alphaR, s0
|
|
dup alphaz_R, alphaR
|
|
fmov alphaI, s1
|
|
dup alphaz_I, alphaI
|
|
|
|
lsl LDC, LDC, #3 // ldc = ldc * 2 * 4
|
|
ptrue p0.s // create true predicate
|
|
|
|
mov pB, origPB
|
|
|
|
// Loop over N
|
|
mov counterJ, origN
|
|
asr counterJ, counterJ, #2 // J = J / 4
|
|
cmp counterJ, #0
|
|
ble .Lcgemm_kernel_L2_BEGIN
|
|
|
|
/******************************************************************************/
|
|
.Lcgemm_kernel_L4_BEGIN:
|
|
mov pCRow0, pC
|
|
add pCRow1, pCRow0, LDC
|
|
add pCRow2, pCRow1, LDC
|
|
add pCRow3, pCRow2, LDC
|
|
|
|
add pC, pCRow3, LDC
|
|
|
|
mov pA, origPA // pA = start of A array
|
|
|
|
.Lcgemm_kernel_L4_Mv1_BEGIN:
|
|
|
|
/* Loop over M is done in an SVE fashion. This has the benefit of the last M%SVE_LEN iterations being done in a single sweep */
|
|
mov counterI, #0
|
|
whilelt p1.s, counterI, origM
|
|
cntp lanes, p0, p1.s // lanes contain number of active SVE lanes in M dimension
|
|
|
|
.align 5
|
|
.Lcgemm_kernel_L4_Mv1_20:
|
|
|
|
mov pB, origPB
|
|
INITv1x4 // fill with zeros
|
|
|
|
asr counterL , origK, #3
|
|
cmp counterL , #2
|
|
blt .Lcgemm_kernel_L4_Mv1_32
|
|
|
|
KERNELv1x4_I
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
|
|
subs counterL, counterL, #2 // subtract 2
|
|
ble .Lcgemm_kernel_L4_Mv1_22a
|
|
|
|
.align 5
|
|
.Lcgemm_kernel_L4_Mv1_22:
|
|
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
|
|
subs counterL, counterL, #1
|
|
bgt .Lcgemm_kernel_L4_Mv1_22
|
|
|
|
.align 5
|
|
.Lcgemm_kernel_L4_Mv1_22a:
|
|
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_E
|
|
|
|
b .Lcgemm_kernel_L4_Mv1_44
|
|
|
|
.align 5
|
|
.Lcgemm_kernel_L4_Mv1_32:
|
|
|
|
tst counterL, #1
|
|
ble .Lcgemm_kernel_L4_Mv1_40
|
|
|
|
KERNELv1x4_I
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_M2
|
|
KERNELv1x4_M1
|
|
KERNELv1x4_E
|
|
|
|
b .Lcgemm_kernel_L4_Mv1_44
|
|
|
|
|
|
.Lcgemm_kernel_L4_Mv1_40:
|
|
|
|
INITv1x4
|
|
|
|
.Lcgemm_kernel_L4_Mv1_44:
|
|
|
|
ands counterL , origK, #7
|
|
ble .Lcgemm_kernel_L4_Mv1_100
|
|
|
|
.align 5
|
|
.Lcgemm_kernel_L4_Mv1_46:
|
|
KERNELv1x4_SUB
|
|
|
|
subs counterL, counterL, #1
|
|
bne .Lcgemm_kernel_L4_Mv1_46
|
|
|
|
.Lcgemm_kernel_L4_Mv1_100:
|
|
SAVEv1x4
|
|
|
|
.Lcgemm_kernel_L4_Mv1_END:
|
|
|
|
incw counterI
|
|
whilelt p1.s, counterI, origM //SVE instruction
|
|
cntp lanes, p0, p1.s // lanes contain number of active SVE lanes in M dimension
|
|
b.any .Lcgemm_kernel_L4_Mv1_20
|
|
|
|
|
|
|
|
.Lcgemm_kernel_L4_END:
|
|
|
|
lsl temp, origK, #5
|
|
add origPB, origPB, temp // B = B + K * 4 * 4 * 2
|
|
|
|
subs counterJ, counterJ , #1 // j--
|
|
bgt .Lcgemm_kernel_L4_BEGIN
|
|
|
|
|
|
/******************************************************************************/
|
|
|
|
.Lcgemm_kernel_L2_BEGIN: // less than 2 left in N direction
|
|
|
|
mov counterJ , origN
|
|
tst counterJ , #3
|
|
ble .Lcgemm_kernel_L999
|
|
|
|
tst counterJ , #2
|
|
ble .Lcgemm_kernel_L1_BEGIN
|
|
|
|
mov pCRow0, pC // pCRow0 = pC
|
|
add pCRow1, pCRow0, LDC
|
|
|
|
add pC,pC,LDC, lsl #1
|
|
|
|
mov pA, origPA // pA = A
|
|
|
|
|
|
|
|
.Lcgemm_kernel_L2_Mv1_BEGIN:
|
|
|
|
mov counterI, #0
|
|
whilelt p1.s, counterI, origM //SVE instruction
|
|
cntp lanes, p0, p1.s
|
|
|
|
|
|
.Lcgemm_kernel_L2_Mv1_20:
|
|
|
|
INITv1x2
|
|
|
|
mov pB, origPB
|
|
asr counterL , origK, #3 // counterL = counterL / 8
|
|
cmp counterL,#0
|
|
ble .Lcgemm_kernel_L2_Mv1_40
|
|
.align 5
|
|
|
|
.Lcgemm_kernel_L2_Mv1_22:
|
|
KERNELv1x2_SUB
|
|
KERNELv1x2_SUB
|
|
KERNELv1x2_SUB
|
|
KERNELv1x2_SUB
|
|
|
|
KERNELv1x2_SUB
|
|
KERNELv1x2_SUB
|
|
KERNELv1x2_SUB
|
|
KERNELv1x2_SUB
|
|
|
|
subs counterL, counterL, #1
|
|
bgt .Lcgemm_kernel_L2_Mv1_22
|
|
|
|
|
|
.Lcgemm_kernel_L2_Mv1_40:
|
|
|
|
ands counterL , origK, #7 // counterL = counterL % 8
|
|
ble .Lcgemm_kernel_L2_Mv1_100
|
|
|
|
.Lcgemm_kernel_L2_Mv1_42:
|
|
|
|
KERNELv1x2_SUB
|
|
|
|
subs counterL, counterL, #1
|
|
bgt .Lcgemm_kernel_L2_Mv1_42
|
|
|
|
.Lcgemm_kernel_L2_Mv1_100:
|
|
|
|
SAVEv1x2
|
|
|
|
.Lcgemm_kernel_L2_Mv1_END:
|
|
|
|
|
|
incw counterI
|
|
whilelt p1.s, counterI, origM //SVE instruction
|
|
cntp lanes, p0, p1.s
|
|
b.any .Lcgemm_kernel_L2_Mv1_20
|
|
|
|
|
|
.Lcgemm_kernel_L2_END:
|
|
lsl temp, origK, #4
|
|
add origPB, origPB, temp // B = B + K * 2 * 4 * 2
|
|
|
|
/******************************************************************************/
|
|
|
|
.Lcgemm_kernel_L1_BEGIN:
|
|
|
|
mov counterJ , origN
|
|
tst counterJ , #1
|
|
ble .Lcgemm_kernel_L999 // done
|
|
|
|
|
|
mov pCRow0, pC // pCRow0 = C
|
|
add pC , pC , LDC // Update pC to point to next
|
|
|
|
mov pA, origPA // pA = A
|
|
|
|
.Lcgemm_kernel_L1_Mv1_BEGIN:
|
|
|
|
mov counterI, #0
|
|
whilelt p1.s, counterI, origM //SVE instruction
|
|
cntp lanes, p0, p1.s
|
|
|
|
|
|
.Lcgemm_kernel_L1_Mv1_20:
|
|
|
|
INITv1x1
|
|
|
|
mov pB, origPB
|
|
asr counterL , origK, #3 // counterL = counterL / 8
|
|
cmp counterL , #0
|
|
ble .Lcgemm_kernel_L1_Mv1_40
|
|
.align 5
|
|
|
|
.Lcgemm_kernel_L1_Mv1_22:
|
|
KERNELv1x1_SUB
|
|
KERNELv1x1_SUB
|
|
KERNELv1x1_SUB
|
|
KERNELv1x1_SUB
|
|
|
|
KERNELv1x1_SUB
|
|
KERNELv1x1_SUB
|
|
KERNELv1x1_SUB
|
|
KERNELv1x1_SUB
|
|
|
|
subs counterL, counterL, #1
|
|
bgt .Lcgemm_kernel_L1_Mv1_22
|
|
|
|
|
|
.Lcgemm_kernel_L1_Mv1_40:
|
|
|
|
ands counterL , origK, #7 // counterL = counterL % 8
|
|
ble .Lcgemm_kernel_L1_Mv1_100
|
|
|
|
.Lcgemm_kernel_L1_Mv1_42:
|
|
|
|
KERNELv1x1_SUB
|
|
|
|
subs counterL, counterL, #1
|
|
bgt .Lcgemm_kernel_L1_Mv1_42
|
|
|
|
.Lcgemm_kernel_L1_Mv1_100:
|
|
|
|
SAVEv1x1
|
|
|
|
.Lcgemm_kernel_L1_Mv1_END:
|
|
|
|
incw counterI
|
|
whilelt p1.s, counterI, origM //SVE instruction
|
|
cntp lanes, p0, p1.s
|
|
b.any .Lcgemm_kernel_L1_Mv1_20
|
|
|
|
.Lcgemm_kernel_L1_END:
|
|
|
|
/******************************************************************************/
|
|
|
|
.Lcgemm_kernel_L999:
|
|
mov x0, #0 // set return value
|
|
ldp d8, d9, [sp, #(0 * 16)]
|
|
ldp d10, d11, [sp, #(1 * 16)]
|
|
ldp d12, d13, [sp, #(2 * 16)]
|
|
ldp d14, d15, [sp, #(3 * 16)]
|
|
ldp d16, d17, [sp, #(4 * 16)]
|
|
ldp x18, x19, [sp, #(5 * 16)]
|
|
ldp x20, x21, [sp, #(6 * 16)]
|
|
ldp x22, x23, [sp, #(7 * 16)]
|
|
ldp x24, x25, [sp, #(8 * 16)]
|
|
ldp x26, x27, [sp, #(9 * 16)]
|
|
ldr x28, [sp, #(10 * 16)]
|
|
add sp, sp, #(11*16)
|
|
ret
|
|
|
|
EPILOGUE
|
|
|