27816fa929
Merge pull request #4472 from sergei-lewis/dev/slewis/merge-from-riscv
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Merge risc-v branch to develop
2024-02-03 20:56:11 +01:00
b6949ce74c
add axpyc to cmake build
2024-02-02 14:42:27 +03:00
441339104f
fix test ext cmake build
2024-02-02 13:49:39 +03:00
f68e9989c4
Remove zero rows/columns matcopy tests
2024-02-02 12:26:23 +03:00
87ba528d8b
Changed C files to straighten out indentation. Removed commented lines from other file.
2024-02-01 18:46:07 -06:00
461cf9083c
Merge remote-tracking branch 'origin/develop' into cgemm_zgemm_c_code
2024-02-01 12:40:04 -06:00
ddac75e0ef
Adding .C versions of CGEMM and ZGEMM
2024-02-01 12:24:25 -06:00
2bb7ea64a1
Only vectorize 64-bit version for Power8.
2024-02-01 08:11:43 -06:00
3ffd6868d7
Merge branch 'develop' into dev/slewis/merge-from-riscv
2024-02-01 11:29:41 +00:00
a3b0ef6596
Restore riscv64 fixes from develop branch: dot product double precision accumulation, zscal NaN handling
2024-02-01 10:32:00 +00:00
ec74dcd213
Merge pull request #4470 from martin-frbg/issue4455
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Add CBLAS interfaces for BLAS extensions ?AMIN/?AMAX and C/ZAXPYC
2024-01-31 23:51:01 +01:00
61c8e19f95
Fix Makefile to support OpenMP on AIX for xlc (clang) with xlf.
2024-01-31 15:27:50 -06:00
42cb567f0f
more cleanup
2024-01-31 13:24:28 -08:00
47bd064763
Fix names in build rules
2024-01-31 20:49:43 +01:00
a7d004e820
Fix CBLAS prototype
2024-01-31 17:55:42 +01:00
b54cda8490
Unify creation of CBLAS interfaces for ?AMIN/?AMAX and C/ZAXPYC between gmake and cmake builds
2024-01-31 16:00:52 +01:00
1a6fdb0353
Add prototypes for extensions ?AMIN/?AMAX and CAXPYC/ZAXPYC
2024-01-31 15:57:57 +01:00
d1343302bd
Merge pull request #4465 from XiWeiGu/utest-zscal
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utest: Add tests for zscal
2024-01-31 14:19:19 +01:00
969601a1dc
X86_64: Fixed bug in zscal
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Fixed handling of NAN and INF arguments when
inc is greater than 1.
2024-01-31 11:23:59 +08:00
98c9ff3194
Merge pull request #4464 from XiWeiGu/loongarch64-zscal
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LoongArch64: Handle NAN and INF
2024-01-30 22:53:29 +01:00
9f0630187a
Merge pull request #4463 from XiWeiGu/loongarch64-zamax-zamin
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Loongarch64: amax and amin
2024-01-30 18:01:30 +01:00
09bb48d1b9
Vectorize in-copy packing/copying for SGEMM - 4X faster.
2024-01-30 09:13:16 -06:00
bb043a021f
utest: Add tests for zscal
2024-01-30 17:42:37 +08:00
83ce97a4ca
LoongArch64: Handle NAN and INF
2024-01-30 17:17:30 +08:00
0d7fe5ea61
clean up whitespace
2024-01-29 22:33:47 -08:00
3d4dfd0085
Benchmark: Rename the executable file names for {sc/dz}a{min/max}
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No interface named {c/z}a{min/max}, keeping it would
cause ambiguity
2024-01-30 11:33:01 +08:00
a79d117405
LoogArch64: Fixed bug for {s/d}amin
2024-01-30 11:32:57 +08:00
519ea6e87a
utest: Add utest for the {sc/dz}amax and {s/d/sc/dz}amin
2024-01-30 11:32:36 +08:00
1093def0d1
Merge branch 'risc-v' into develop
2024-01-29 11:11:39 +00:00
8892121130
Merge pull request #4462 from martin-frbg/issue4449
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Use +sve in arch declarations of the fallback paths for SVE targets
2024-01-26 22:41:16 +01:00
48a4c4d454
Use +sve in arch declarations of the fallback paths for SVE targets
2024-01-26 16:30:52 +01:00
e0b610d01f
Harmonize riscv64 LIBNAME for forced and non-forced targets
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The forced values for LIBNAME were either riscv64_generic or c910v
while the non-forced value of LIBNAME was always riscv64.
2024-01-26 15:18:18 +00:00
ec2aa32eb0
Fix crash in cpuid_riscv64.c
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The crash is reproducible when building OpenBLAS without forcing a
target in a riscv64 container running on an X86_64 machine with an
older version of QEMU, e.g., 7.0.0, registered with binfmt_misc to
run riscv64 binaries. With this setup, cat /proc/cpuinfo in the
container returns the cpu information for the host, which contains a
"model name" string, and we execute the buggy code. The code in
question is searching in an uninitialised buffer for the ':' character
and doesn't check to see whether it was found or not. This can result
in pmodel containing the pointer value 1 and a crash when pmodel is
defererenced. The algorithm to detect the C910V CPU has not been
modified, merely fixed to prevent the crash.
A few additional checks for NULL pointers are added to improve the
robustness of the code and a whitespace error is corrected.
2024-01-26 15:17:31 +00:00
889c5d026a
Merge pull request #4456 from kseniyazaytseva/riscv-rvv10
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Fix BLAS and LAPACK tests for RVV 1.0 target, update to 0.12.0 intrincics
2024-01-26 13:31:09 +01:00
4e2a32ff51
Merge pull request #4454 from kseniyazaytseva/riscv-rvv07
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Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets
2024-01-26 11:40:46 +01:00
276e3ebf9e
LoongArch64: Add dzamax and dzamin opt
2024-01-26 10:03:50 +08:00
a21b2fa5e4
Merge pull request #4452 from kseniyazaytseva/riscv-generic
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Fix BLAS, BLAS-like functions and Generic RISC-V kernels
2024-01-24 17:52:25 +01:00
73530b03fa
remove RISCV64_ZVL256B additional extentions
2024-01-24 11:38:14 +03:00
86943afa9c
Fix x280 taget include riscv_vector.h
2024-01-24 10:53:13 +03:00
d938aed7fe
reset "mem structure overflowed" state on shutdown
2024-01-23 17:15:53 +01:00
9c49a81d54
Resolve conflicts
2024-01-23 19:08:53 +03:00
e1afb23811
Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets
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* Fixed bugs in dgemm, [a]min\max, asum kernels
* Added zero checks for BLAS kernels
* Added dsdot implementation for RVV 0.7.1
* Fixed bugs in _vector files for C910V and RISCV64_ZVL256B targets
* Added additional definitions for RISCV64_ZVL256B target
2024-01-23 19:01:31 +03:00
d6a5174e9c
Merge pull request #4447 from RevySR/update-thead-toolchains
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Update T-Head toolchains v2.8.0
2024-01-22 08:10:02 +01:00
304a9b60af
Update T-Head toolchains v2.8.0
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Signed-off-by: Han Gao/Revy/Rabenda <rabenda.cn@gmail.com>
2024-01-21 14:32:52 +00:00
f5de4fad27
Merge pull request #4444 from Mousius/part-mapping
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Add dynamic support for Arm(R) Neoverse(TM) V2 processor
2024-01-20 15:55:07 +01:00
aaf65210cc
Add dynamic support for Arm(R) Neoverse(TM) V2 processor
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Whilst I figure out how best to map the L2 parameters without
duplicating all of `ARMV8SVE`, lets just map this to `NEOVERSEV1`.
2024-01-19 19:05:50 +00:00
10c22f4a39
Merge pull request #4355 from imaginationtech/img-riscv64-zvl128b
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[RISC-V] Add RISC-V Vector 128-bit target
2024-01-19 13:51:07 +01:00
ccbc3f875b
[RISC-V] Add RISCV64_ZVL128B target to common_riscv64.h
2024-01-19 12:40:00 +00:00
deecfb1a39
Merge branch 'risc-v' into img-riscv64-zvl128b
2024-01-19 12:26:38 +00:00
c99e231fc5
Fix rand_generate
2024-01-18 23:56:22 +03:00
Martin Kroeker
kseniyazaytseva
austinpagan
Chip Kerchner
Sergei Lewis
Mark Seminatore
gxw
Mark Ryan
Andrey Sokolov
Han Gao/Revy/Rabenda
Chris Sidebottom
Octavian Maghiar