461ecabb22
add RISCV64_ZVL128B and RISCV64_ZVL256B targets to CI flows and to README.md
2024-02-16 16:26:29 +00:00
86943afa9c
Fix x280 taget include riscv_vector.h
2024-01-24 10:53:13 +03:00
ccbc3f875b
[RISC-V] Add RISCV64_ZVL128B target to common_riscv64.h
2024-01-19 12:40:00 +00:00
9edb805e64
fix builds with t-head toolchains that use old versions of the intrinsics spec
2024-01-16 14:33:08 +00:00
2406958629
* update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics)
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* fix multiple numerical stability and corner case issues
* add a script to generate arbitrary gemm kernel shapes
* add a generic zvl256b target to demonstrate large gemm kernel unrolls
2023-02-24 10:45:03 +00:00
387e8970cd
Fix merge problem; Update compiling COMMON_OPT per review comments.
2022-11-28 21:42:29 -08:00
bef47917bd
Initial version for riscv sifive x280
2022-11-15 00:06:25 -08:00
968e1f51d8
Update RISC-V Intrinsic API.
2022-06-06 13:52:21 +08:00
fc35b72ae1
Refs #2899
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Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910
2020-11-10 09:38:04 +08:00
ef8e7d0279
Add the support for RISC-V Vector.
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Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266
2020-10-15 16:09:02 +08:00
c167a3d6f4
Added RISCV build
2018-04-16 14:08:31 -07:00
Sergei Lewis
kseniyazaytseva
Octavian Maghiar
Heller Zheng
Xianyi Zhang
damonyu
Jerry Zhao