10 Commits

Author	SHA1	Message	Date
Martin Kroeker	df87aeb5a2	Drop the -static Fortran flag from generic builds as it breaks OpenMP	2024-06-04 09:49:18 +02:00
Andrey Sokolov	73530b03fa	remove RISCV64_ZVL256B additional extentions	2024-01-24 11:38:14 +03:00
Andrey Sokolov	9c49a81d54	Resolve conflicts	2024-01-23 19:08:53 +03:00
kseniyazaytseva	e1afb23811	Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets ... * Fixed bugs in dgemm, [a]min\max, asum kernels * Added zero checks for BLAS kernels * Added dsdot implementation for RVV 0.7.1 * Fixed bugs in _vector files for C910V and RISCV64_ZVL256B targets * Added additional definitions for RISCV64_ZVL256B target	2024-01-23 19:01:31 +03:00
Octavian Maghiar	e4586e81b8	[RISC-V] Add RISC-V Vector 128-bit target ... Current RVV x280 target depends on vlen=512-bits for Level 3 operations. Commit adds generic target that supports vlen=128-bits. New target uses the same scalable kernels as x280 for Level 1&2 operations, and autogenerated kernels for Level 3 operations. Functional correctness of Level 3 operations tested on vlen=128-bits using QEMU v8.1.1 for ctests and BLAS-Tester.	2023-12-04 11:02:18 +00:00
Heller Zheng	0954746380	remove argument unused during compilation. ... fix wrong vr = VFMVVF_FLOAT(0, vl);	2023-06-04 20:06:58 -07:00
Heller Zheng	387e8970cd	Fix merge problem; Update compiling COMMON_OPT per review comments.	2022-11-28 21:42:29 -08:00
Heller Zheng	bef47917bd	Initial version for riscv sifive x280	2022-11-15 00:06:25 -08:00
Xianyi Zhang	968e1f51d8	Update RISC-V Intrinsic API.	2022-06-06 13:52:21 +08:00
damonyu	ef8e7d0279	Add the support for RISC-V Vector. ... Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266	2020-10-15 16:09:02 +08:00