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35 Commits

Author SHA1 Message Date
kseniyazaytseva ff41cf5c49 Fix BLAS, BLAS-like functions and Generic RISC-V kernels 
* Fixed gemmt, imatcopy, zimatcopy_cnc functions
* Fixed cblas_cscal testing in ctest
* Removed rotmg unreacheble code
* Added zero size checks
 2024-01-18 23:19:52 +03:00
Martin Kroeker 88e994116c
Merge pull request #4354 from imaginationtech/img-rvv-kernel-generator 
[RISC-V] Improve RVV kernel generator LMUL usage
 2024-01-17 15:19:37 +01:00
Sergei Lewis 9edb805e64 fix builds with t-head toolchains that use old versions of the intrinsics spec 2024-01-16 14:33:08 +00:00
Octavian Maghiar 4a12cf53ec [RISC-V] Improve RVV kernel generator LMUL usage 
The RVV kernel generation script uses the provided LMUL to increase the number of accumulator registers.
Since the effect of the LMUL is to group together the vector registers into larger ones, it actually should be used as a multiplier in the calculation of vlenmax.
At the moment, no matter what LMUL is provided, the generated kernels would only set the maximum number of vector elements equal to VLEN/SEW.
Commit changes the use of LMUL to properly adjust vlenmax. Note that an increase in LMUL results in a decrease in the number of effective vector registers.
 2023-12-04 11:13:35 +00:00
Octavian Maghiar 826a9d5fa4 Adds tail undisturbed for RVV Level 2 operations 
During the last iteration of some RVV operations, accumulators can get overwritten when VL < VLMAX and tail policy is agnostic.
Commit changes intrinsics tail policy to undistrubed.
 2023-07-25 11:36:23 +01:00
Octavian Maghiar 8df0289db6 Adds tail undisturbed for RVV Level 1 operations 
During the last iteration of some RVV operations, accumulators can get overwritten when VL < VLMAX and tail policy is agnostic.
Commit changes intrinsics tail policy to undistrubed.
 2023-07-20 15:28:35 +01:00
Octavian Maghiar 1e4a3a2b5e Fixes RVV masked intrinsics for izamax/izamin kernels 2023-07-12 12:55:50 +01:00
Octavian Maghiar e1958eb705 Fixes RVV masked intrinsics for iamax/iamin/imax/imin kernels 
Changes masked intrinsics from _m to _mu and reintroduces maskedoff argument.
 2023-07-05 11:34:00 +01:00
ZhengSh 2a8bc38cdc
Merge branch 'xianyi:risc-v' into risc-v 2023-06-09 20:01:03 +08:00
Heller Zheng 0954746380 remove argument unused during compilation. 
fix wrong vr = VFMVVF_FLOAT(0, vl);
 2023-06-04 20:06:58 -07:00
sh-zheng d3bf5a5401 Combine two reduction operations of zhe/symv into one, with tail undisturbed setted. 2023-05-22 22:39:45 +08:00
sh-zheng 18d7afe69d Add rvv support for zsymv and active rvv support for zhemv 2023-05-20 01:19:44 +08:00
Heller Zheng 1374a2d08b This PR adapts latest spec changes 
Add prefix (_riscv) for all riscv intrinsics
Update some intrinsics' parameter, like vfredxxxx, vmerge
 2023-03-19 23:59:03 -07:00
Zhang Xianyi 19f17c8bc6
Merge pull request #3893 from HellerZheng/develop 
add riscv level3 C,Z kernel functions.
 2023-03-15 10:17:13 +08:00
Sergei Lewis 9b61be4545 factoring riscv64/dot.c fix into separate PR as requested 2023-03-01 17:40:42 +00:00
Sergei Lewis 2406958629 * update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) 
* fix multiple numerical stability and corner case issues
* add a script to generate arbitrary gemm kernel shapes
* add a generic zvl256b target to demonstrate large gemm kernel unrolls
 2023-02-24 10:45:03 +00:00
Heller Zheng 63cf4d0166 add riscv level3 C,Z kernel functions. 2023-02-01 19:13:44 -08:00
Xianyi Zhang c19dff0a31 Fix T-Head RVV intrinsic API changes. 2023-01-25 19:33:32 +08:00
Heller Zheng 3918d8504e nrm2 simple optimization 2022-11-21 19:06:07 -08:00
Heller Zheng 5d0d1c5551 Remove redundant files 2022-11-15 18:22:21 -08:00
Heller Zheng bef47917bd Initial version for riscv sifive x280 2022-11-15 00:06:25 -08:00
Xianyi Zhang 968e1f51d8 Update RISC-V Intrinsic API. 2022-06-06 13:52:21 +08:00
Xianyi Zhang 45786b05da Merge branch 'develop' into risc-v 2022-02-28 11:48:02 +08:00
Wu Zhigang 92b7b949dd fix bug in zscal function 
memset can not be used in zscal because of
the stride parameters.

Signed-off-by: Wu Zhigang <zhigang.wu@starfivetech.com>
 2021-12-15 01:23:30 -08:00
Zhaofeng Li 590be3fae3 riscv64: Add Makefile 2021-06-07 22:55:56 +00:00
Zhaofeng Li 3521cd48cb RISCV64_GENERIC: Use generic kernel for DSDOT for better precision 
The implementation in `riscv64/dot.c` fails the `test_dsdot` test, and
the generic kernel seems to have better precision. Tested on SiFive
FU740 (HiFive Unmatched) and QEMU.

Also see #1469.
 2021-06-07 22:50:23 +00:00
Zhaofeng Li 1e0192a5cc riscv64/imin: Fix wrong comparison 
Same as #1990.
 2021-06-07 22:49:39 +00:00
damonyu ceb44bef14 update the intrinsic api to the offical name. 2021-04-27 11:12:29 +08:00
Xianyi Zhang a3cac9cca0 Update sgemm kernel 1x4 for C910. 2020-12-18 11:53:23 +08:00
Xianyi Zhang fc35b72ae1 Refs #2899 
Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910
 2020-11-10 09:38:04 +08:00
damonyu ef8e7d0279 Add the support for RISC-V Vector. 
Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266
 2020-10-15 16:09:02 +08:00
Xianyi Zhang 265ab484c8 Change default RISC-V 64-bit corename to RISCV64_GENERIC 
e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
 2020-02-27 14:46:15 +08:00
Xianyi Zhang 44020a42a4 Fixed compile bug for RV64. 2020-02-27 14:29:42 +08:00
Jerry Zhao 0ee395db35 Fixed TRMM and SYMM for RISCV 2018-04-18 18:03:32 -07:00
Jerry Zhao c167a3d6f4 Added RISCV build 2018-04-16 14:08:31 -07:00