 Wang Qian
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d5cffd506a
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Modified the default kernel makefile in MIPS64 arch.
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2011-03-07 11:23:12 +00:00 |
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Xianyi Zhang
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5838f12995
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Support unalign address in daxpy on loongson3a simd..
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2011-03-05 10:17:10 +08:00 |
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Xianyi Zhang
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5444a3f8f7
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Unroll to 16 in daxpy on loongson3a.
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2011-03-04 17:50:17 +08:00 |
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Xianyi Zhang
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1e671b49f3
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Did the experiment with Loongson 3A 128bit load & store instruction.
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2011-01-29 03:05:27 +08:00 |
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Xianyi Zhang
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77b7020d69
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changed prefetch order.
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2011-01-29 03:03:34 +08:00 |
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Xianyi Zhang
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e003b811ab
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load x & y contiguously in axpy.
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2011-01-28 11:18:50 +08:00 |
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Xianyi Zhang
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ebe2da8474
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Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A.
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2011-01-27 23:07:06 +08:00 |
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Xianyi Zhang
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c0b5992fab
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added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.
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2011-01-26 22:34:33 +08:00 |
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Xianyi Zhang
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342bbc3871
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Import GotoBLAS2 1.13 BSD version codes.
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2011-01-24 14:54:24 +00:00 |
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