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70 Commits

Author SHA1 Message Date
Martin Kroeker
3ce28fb81a Merge pull request #2055 from martin-frbg/atomid 
Add CPUID data for Intel Denverton (as Nehalem)
 2019-03-12 22:57:07 +01:00
Martin Kroeker
04f2226ea6 Add Intel Denverton 2019-03-12 16:09:55 +01:00
Martin Kroeker
11cfd0bd75 Do not compile in AVX512 check if AVX support is disabled 
xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway
 2019-03-05 16:04:25 +01:00
caiyu
29dc72889f Add support for Hygon Dhyana 2019-01-16 14:25:19 +08:00
Martin Kroeker
dbc9a060ef Fix missing braces in support_av() call 2019-01-14 22:41:31 +01:00
Martin Kroeker
31ed19e8b9 Add message for SkylakeX and KNL fallbacks to Haswell 2019-01-05 19:41:13 +01:00
Martin Kroeker
e1574fa2b4 Add xcr0 (os support) check 2019-01-05 18:08:02 +01:00
Martin Kroeker
ae1d1f74f7 Query AVX2 and AVX512 capability for runtime cpu selection 2019-01-05 16:55:33 +01:00
Martin Kroeker
504310eeb9 Merge pull request #1665 from martin-frbg/cpuid-ryzen2 
Add cpuid for AMD Ryzen 2
 2018-07-04 08:19:40 +02:00
Martin Kroeker
d0ec4325cf Add cpuid for AMD Ryzen 2 2018-07-03 21:03:24 +02:00
Martin Kroeker
9d15a3bd16 Fix typo that broke compilation with DYNAMIC_ARCH and NO_AVX2 
fixes 1659
 2018-07-02 14:40:41 +02:00
Martin Kroeker
750162a05f Try gradual fallback for cores not in the dynamic core list 2018-06-25 21:02:31 +02:00
Martin Kroeker
1833a67071 Add support for a user-defined list of dynamic targets 2018-06-23 19:42:15 +02:00
Martin Kroeker
63f7395fb4 Move some DYNAMIC_ARCH targets to new DYNAMIC_OLDER option 2018-06-09 16:31:38 +02:00
Martin Kroeker
38ad05bd04 Extend loop range to find SkylakeX in force_coretype 2018-06-05 10:26:49 +02:00
Martin Kroeker
8be027e4c6 Update dynamic.c 2018-06-04 14:36:39 +02:00
Martin Kroeker
ac7b6e3e9a Fix misplaced endif 2018-06-04 08:23:40 +02:00
Martin Kroeker
ef626c6824 typo fix 2018-06-04 00:13:19 +02:00
Martin Kroeker
5a51cf4576 Separate Skylake X from Skylake 2018-06-03 23:41:33 +02:00
Arjan van de Ven
99c7bba8e4 Initial support for SkylakeX / AVX512 
This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.
 2018-06-03 07:58:52 +00:00
Isuru Fernando
2f12ea017b No strncasecmp with MSVC 2017-08-08 00:07:25 +05:30
Gian-Carlo Pascutto
9c884986ad Add an extra familiy/model combination used by AMD Steamrolller (Godavari). 2017-04-19 19:15:47 +02:00
Gian-Carlo Pascutto
0cbd2d34e4 Recognize ZEN when passed as OPENBLAS_CORETYPE. 2017-04-10 20:05:16 +02:00
Gian-Carlo Pascutto
62979fd104 Fix dynamic detection for ZEN CPUs. 2017-04-10 19:08:37 +02:00
Denis Steckelmacher
c9ff735da6 Add ZEN support (tested for auto-detected static backend) 2017-03-19 15:32:50 +01:00
Andrew
5088523786 detect apollo lake for real 2017-02-20 23:54:59 +01:00
Elliot Saba
1d8ab99e09 Add exfamily == 9 case (Kaby Lake) to dynamic arch detection 2017-02-10 15:23:55 -08:00
Martin Koehler
76c6e33e54 Enable EXCAVATOR kernels for A12-9800 2017-02-07 21:38:28 +01:00
Martin Kroeker
596ead0f8d Add files via upload 2016-11-06 23:26:39 +01:00
Martin Kroeker
8a8f3932eb Update dynamic.c 
Add Bay Trail "Pentium N3520" atom
 2016-10-16 22:40:00 +02:00
Martin Kroeker
7de829f713 Update dynamic.c 
Add Braswell (extended model 4, model 12) N3150 as Nehalem
 2016-07-14 12:22:55 +02:00
Werner Saar
2b967590a0 bugfix in dynamic.c 2016-04-25 09:08:38 +02:00
Zhang Xianyi
1edf30b790 Change Opteron(SSE3) to Opteron_SSE3 at dyanmaic core name. 2016-03-01 20:13:08 +08:00
Martin Kroeker
935356c34f Update dynamic.c and cpuid_x86.c for Intel Avoton. 
Second part of "support Intel Avoton via Nehalem kernel"
 2016-02-02 13:42:55 -05:00
Zhang Xianyi
839395fc25 Detect AMD Trinity and Richland. 2015-10-29 02:53:29 +08:00
Zhang Xianyi
cc7cab8a45 Detect other Intel Skylake cores. 
http://users.atw.hu/instlatx64/
 2015-09-09 10:47:17 -05:00
Yichao Yu
61ae47eb99 Ref #632. Support Intel Skylake by Haswell kernels. 2015-09-09 11:07:33 -04:00
Zhang Xianyi
51ff17d46e Add AMD Excavator target. 2015-05-13 16:16:30 -05:00
Zhang Xianyi
8977b3f235 Refs #529. Support Intel Broadwell by Haswell kernels. 2015-04-02 11:08:03 -05:00
Zhang Xianyi
e95d64333a Refs #519. Avoid calling strncpy. 2015-03-19 15:57:22 -05:00
Werner Saar
0dc559ed30 bugfix in dynamic.c 2014-12-28 17:15:42 +01:00
Werner Saar
4319769b79 added target processor STEAMROLLER 2014-12-28 20:16:46 +08:00
Zhang Xianyi
c94762bb56 Refs #401. Added NO_AVX2 flag for old binutils (e.g. RHEL6) 2014-07-16 08:38:25 +08:00
Timothy Gu
6c2ead30f0 Remove all trailing whitespace except lapack-netlib 
Signed-off-by: Timothy Gu <timothygu99@gmail.com>
 2014-06-27 12:05:18 -07:00
wernsaar
53bfa51ee0 Ref #385: fixed warnings in dynamic.c 2014-06-12 18:17:08 +02:00
wernsaar
a86d349a51 Ref #380: enhancements for dynamic_arch 2014-06-12 14:20:03 +02:00
Zhang Xianyi
8c7687b419 Refs #338. Added OPENBLAS_VERBOSE environment variable on runtime 
By default, OpenBLAS doesn't output the warning message. You can set
OPENBLAS_VERBOSE (e.g. export OPENBLAS_VERBOSE=1) to enable the warning
message on runtime.
 2014-01-24 02:05:59 +08:00
Zhang Xianyi
ab69443bd4 Refs #332. Added addtional Intel Ivy Bridge and Haswell CPU-id. 2014-01-05 23:44:29 +08:00
wernsaar
5c648a8984 Merge remote branch 'origin/develop' into haswell 2013-12-01 11:25:33 +01:00
Sébastien Villemot
eae4cfa3f6 Avoid failure on qemu guests declaring an Athlon CPU without 3dnow! 
The present patch verifies that, on machines declaring an Athlon CPU model and
family, the 3dnow and 3dnowext feature flags are indeed present. If they are
not, it fallbacks on the most generic x86 kernel. This prevents crashes due to
illegal instruction on qemu guests with a weird configuration.

Closes #272
 2013-08-28 14:29:42 +02:00