traz
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782205a693
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Add dgemm compiler Options in KERNEL.LOONGSON3A.
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2011-04-06 10:38:34 +00:00 |
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traz
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ac494c0d04
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New kernel in LOONGSON3A.
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2011-04-06 10:36:44 +00:00 |
Xianyi Zhang
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f405b5bcc5
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Fixed the bug about Loongson3A gsLQC1 & gsSQC1 instructions in daxpy kernel. Now daxpy is correct.
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2011-03-18 23:05:56 +00:00 |
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Wang Qian
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d5cffd506a
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Modified the default kernel makefile in MIPS64 arch.
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2011-03-07 11:23:12 +00:00 |
Xianyi Zhang
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5838f12995
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Support unalign address in daxpy on loongson3a simd..
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2011-03-05 10:17:10 +08:00 |
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Xianyi Zhang
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5444a3f8f7
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Unroll to 16 in daxpy on loongson3a.
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2011-03-04 17:50:17 +08:00 |
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Xianyi Zhang
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88cbfcc5b5
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Merge commit 'origin/x86' into loongson3a
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2011-03-04 14:11:52 +00:00 |
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Xianyi Zhang
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ce78abe37e
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Merge branch 'x86' of github.com:xianyi/OpenBLAS into x86
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2011-03-04 11:53:04 +08:00 |
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Xianyi Zhang
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8f1090d32a
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Support NO_LAPACK=1 to build the lib without LAPACK functions.
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2011-03-04 11:51:32 +08:00 |
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Xianyi
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272f62a2b6
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Changed movlps macro name in capital in x86/zdot_sse2.S file.
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2011-03-03 00:46:39 +08:00 |
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Xianyi
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36016fe349
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On x86 32bits, gcc 4.4.3 generated wrong codes (movsd) from movlps in zdot_sse2.S line 191.
This would casue zdotu & zdotc failures. Instead, use movlpd to walk around it. Fixed #8. Fixed #9.
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2011-03-02 18:45:43 +08:00 |
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Xianyi Zhang
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6eb02bbb9c
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Merge remote branch 'origin/x86' into loongson3a
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2011-03-02 13:52:05 +08:00 |
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Xianyi
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12214e1d0f
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Fixed #7. Modified axpy kernel codes to avoid unloop with incx==0 or incy==0 in x86 32bits arch.
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2011-02-23 20:08:34 +08:00 |
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Xianyi Zhang
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0cfd29a819
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Fixed #7. 1)Disable the multi-thread and 2) Modified kernel codes to avoid unloop in axpy function when incx==0 or incy==0.
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2011-02-21 00:24:21 +08:00 |
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Xianyi
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bfaa80c316
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fixed #4 csrot & drot returned the wrong result when incx==incy==0 on i686 arch.
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2011-02-18 03:00:58 +08:00 |
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Xianyi Zhang
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c5852d4e30
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fixed #4 csrot returned the wrong result when incx==incy==0.
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2011-02-16 23:39:43 +08:00 |
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Xianyi Zhang
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84ba64e65b
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fixed a bug in drot whe incx or incy equals to zero.
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2011-02-16 23:35:41 +08:00 |
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Xianyi Zhang
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1e671b49f3
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Did the experiment with Loongson 3A 128bit load & store instruction.
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2011-01-29 03:05:27 +08:00 |
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Xianyi Zhang
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77b7020d69
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changed prefetch order.
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2011-01-29 03:03:34 +08:00 |
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Xianyi Zhang
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e003b811ab
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load x & y contiguously in axpy.
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2011-01-28 11:18:50 +08:00 |
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Xianyi Zhang
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ebe2da8474
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Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A.
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2011-01-27 23:07:06 +08:00 |
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Xianyi Zhang
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c0b5992fab
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added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.
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2011-01-26 22:34:33 +08:00 |
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Xianyi Zhang
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342bbc3871
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Import GotoBLAS2 1.13 BSD version codes.
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2011-01-24 14:54:24 +00:00 |