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22 Commits

Author SHA1 Message Date
Martin Kroeker a34a0a7abc
Allow negative INCX (API change from version 3.10 of the reference implementation) 2023-08-10 16:56:52 +02:00
Martin Kroeker 76ef1672f8
Override DSDOT with generic code to get rid of qemu precision error 2023-07-19 22:31:07 +02:00
Xianyi Zhang e14a025bb1 Temporily walk around zaxpy vector kernel bug. 2023-06-28 11:17:38 +00:00
Martin Kroeker 772b0cc715
Fix early bailout 2023-06-27 16:12:27 +02:00
Martin Kroeker d6be5036d7
Fix IDAMAX 2023-06-26 21:19:33 +02:00
Martin Kroeker 1fe96f8da7
Fix failures to handle increments of zero 2023-06-25 22:36:57 +02:00
Martin Kroeker 73b30b1dec
Fix VLEV_FLOAT/VSEV_FLOAT macros to compile with t-head 2.6.1 2023-06-18 17:46:29 +02:00
Sergei Lewis cb0a70e0e2 dot.c early bail fix 2023-03-02 09:51:10 +00:00
Xianyi Zhang 968e1f51d8 Update RISC-V Intrinsic API. 2022-06-06 13:52:21 +08:00
Xianyi Zhang 45786b05da Merge branch 'develop' into risc-v 2022-02-28 11:48:02 +08:00
Wu Zhigang 92b7b949dd fix bug in zscal function 
memset can not be used in zscal because of
the stride parameters.

Signed-off-by: Wu Zhigang <zhigang.wu@starfivetech.com>
 2021-12-15 01:23:30 -08:00
Zhaofeng Li 590be3fae3 riscv64: Add Makefile 2021-06-07 22:55:56 +00:00
Zhaofeng Li 3521cd48cb RISCV64_GENERIC: Use generic kernel for DSDOT for better precision 
The implementation in `riscv64/dot.c` fails the `test_dsdot` test, and
the generic kernel seems to have better precision. Tested on SiFive
FU740 (HiFive Unmatched) and QEMU.

Also see #1469.
 2021-06-07 22:50:23 +00:00
Zhaofeng Li 1e0192a5cc riscv64/imin: Fix wrong comparison 
Same as #1990.
 2021-06-07 22:49:39 +00:00
damonyu ceb44bef14 update the intrinsic api to the offical name. 2021-04-27 11:12:29 +08:00
Xianyi Zhang a3cac9cca0 Update sgemm kernel 1x4 for C910. 2020-12-18 11:53:23 +08:00
Xianyi Zhang fc35b72ae1 Refs #2899 
Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910
 2020-11-10 09:38:04 +08:00
damonyu ef8e7d0279 Add the support for RISC-V Vector. 
Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266
 2020-10-15 16:09:02 +08:00
Xianyi Zhang 265ab484c8 Change default RISC-V 64-bit corename to RISCV64_GENERIC 
e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
 2020-02-27 14:46:15 +08:00
Xianyi Zhang 44020a42a4 Fixed compile bug for RV64. 2020-02-27 14:29:42 +08:00
Jerry Zhao 0ee395db35 Fixed TRMM and SYMM for RISCV 2018-04-18 18:03:32 -07:00
Jerry Zhao c167a3d6f4 Added RISCV build 2018-04-16 14:08:31 -07:00