3 Commits

Author	SHA1	Message	Date
Octavian Maghiar	8df0289db6	Adds tail undisturbed for RVV Level 1 operations ... During the last iteration of some RVV operations, accumulators can get overwritten when VL < VLMAX and tail policy is agnostic. Commit changes intrinsics tail policy to undistrubed.	2023-07-20 15:28:35 +01:00
Heller Zheng	1374a2d08b	This PR adapts latest spec changes ... Add prefix (_riscv) for all riscv intrinsics Update some intrinsics' parameter, like vfredxxxx, vmerge	2023-03-19 23:59:03 -07:00
Heller Zheng	bef47917bd	Initial version for riscv sifive x280	2022-11-15 00:06:25 -08:00