Commit Graph

17 Commits

Author SHA1 Message Date
Martin Kroeker d02c61e82e
Update lowercase cpunames for RISC-V 2024-02-04 10:01:27 +01:00
Martin Kroeker 7228c708d7
Merge pull request #4461 from markdryan/cpuid_riscv64_crash
Fix two issues with cpuid_riscv64.c
2024-02-04 09:57:00 +01:00
Mark Ryan e0b610d01f Harmonize riscv64 LIBNAME for forced and non-forced targets
The forced values for LIBNAME were either riscv64_generic or c910v
while the non-forced value of LIBNAME was always riscv64.
2024-01-26 15:18:18 +00:00
Mark Ryan ec2aa32eb0 Fix crash in cpuid_riscv64.c
The crash is reproducible when building OpenBLAS without forcing a
target in a riscv64 container running on an X86_64 machine with an
older version of QEMU, e.g., 7.0.0, registered with binfmt_misc to
run riscv64 binaries.  With this setup, cat /proc/cpuinfo in the
container returns the cpu information for the host, which contains a
"model name" string, and we execute the buggy code.  The code in
question is searching in an uninitialised buffer for the ':' character
and doesn't check to see whether it was found or not.  This can result
in pmodel containing the pointer value 1 and a crash when pmodel is
defererenced.  The algorithm to detect the C910V CPU has not been
modified, merely fixed to prevent the crash.

A few additional checks for NULL pointers are added to improve the
robustness of the code and a whitespace error is corrected.
2024-01-26 15:17:31 +00:00
Octavian Maghiar deecfb1a39 Merge branch 'risc-v' into img-riscv64-zvl128b 2024-01-19 12:26:38 +00:00
Sergei Lewis 9edb805e64 fix builds with t-head toolchains that use old versions of the intrinsics spec 2024-01-16 14:33:08 +00:00
Octavian Maghiar e4586e81b8 [RISC-V] Add RISC-V Vector 128-bit target
Current RVV x280 target depends on vlen=512-bits for Level 3 operations.
Commit adds generic target that supports vlen=128-bits.
New target uses the same scalable kernels as x280 for Level 1&2 operations, and autogenerated kernels for Level 3 operations.
Functional correctness of Level 3 operations tested on vlen=128-bits using QEMU v8.1.1 for ctests and BLAS-Tester.
2023-12-04 11:02:18 +00:00
Sergei Lewis 2406958629 * update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics)
* fix multiple numerical stability and corner case issues
* add a script to generate arbitrary gemm kernel shapes
* add a generic zvl256b target to demonstrate large gemm kernel unrolls
2023-02-24 10:45:03 +00:00
Heller Zheng bef47917bd Initial version for riscv sifive x280 2022-11-15 00:06:25 -08:00
Martin Kroeker ef9c976a94
Really fix compilation; fix crash when pmodel is not present in cpuinfo 2022-07-31 00:41:04 +02:00
Martin Kroeker 30df29c0b3
Fix compilation 2022-05-19 18:57:46 +02:00
Han Gao 8dd4579480 riscv: Fix machine recognition for c910v
Signed-off-by: Han Gao <gaohan@uniontech.com>
2022-05-19 17:32:48 +08:00
Martin Kroeker 46d22150de
Initial attempt at proper cpu detection on RISCV 2022-05-04 08:58:56 +02:00
Han Gao 8123324c99 Fix riscv64 arch detect
Signed-off-by: Han Gao <gaohan@uniontech.com>
2022-04-27 02:29:43 +08:00
Xianyi Zhang fc35b72ae1 Refs #2899
Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910
2020-11-10 09:38:04 +08:00
damonyu ef8e7d0279 Add the support for RISC-V Vector.
Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266
2020-10-15 16:09:02 +08:00
Jerry Zhao c167a3d6f4 Added RISCV build 2018-04-16 14:08:31 -07:00