Shivraj Patil
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2c3dfe2bf3
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MIPS P5600(32 bit) and I6400(64 bit) cores support added.
Seperated mips and mips64 files.
Configurations support for mips 32 bit.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
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2016-04-22 14:03:18 +05:30 |
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Ashwin Sekhar T K
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f2f8a0fe8b
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Adding arm64 target CORTEXA57
Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
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2015-11-09 14:15:50 +05:30 |
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Fábio Perez
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b8d64a856a
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Add POWER7/POWER8 as targets
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2015-08-05 11:02:39 -03:00 |
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Zhang Xianyi
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51ff17d46e
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Add AMD Excavator target.
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2015-05-13 16:16:30 -05:00 |
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Zhang Xianyi
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c674fa32be
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Add ARM targets.
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2015-03-24 12:17:04 -05:00 |
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Werner Saar
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4319769b79
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added target processor STEAMROLLER
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2014-12-28 20:16:46 +08:00 |
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Zhang Xianyi
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70d1ba09b2
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Update the doc for target list.
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2014-09-17 14:29:21 +08:00 |
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Eliot Eshelman
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9912dbbcf9
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Add HASWELL to TargetList.txt
The Intel "Haswell" architecture is missing from the list of build targets.
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2014-09-16 18:26:45 -04:00 |
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Explorer09
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309f90e563
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TargetList.txt: minor re-ordering
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2013-03-17 23:03:05 +08:00 |
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Zhang Xianyi
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bfaaa975e6
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Added BULLDOZER target. So far it uses barcelona kernels.
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2012-12-07 00:53:31 +08:00 |
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Zhang Xianyi
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d3b67d0bd8
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Refs #113. Fixed the typo BOBCATE -> BOBCAT
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2012-05-31 22:40:15 +08:00 |
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Zhang Xianyi
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d6cab3f37e
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Refs #113. Support AMD Bobcate using Barcelona kernel codes. Replace 3DNow! with MMX.
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2012-05-31 18:17:45 +08:00 |
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Xianyi Zhang
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19a48b82cf
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Init Sandybridge codes based on Nehalem.
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2012-03-30 20:01:03 +08:00 |
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Xianyi Zhang
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b8d93812f0
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Added docs for make TARGET=your_cpu_target.
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2011-04-22 22:07:46 +08:00 |
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