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Commit Graph

98 Commits

Author SHA1 Message Date
Martin Kroeker
faae86fba2 Add CPUIDs for Alder Lake and some other recent Intel cpus 2021-11-04 20:35:41 +01:00
Neutron3529
ead476025d auto-detect for Intel i7-11800H 2021-10-27 14:16:37 +08:00
Wangyang Guo
3dc6052c7e initial support for Sapphire Rapids platform 2021-10-12 01:30:40 -07:00
JonasZhou
0fca36c8c3 Add cpu detection support for Zhaoxin processors 
Signed-off-by: JonasZhou <JonasZhou@zhaoxin.com>
 2021-07-12 13:43:45 +08:00
Martin Kroeker
4f4e286bf6 Fix copy-paste error in LIBCORE assignment for Tiger Lake 2021-07-10 18:20:40 +02:00
Martin Kroeker
da623ae838 Add vendor string Shanghai as the successor to Centaur 2021-07-08 18:26:23 +02:00
Martin Kroeker
0d8d261dd4 Recognize newer Zhaoxin/Centaur cpus as Nehalem 2021-07-08 12:20:19 +02:00
Martin Kroeker
26e87ac517 Support Intel Ice Lake SP as Cooper Lake 2021-05-14 20:39:55 +02:00
Martin Kroeker
ae53e3e233 Recognize Intel Tiger Lake as SkylakeX 2021-02-11 20:16:27 +01:00
Martin Kroeker
0f7776af0b Add Intel Rocket Lake 2020-12-14 22:30:36 +01:00
Guillaume Horel
1f564d729b fix avx2 detection 
reword commits to make it clearer
 2020-10-31 10:00:48 -04:00
Chen, Guobing
e740c4873d Enable COOPERLAKE build target 
Enable new build target platform -- COOPERLAKE. This target platform
supports all the SKYLAKEX supported ISAs + avx512bf16. So all the
SKYLAKEX specific kernels/drivers and related code are now extended
to be also active on COOPERLAKE. Besides, new BF16 related kernels
are active under this target.
 2020-08-13 06:18:00 +08:00
Martin Kroeker
200f5c44cc Add AMD Renoir models and preliminary support for ZEN3 as ZEN2 
also remap erroneous family 16 entry to BOBCAT and reclaim erroneous family 25 "Barcelona" for Zen3
 2020-07-28 13:45:23 +00:00
Martin Kroeker
83f4746825 Add support for Comet Lake H and S 2020-06-27 14:41:24 +02:00
Matthew Treinish
2f9c10810c Also set CPUTYPE in get_cpuname() 2020-06-25 15:53:56 -04:00
Matthew Treinish
2a91452bdd Add cpu detection support for comet lake U 
Comet Lake U CPUs have family: 6, model: 6, extended family: 0, and
extended model: 10 were not being correctly detected by GETARCH during
openblas builds and would show CORE=UNKNOWN and LIBCORE=unknown. This
commit adds the necessary information to cpuid_x86 to detect extended
family 10 model 6 and return the proper core information. It's
essentially just a skylake cpu, not skylake x, so I just took the used
the same return fields as skylake.
 2020-06-25 11:32:09 -04:00
Martin Kroeker
303bdb673b Fix coretype detection for Intel extended models 6 and 7 
affecting Goldmont, Cannon Lake, Ice Lake autodetection
 2020-02-10 19:17:32 +01:00
Martin Kroeker
e9437eebd2 Restore Goldmont ID and improve QEMU support 
#2283 had inadvertently removed Goldmont+, and cpuid was reporting a mix of Core2 and Pentium2 for some QEMU configurations
 2019-10-24 18:45:27 +02:00
Martin Kroeker
e8a2aed2b9 Support QEMU cpu calling itself 64bit AMD Athlon as well 
Some QEMU instances pretend to be "AuthenticAMD" with the same family 6/model 6 even when running on an Intel host
(could be related to qemu or libvirt version and/or kvm availability). Also fix the define to depend on __x86_64__ set by the
compiler, the defines using __64BIT__ will only work for getarch_2nd.
 2019-10-09 18:24:13 +02:00
Martin Kroeker
f262031685 Support QEMU virtual cpu as CORE2 
qemu itself claims it is a 64bit P6, which does not exist in the wild.
 2019-10-08 22:30:02 +02:00
Martin Kroeker
6d8595351c Add Intel Goldmont Plus CPUID 
fixes #2227
 2019-08-19 14:19:21 +02:00
Martin Kroeker
b1393c7a97 Add Intel Denverton 
for #2048
 2019-03-12 16:03:56 +01:00
Martin Kroeker
83b5c6b92d Fix compilation with NO_AVX=1 set 
fixes #1974
 2019-01-20 12:18:53 +01:00
caiyu
29dc72889f Add support for Hygon Dhyana 2019-01-16 14:25:19 +08:00
Martin Kroeker
00401489c2 Fix missing braces in support_avx() 2019-01-14 22:38:32 +01:00
Martin Kroeker
68eb3146ce Add xcr0 (os support) check 2019-01-05 18:07:14 +01:00
Martin Kroeker
0afaae4b23 Query AVX2 and AVX512VL capability in x86 cpu detection 2019-01-05 16:58:56 +01:00
TiborGY
211120c508 Fix typo in UNKNOWN core name 
Should be of no consequence, right?
 2018-12-27 23:09:21 +01:00
Martin Kroeker
64ca44873b Fix detection of Ryzen2 (missing CORE_ZEN) 2018-10-28 18:36:55 +01:00
Martin Kroeker
3f73e8b8cf Add cpuid for AMD Ryzen 2 
for #1664
 2018-07-03 21:01:35 +02:00
Martin Kroeker
2d8cc7193a Support upcoming Intel Cannon Lake CPUs as Skylake X (#1621) 
* Support  upcoming Cannon Lake as Skylake X
 2018-06-17 23:38:14 +02:00
Martin Kroeker
dc9fe05ab5 Update cpuid_x86.c 2018-06-04 17:10:19 +02:00
Martin Kroeker
5a92b311e0 Separate Skylake X from Skylake 2018-06-03 23:29:07 +02:00
Arjan van de Ven
99c7bba8e4 Initial support for SkylakeX / AVX512 
This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.
 2018-06-03 07:58:52 +00:00
Martin Kroeker
aece65ea29 Fix coretype detection for Bay Trail Atom 
My earlier PR #982 appears to have been incomplete in this regard - fixes #1285
 2017-08-27 13:06:54 +02:00
Martin Kroeker
00774b1105 Add dummy implementation of cpuid_count for the CPUIDEMU case 2017-07-12 21:56:23 +02:00
Martin Kroeker
6497aae57c Use cpuid 4 with subleafs to query L1 cache size on Intel processors 2017-07-12 20:43:09 +02:00
Gian-Carlo Pascutto
9c884986ad Add an extra familiy/model combination used by AMD Steamrolller (Godavari). 2017-04-19 19:15:47 +02:00
Johannes Buchner
b4071d0d16 Autodetect AMD A8-6410 as BARCELONA 2017-04-03 17:07:27 +10:00
Denis Steckelmacher
c9ff735da6 Add ZEN support (tested for auto-detected static backend) 2017-03-19 15:32:50 +01:00
Martin Kroeker
688267edf3 Fix core detection for Kaby Lake without AVX (G4560) 
Should fix #1109)
 2017-03-02 17:36:16 +01:00
Elliot Saba
04b2b06665 CPUID mappings for Core i5-7600K (Kaby Lake) 2017-02-10 14:53:15 -08:00
Martin Koehler
76c6e33e54 Enable EXCAVATOR kernels for A12-9800 2017-02-07 21:38:28 +01:00
Martin Kroeker
60816c9259 Add files via upload 2016-11-06 23:26:04 +01:00
Martin Kroeker
3409bccb21 Update cpuid_x86.c 
Add Bay Trail "Pentium N3520" atom cpu
 2016-10-16 22:45:44 +02:00
Martin Kroeker
154729908e Update cpuid_x86.c 2016-07-14 17:29:34 +02:00
Martin Kroeker
97bd1e42c8 Update cpuid_x86.c 2016-07-14 12:25:17 +02:00
Martin Kroeker
935356c34f Update dynamic.c and cpuid_x86.c for Intel Avoton. 
Second part of "support Intel Avoton via Nehalem kernel"
 2016-02-02 13:42:55 -05:00
Martin Kroeker
4f05c23673 Update cpuid_x86.c 
Add recognition of Intel Atom C27xx (Avoton, model code 4D)
 2016-02-02 13:38:01 -05:00
Jerome Robert
76398c3233 Fix detection of AMD E2-3200 2015-12-28 19:45:47 +01:00